Park, et al., Evaluation of Scheduling Techniques on a SPARC-Based VLIW Testbed, Proceedings of the 30th Annual International Symposium on Microarchitecture, Dec. 1997. |
Moreno, et al., Simulation/evaluation environment for a VLIW processor architecture, IBM Journal of Research and Development, vol. 41, No. 3 Received Aug. 8, 1996; accepted for publication Mar. 18, 1997. |
Lichtenstein, et al., Model Based Test Generation for Processor Design Verification, Sixth Innovative Applications of Artificial Intelligence Conference, Aug. 1994. |
Lichtenstein, et al., Test Program Generation for Functional Verification of PowerPC processors in IBM, IEEE/ACM 32'nd Design Automation Conference, Jun. 1995. |
Aharon, et al., Verification of the IBM RISC System/6000 by a dynamic biased pseudo-random test program generator, published in IBM Systems Journal, vol. 30, No. 4, 1991. |
Casaubieilh, et al., Functional verification methodology of Chameleon processor, presented at the 33rd Annual ACM IEEE Design Automation Conference, Jun. 3-7, 1996. |
Bellon, et al., Automatic Generation of Microprocessor Test Programs, presented at ACM IEEE Nineteenth Design Automation Conference Proceedings, Jun., 1982. |
Anderson, Logical Verification of the NVAX CPU Chip Design, Digital Technical Journal of Digital Equipment Corporation, vol. 4 No. 3, Summer 1992. |
Chandra, et al., Constraint Solving for Test Case Generation—A Technique for High Level Design Verification, published in: International Conference on Computer Design: VLSI in Computers and Processors, Proceedings. Los Alamitos, IEEE Computer Society Press, 1992. |
Logan, et al., Directions in Multiprocessor Verification, presented at the 14th Annual IEEE International Phoenix Conference on Computers and Communications, Mar., 1995. |
Raghavan, et al., Multiprocessor System Verification Through Behavioral Modeling and Simulation, presented at the 14th Annual IEEE International Phoenix Conference on Computers and Communications, Mar., 1995. |
Saha, et al., A Simulation-Based Approach to Architectural Verification of Multiprocessor Systems, presented at the 14th Annual IEEE International Phoenix Conference on Computers and Communications, Mar., 1995. |