Claims
- 1. An apparatus comprising:
a first circuit to generate a data signal containing data, and a second circuit to utilize said data, the first and second circuits being commonly clocked by a latch signal; and a circuit having a first level sensitive latch to latch the data signal from the first circuit upon receiving by way of a delay circuit the latch signal, and a second level sensitive latch to latch an output signal of the first level sensitive latch to the second circuit upon receiving the latch signal.
- 2. The apparatus of claim 1 in which the circuit is to invert the latch signal received by way of the delay so that the latch signal as received by the first level sensitive latch is both delayed and inverted relative to the one received by the second level sensitive latch.
- 3. The apparatus of claim 1 in which the circuit is further adapted to latch the data signal in accordance with a load signal.
- 4. A computer system comprising:
a processor; a first circuit to produce a signal as a result of execution of an instruction by the processor; a second circuit to use the signal, wherein the first and second circuits share a common clock node that is to receive a latch signal; and a third circuit to latch the signal upon receiving by way of a delay circuit the latch signal, the third circuit to -output a latched signal to the second circuit upon receiving the latch signal.
- 5. The system of claim 4 in which the circuit is to invert the latch signal received by way of the delay, relative to how the latch signal is used to output the latched signal to the second circuit.
- 6. The system of claim 4 in which the circuit is to latch the data signal in accordance with a load signal.
- 7. The system of claim 4 wherein the third circuit includes a flip flop and the delay circuit is to provide a time delay sufficient to meet a set-up time of the flip flop.
- 8. A circuit comprising:
first means for sampling an input signal; second means for sampling an output of the first sampler means; and means for extending a sampling interval of the first sampler means so that valid data in the input signal is sampled by the first sampler means without proportionally delaying the time at which said valid data appears at an output of the second sampler means.
- 9. The circuit of claim 8 further comprising means for controlling whether or not the first sampler means is to sample the input signal.
- 10. The circuit of claim 8 further comprising:
means for sourcing said valid data in the input signal; and means for using said valid data from the output of the second sampler means.
Parent Case Info
[0001] This is a divisional application of U.S. Ser. No. 09/453,669 filed Dec. 3, 1999.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09453669 |
Dec 1999 |
US |
Child |
10752770 |
Jan 2004 |
US |