Patent Application
20230019974
Cloud computing provides access to servers, storage, databases, and a broad set of application services over the Internet. A cloud service provider offers cloud services such as network services and business applications that are hosted in servers in one or more data centers that can be accessed by companies or individuals over the Internet. Hyperscale cloud-service providers typically have hundreds of thousands of servers. Each server in a hyperscale cloud includes storage devices to store user data, for example, user data for business intelligence, data mining, analytics, social media and micro-services. The cloud service provider generates revenue from companies and individuals (also referred to as tenants) that use the cloud services.
Disaggregated computing or Composable Disaggregated Infrastructure (CDI) is an emerging technology that makes use of high bandwidth, low-latency interconnects to aggregate compute, storage, memory, and networking fabric resources into shared resource pools that can be provisioned on demand.
Features of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, in which like numerals depict like parts, and in which:
Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.
High speed networks are essential for supporting business, providing communication, and delivering entertainment. To increase network speed, Cloud service providers (CSPs) are evolving their hardware platforms by offering central processing units (CPUs), general purpose graphics processing units (GPGPUs), custom XPUs, and pooled storage and memory (for example, DDR, persistent memory, 3D XPoint, Optane, or memory devices that use chalcogenide glass). CSPs are vertically integrating these with custom orchestration control planes to expose these as services to users.
Growth in cloud native, scale out in applications, emergence of Compute Express Link (CXL) based protocols to stitch together systems and resources across multiple platforms, and increased and enhanced usages and capabilities offered by XPUs (for example, GPUs and Infrastructure Processing Units (IPUs)) have led a shift from core and CPU focused computing, to computing that spans multiple platforms and even multiple datacenters at times.
A network device, for example, an Infrastructure Processing Unit (IPU), data processing unit (DPU) or Smart Network Interface Controller (NIC) may experience long periods of idleness while the network pipeline is in an active state of operation.
These periods of idleness in the data center while in active state, is an opportunity to save power and therefore the cost of operating the data center while a packet processing pipeline is in an idle state. A continuous, fully-active workload does not present an opportunity for idle power savings in the packet processing pipeline. A long-duration period of idleness is typically managed by data center high-level power management such as migration and shutdown.
However, dynamic workloads have brief, unpredictable idle intervals. Idle intervals of sufficient duration for dynamic workloads can be detected by a network device. The network device can place some or all of the packet processing pipeline into a low-power state for the detected idle intervals of sufficient duration.
The network device detects idleness greater than a critical duration and automatically engages a low-power mode involving clock throttling and/or clock gating. The power savings along the packet processing pipeline in the network device is based on the average long-term residency in idleness. The idle power is reduced for the packet processing pipeline in the network device based on average long-term idleness as a function of the minimum latency of the packet processing pipeline, which is used to reduce the clock rate of the packet processing pipeline, thereby resulting in power savings for the network device. Idleness detection can be performed in one or more packet processing pipeline stages (for example, infra-structure networking stack and/or in-line crypto engine) or across all packet processing pipeline stages in the packet processing pipeline.
Various embodiments and aspects of the inventions will be described with reference to details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of the invention and are not to be construed as limiting the invention. Numerous specific details are described to provide a thorough understanding of various embodiments of the present invention. However, in certain instances, well-known or conventional details are not described in to provide a concise discussion of embodiments of the present inventions.
Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in conjunction with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment.
Various examples described herein can perform an application composed of microservices, where each microservice runs in its own process and communicates using protocols (e.g., application program interface (API), a Hypertext Transfer Protocol (HTTP) resource API, message service, remote procedure calls (RPC), or Google RPC (gRPC)). Microservices can be independently deployed using centralized management of these services. The management system may be written in different programming languages and use different data storage technologies. A microservice can be characterized by one or more of: use of fine-grained interfaces (to independently deployable services), polyglot programming (e.g., code written in multiple languages to capture additional functionality and efficiency not available in a single language), or lightweight container or virtual machine deployment, and decentralized continuous microservice delivery. One or more microservices can execute on or use any resources described herein, such as resources of
In the illustrative embodiment, the nodes in each system 110, 120, 130, 140 are connected to multiple system switches (e.g., switches that route data communications to and from nodes within the system). Switches can be positioned at the top of rack (TOR), end of row (EOR), middle of rack (MOR), or other. The system switches, in turn, connect with spine switches 150 that switch communications among systems (e.g., the systems 110, 120, 130, 140) in the data center 100. In some embodiments, the nodes may be connected with a fabric using standards described herein or proprietary standards. In other embodiments, the nodes may be connected with other fabrics, such as InfiniBand or Ethernet or optical. As described in more detail herein, resources within nodes in the data center 100 may be allocated to a group (referred to herein as a “managed node”) containing resources from one or more nodes to be collectively utilized in the execution of a workload. The workload can execute as if the resources belonging to the managed node were located on the same node. The resources in a managed node may belong to nodes belonging to different racks, and even to different systems 110, 120, 130, 140. As such, some resources of a single node may be allocated to one managed node while other resources of the same node are allocated to a different managed node (e.g., one processor assigned to one managed node and another processor of the same node assigned to a different managed node).
The disaggregation of resources to nodes comprised predominantly of a single type of resource (e.g., compute nodes comprising primarily compute resources, memory nodes containing primarily memory resources), and the selective allocation and deallocation of the disaggregated resources to form a managed node assigned to execute a workload improves the operation and resource usage of the data center 100 relative to typical data centers comprised of hyperconverged servers containing compute, memory, storage and perhaps additional resources. For example, because nodes predominantly contain resources of a particular type, resources of a given type can be upgraded independently of other resources. Additionally, because different resource types (processors, memory, storage, accelerators, etc.) typically have different refresh rates, greater resource utilization, and reduced total cost of ownership may be achieved. For example, a data center operator can upgrade the processors throughout their facility by only swapping out the compute nodes. In such a case, accelerator and storage resources may not be contemporaneously upgraded and, rather, may be allowed to continue operating until those resources are scheduled for their own refresh. Resource utilization may also increase. For example, if managed nodes are composed based on requirements of the workloads that will be running on them, resources within a node are more likely to be fully utilized. Such utilization may allow for more managed nodes to run in a data center with a given set of resources, or for a data center expected to run a given set of workloads, to be built using fewer resources.
It should be appreciated that each of the other systems 120, 130, 140 (as well as additional systems of the data center 100) may be similarly structured as, and have components similar to, the system 110 shown in and described in regard to
Referring now to
Although two physical resources 320 are shown in
The node 300 also includes one or more additional physical resources 330 mounted to circuit board substrate 302. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of the node 300, the physical resources 330 may include additional or other electrical components, circuits, and/or devices in other embodiments.
The physical resources 320 can be communicatively coupled to the physical resources 330 via an Input/Output (I/O) subsystem 322. The I/O subsystem 322 may be embodied as circuitry and/or components to facilitate Input/Output operations with the physical resources 320, the physical resources 330, and/or other components of the node 300. For example, the I/O subsystem 322 may be embodied as, or otherwise include, memory controller hubs, Input/Output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, waveguides, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the Input/Output operations. In the illustrative embodiment for memory system, the I/O subsystem 322 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDR5 data bus.
In some embodiments, the node 300 may also include a resource-to-resource interconnect 324. The resource-to-resource interconnect 324 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 324 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 322). For example, the resource-to-resource interconnect 324 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), PCI express (PCIe), or other high-speed point-to-point interconnect utilized for resource-to-resource communications.
The node 300 also includes a power connector 340 configured to mate with a corresponding power connector of the rack 240 when the node 300 is mounted in the corresponding rack 240. The node 300 receives power from a power supply of the rack 240 via the power connector 340 to supply power to the various electrical components of the node 300. In some examples, the node 300 includes local power supply (e.g., an on-board power supply) to provide power to the electrical components of the node 300. In some examples, the node 300 does not include any local power supply (e.g., an on-board power supply) to provide power to the electrical components of the node 300. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the circuit board substrate 302, which may increase the thermal cooling characteristics of the various electrical components mounted on the circuit board substrate 302 as discussed above. In some embodiments, voltage regulators are placed on circuit board substrate 302 directly opposite of the processors 520 (see
In some embodiments, the node 300 may also include mounting features 342 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the node 300 in a rack 240 by the robot. The mounting features 342 may be embodied as any type of physical structures that allow the robot to grasp the node 300 without damaging the circuit board substrate 302 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 342 may be embodied as non-conductive pads attached to the circuit board substrate 302. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the circuit board substrate 302. The particular number, shape, size, and/or make-up of the mounting feature 342 may depend on the design of the robot configured to manage the node 300.
Referring now to
The memory devices 420 may be embodied as any type of memory device capable of storing data for the physical resources 320 during operation of the node 300, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or nonvolatile memory.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies, for example, multi-threshold level NAND flash memory and NOR flash memory. A block can be any size such as but not limited to 2KB, 4KB, 5KB, and so forth. A memory device may also include next-generation nonvolatile devices, such as Intel Optane® memory or other byte addressable write-in-place nonvolatile memory devices (e.g., memory devices that use chalcogenide glass), multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of one or more of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
Referring now to
In some embodiments, the compute node 500 may also include a processor-to-processor interconnect 542. Processor-to-processor interconnect 542 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 542 communications. In the illustrative embodiment, the processor-to-processor interconnect 542 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 322). For example, the processor-to-processor interconnect 542 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect utilized for processor-to-processor communications (e.g., PCIe or CXL).
The compute node 500 also includes a communication circuit 530. The illustrative communication circuit 530 includes a network interface controller (NIC) 532, which may also be referred to as a host fabric interface (HFI). The NIC 532 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, or other devices that may be used by the compute node 500 to connect with another compute device (e.g., with other nodes 300). In some embodiments, the NIC 532 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 532 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 532. In such embodiments, the local processor of the NIC 532 may be capable of performing one or more of the functions of the processors 520. Additionally or alternatively, in such embodiments, the local memory of the NIC 532 may be integrated into one or more components of the compute node 500 at the board level, socket level, chip level, and/or other levels. In some examples, a network interface includes a network interface controller or a network interface card. In some examples, a network interface can include one or more of a network interface controller (NIC) 532, a host fabric interface (HFI), a host bus adapter (HBA), network interface connected to a bus or connection (e.g., PCIe, CXL, DDR, and so forth). In some examples, a network interface can be part of a switch or a system-on-chip (SoC).
Some examples of a NIC 532 are part of an Infrastructure Processing Unit (IPU) or data processing unit (DPU) or utilized by an IPU or DPU. An IPU or DPU can include a network interface, memory devices, and one or more programmable or fixed function processors (e.g., CPU or XPU) to perform offload of operations that could have been performed by a host CPU or XPU or remote CPU or XPU. In some examples, the IPU or DPU can perform virtual switch operations, manage storage transactions (e.g., compression, cryptography, virtualization), and manage operations performed on other IPUs, DPUs, servers, or devices.
The communication circuit 530 is communicatively coupled to an optical data connector 534. The optical data connector 534 is configured to mate with a corresponding optical data connector of a rack when the compute node 500 is mounted in the rack. Illustratively, the optical data connector 534 includes a plurality of optical fibers which lead from a mating surface of the optical data connector 534 to an optical transceiver 536. The optical transceiver 536 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector 534 in the illustrative embodiment, the optical transceiver 536 may form a portion of the communication circuit 530 in other embodiments.
In some embodiments, the compute node 500 may also include an expansion connector 540. In such embodiments, the expansion connector 540 is configured to mate with a corresponding connector of an expansion circuit board substrate to provide additional physical resources to the compute node 500. The additional physical resources may be used, for example, by the processors 520 during operation of the compute node 500. The expansion circuit board substrate may be substantially similar to the circuit board substrate 302 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion circuit board substrate may depend on the intended functionality of the expansion circuit board substrate. For example, the expansion circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits. Note that reference to GPU or CPU herein can in addition or alternatively refer to an XPU or xPU. An xPU can include one or more of: a GPU, ASIC, FPGA, or accelerator device.
Referring now to
In the illustrative accelerator node 600, the physical resources 320 are embodied as accelerator circuits 620. Although only two accelerator circuits 620 are shown in
In some embodiments, the accelerator node 600 may also include an accelerator-to-accelerator interconnect 642. Similar to the resource-to-resource interconnect 324 of the node 300 discussed above, the accelerator-to-accelerator interconnect 642 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 642 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 322). For example, the accelerator-to-accelerator interconnect 642 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect utilized for accelerator-to-accelerator communications. In some embodiments, the accelerator circuits 620 may be daisy-chained with a primary accelerator circuit 620 connected to the NIC 532 and memory 420 through the I/O subsystem 322 and a secondary accelerator circuit 620 connected to the NIC 532 and memory 420 through a primary accelerator circuit 620.
Referring now to
In the illustrative storage node 700, the physical resources 320 are embodied as storage controllers 720. Although only two storage controllers 720 are shown in
In some embodiments, the storage node 700 may also include a controller-to-controller interconnect 742. Similar to the resource-to-resource interconnect 324 of the node 300 discussed above, the controller-to-controller interconnect 742 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 742 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 322). For example, the controller-to-controller interconnect 742 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect utilized for controller-to-controller communications.
Referring now to
In the illustrative memory node 800, the physical resources 320 are embodied as memory controllers 820. Although only two memory controllers 820 are shown in
In some embodiments, the memory node 800 may also include a controller-to-controller interconnect 842. Similar to the resource-to-resource interconnect 324 of the node 300 discussed above, the controller-to-controller interconnect 842 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 322). For example, the controller-to-controller interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect utilized for controller-to-controller communications. As such, in some embodiments, a memory controller 820 may access, through the controller-to-controller interconnect 842, memory that is within the memory set 832 associated with another memory controller 820. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory node (e.g., the memory node 800). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, the memory controllers 820 may implement a memory interleave (e.g., one memory address is mapped to the memory set 830, the next memory address is mapped to the memory set 832, and the third address is mapped to the memory set 830, etc.). The interleaving may be managed within the memory controllers 820, or from CPU sockets (e.g., of the compute node 500) across network links to the memory sets 830, 832, and may improve the latency and bandwidth associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.
Further, in some embodiments, the memory node 800 may be connected to one or more other nodes 300 (e.g., in the same rack 240 or an adjacent rack 240) through a waveguide, using the waveguide connector 880. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 830, 832) to another node (e.g., a node 300 in the same rack 240 or an adjacent rack 240 as the memory node 800) without adding to the load on the optical data connector 534.
Referring now to
The managed node 970 may be embodied as an assembly of physical resources 320, such as processors 520, memory resources 420, accelerator circuits 620, or data storage 750, from the same or different nodes 300. Further, the managed node 970 may be established, defined, or “spun up” by the orchestrator server 920 at the time a workload is to be assigned to the managed node 970, and may exist regardless of whether a workload is presently assigned to the managed node 970. In the illustrative embodiment, the orchestrator server 920 may selectively allocate and/or deallocate physical resources 320 from the nodes 300 and/or add or remove one or more nodes 300 from the managed node 970 as a function of quality of service (QoS) targets (e.g., a target throughput, a target latency, a target number of instructions per second, etc.) associated with a service level agreement or class of service (COS or CLOS) for the workload (e.g., the application 932). In doing so, the orchestrator server 920 may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in each node 300 of the managed node 970 and compare the telemetry data to the quality-of-service targets to determine whether the quality of service targets are being satisfied. The orchestrator server 920 may additionally determine whether one or more physical resources may be deallocated from the managed node 970 while still satisfying the QoS targets, thereby freeing up those physical resources for use in another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not presently satisfied, the orchestrator server 920 may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application 932) while the workload is executing. Similarly, the orchestrator server 920 may determine to dynamically deallocate physical resources from a managed node 970 if the orchestrator server 920 determines that deallocating the physical resource would result in QoS targets still being met.
Additionally, in some embodiments, the orchestrator server 920 may identify trends in the resource utilization of the workload (e.g., the application 932), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 932) and pre-emptively identifying available resources in the data center and allocating them to the managed node 970 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, the orchestrator server 920 may model performance based on various latencies and a distribution scheme to place workloads among compute nodes 930 and other resources (e.g., accelerator nodes, memory nodes, storage nodes) in the data center. For example, the orchestrator server 920 may utilize a model that accounts for the performance, including optionally previously collected historical performance, of resources on the nodes 300 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server 920 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute node executing the workload and the node 300 on which the resource is located).
In some embodiments, the orchestrator server 920 may generate a map of heat generation in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the nodes 300 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center 100. Additionally or alternatively, in some embodiments, the orchestrator server 920 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server 920 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center 100. In some embodiments, the orchestrator server 920 may identify patterns in resource utilization phases of the workloads and use the patterns to predict future resource utilization of the workloads.
To reduce the computational load on the orchestrator server 920 and the data transfer load on the network, in some embodiments, the orchestrator server 920 may send self-test information to the nodes 300 to enable each node 300 to locally (e.g., on the node 300) determine whether telemetry data generated by the node 300 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each node 300 may then report back a simplified result (e.g., yes or no) to the orchestrator server 920, which the orchestrator server 920 may utilize in determining the allocation of resources to managed nodes.
Embodiments described herein can be used in a data center or disaggregated composite nodes. The techniques described herein can apply to both disaggregated and traditional server architectures. A traditional server can include a CPU, XPU, one or more memory devices, networking communicatively coupled to one or more circuit boards within a server.
Edge computing, at a general level, refers to the implementation, coordination, and use of computing and resources at locations closer to the “edge” or collection of “edges” of the network. The purpose of this arrangement is to improve total cost of ownership, reduce application and network latency, reduce network backhaul traffic and associated energy consumption, improve service capabilities, and improve compliance with security or data privacy requirements (especially as compared to conventional cloud computing). Components that can perform edge computing operations (“edge nodes”) can reside in whatever location needed by the system architecture or ad hoc service (e.g., in a high-performance compute data center or cloud installation; a designated edge node server, an enterprise server, a roadside server, a telecom central office; or a local or peer at-the-edge device being served consuming edge services).
With the illustrative edge networking systems described below, computing and storage resources are moved closer to the edge of the network (e.g., closer to the clients, endpoint devices, or “things”). By moving the computing and storage resources closer to the device producing or using the data, various latency, compliance, and/or monetary or resource cost constraints may be achievable relative to a standard networked (e.g., cloud computing) system. To do so, in some examples, pools of compute, memory, and/or storage resources may be located in, or otherwise equipped with, local servers, routers, and/or other network equipment. Such local resources facilitate the satisfying of constraints placed on the system. For example, the local compute and storage resources allow an edge system to perform computations in real-time or near real-time, which may be a consideration in low latency user-cases such as autonomous driving, video surveillance, and mobile media consumption. Additionally, these resources will benefit from service management in an edge system which provides the ability to scale and achieve local service level agreements (SLAs) or service level objectives (SLOs), manage tiered service requirements, and enable local features and functions on a temporary or permanent basis.
A pool can include a device on a same chassis or different physically dispersed devices on different chassis or different racks. A resource pool can include homogeneous processors, homogeneous processors, and/or a memory pool. Pooling of heterogeneous resources can be implemented using multiple homogeneous resource pools.
An illustrative edge computing system may support and/or provide various services to endpoint devices (e.g., client user equipment (UEs)), each of which may have different requirements or constraints. For example, some services may have priority or quality-of-service (QoS) constraints (e.g., traffic data for autonomous vehicles may have a higher priority than temperature sensor data), reliability and resiliency (e.g., traffic data may require mission-critical reliability, while temperature data may be allowed some error variance), as well as power, cooling, and form-factor constraints. These and other technical constraints may offer significant complexity and technical challenges when applied in the multi-stakeholder setting.
For example, the client compute nodes 1002 are located at an endpoint layer, while the edge gateway nodes 1012 are located at an edge devices layer (local level) of the edge computing system 1000. Additionally, the edge aggregation nodes 1022 (and/or fog devices 1024, if arranged or operated with or among a fog networking configuration 1026) are located at a network access layer (an intermediate level). Fog computing (or “fogging”) generally refers to extensions of cloud computing to the edge of an enterprise’s network or to the ability to manage transactions across the cloud/edge landscape, typically in a coordinated distributed or multi-node network. Some forms of fog computing provide the deployment of compute, storage, and networking services between end devices and cloud computing data centers, on behalf of the cloud computing locations. Some forms of fog computing also provide the ability to manage the workload/workflow level services, in terms of the overall transaction, by pushing certain workloads to the edge or to the cloud based on the ability to fulfill the overall service level agreement. Fog computing in many scenarios provide a decentralized architecture and serves as an extension to cloud computing by collaborating with one or more edge node devices, providing the subsequent amount of localized control, configuration and management, and much more for end devices. Thus, some forms of fog computing provide operations that are consistent with edge computing as discussed herein; the edge computing aspects discussed herein are also applicable to fog networks, fogging, and fog configurations. Further, aspects of the edge computing systems discussed herein may be configured as a fog, or aspects of a fog may be integrated into an edge computing architecture.
The core data center 1032 is located at a core network layer (a regional or geographically-central level), while the global network cloud 1042 is located at a cloud data center layer (a national or world-wide layer). The use of “core” is provided as a term for a centralized network location—deeper in the network—which is accessible by multiple edge nodes or components; however, a “core” does not necessarily designate the “center” or the deepest location of the network. Accordingly, the core data center 1032 may be located within, at, or near the edge computing system 1000. Although an illustrative number of client compute nodes 1002, edge gateway nodes 1012, edge aggregation nodes 1022, edge core data centers 1032, global network clouds 1042 are shown in
Consistent with the examples provided herein, a client compute node 1002 may be embodied as any type of endpoint component, device, appliance, or other thing capable of communicating as a producer or consumer of data. Further, the label “node” or “device” as used in the edge computing system 1000 does not necessarily mean that such node or device operates in a client or agent/minion/follower role; rather, one or more of the nodes or devices in the edge computing system 1000 refer to individual entities, nodes, or subsystems which include discrete or connected hardware or software configurations to facilitate or use the edge computing system 1000.
As such, the edge computing system 1000 is formed from network components and functional features operated by and within the edge gateway nodes 1012 and the edge aggregation nodes 1022. The edge computing system 1000 may be embodied as any type of deployment that provides edge computing and/or storage resources which are proximately located to radio access network (RAN) capable endpoint devices (e.g., mobile computing devices, IoT devices, smart devices, etc.), which are shown in
In some examples, the edge computing system 1000 may form a portion of or otherwise provide an ingress point into or across a fog networking configuration 1026 (e.g., a network of fog devices 1024, not shown in detail), which may be embodied as a system-level horizontal and distributed architecture that distributes resources and services to perform a specific function. For instance, a coordinated and distributed network of fog devices 1024 may perform computing, storage, control, or networking aspects in the context of an IoT system arrangement. Other networked, aggregated, and distributed functions may exist in the edge computing system 1000 between the core data center 1032 and the client endpoints (e.g., client compute nodes 1002). Some of these are discussed in the following sections in the context of network functions or service virtualization, including the use of virtual edges and virtual services which are orchestrated for multiple stakeholders.
As discussed in more detail below, the edge gateway nodes 1012 and the edge aggregation nodes 1022 cooperate to provide various edge services and security to the client compute nodes 1002. Furthermore, because a client compute node 1002 may be stationary or mobile, a respective edge gateway node 1012 may cooperate with other edge gateway devices to propagate presently provided edge services, relevant service data, and security as the corresponding client compute node 1002 moves about a region. To do so, the edge gateway nodes 1012 and/or edge aggregation nodes 1022 may support multiple tenancy and multiple stakeholder configurations, in which services from (or hosted for) multiple service providers, owners, and multiple consumers may be supported and coordinated across a single or multiple compute devices.
A variety of security approaches may be utilized within the architecture of the edge computing system 1000. In a multi-stakeholder environment, there can be multiple loadable security modules (LSMs) used to provision policies that enforce the stakeholder’s interests. Enforcement point environments could support multiple LSMs that apply the combination of loaded LSM policies (e.g., where the most constrained effective policy is applied, such as where if one or more of A, B or C stakeholders restricts access then access is restricted). Within the edge computing system 1000, each edge entity can provision LSMs that enforce the Edge entity interests. The Cloud entity can provision LSMs that enforce the cloud entity interests. Likewise, the various Fog and IoT network entities can provision LSMs that enforce the Fog entity’s interests.
Infrastructure Processing Units (IPUs) also referred to as Data Processing Units (DPUs) can be used by CSPs for performance, management, security and coordination functions in addition to infrastructure offload and communications. For example, IPUs can be integrated with smart NICs and storage or memory (for example, on a same die, system on chip (SoC), or connected dies) that are located at on-premises systems, base stations, gateways, neighborhood central offices, and so forth.
The IPU 1204 can perform an application composed of microservices. Microservices can include a decomposition of a monolithic application into small manageable defined services. Each microservice runs in its own process and communicates using protocols (for example, a Hypertext Transfer Protocol (HTTP) resource application programming interfaces (API), message service or Google remote procedure call (gRPC) calls/messages). Microservices can be independently deployed using centralized management of these services.
The IPU 1204 can execute platform management, networking stack processing operations, security (crypto) operations, storage software, identity and key management, telemetry, logging, monitoring and service mesh (e.g., control how different microservices communicate with one another). The IPU 1204 can access the xPU 1202 to offload performance of various tasks.
The network device pipeline stage 1300 receives output from other pipeline stages in the network device pipeline on input 1304 and input 1308 and sends the result of processing the input 1304 and input 1308 on output 1306 to one or more other network device pipeline stages 1300. An input stream received on input 1304 is stored in input First In First Out (FIFO) queue 1312 and an input stream received on input 1308 is stored in input FIFO queue 1310.
Descriptor fetch circuitry 1314 fetches descriptors from the input First In First Out (FIFO) queue 1312. The descriptors include metadata for network packets that are processed in the network device pipeline. Descriptor cache 1316 is a memory that can be used to store metadata while the packet is being processed in the network device pipeline stage 1300. The metadata is used to process the packet and can be updated as the packet is processed and evicted from descriptor cache 1316 after the packet has been processed by the network device pipeline stage 1300. Descriptor processing circuitry 1318 performs processing of the metadata and modification and processing of the packet.
Idleness detection circuitry 1324 monitors a number of entries stored in input FIFO queue 1312 and input FIFO queue 1310. The idleness detection circuitry 1324 can be enabled or disabled via a configuration register (not shown).
When the idleness detection circuitry 1324 detects that the input FIFO queue 1312 and the input FIFO queue 1310 are idle, idle detection 1326 is asserted. Upon detecting the assertion of idle detection 1326, the clock subsystem 1328 transitions from normal mode to idle mode (also referred to as dynamic clock throttled mode). Data packets can continue to be received on input 1304 and/or input 1308 and stored in the respective input FIFOs 1312, 1310 while the clock subsystem 1328 is in idle mode.
Upon detecting that one of the input FIFO queues 1312, 1310 is not empty, idle detection 1326 is de-asserted and the clock subsystem transitions from idle mode to normal mode. In idled mode, the clock frequency is decreased while idle detection 1326 is asserted.
Latency of the network device pipeline stage 1300 is the time for a data packet received by the network device pipeline stage 1300 at input 1304 or input 1308 to be processed by the network pipeline stage 1330 and exit the network pipeline stage at output 1306. The idleness detection circuitry 1324 to monitor data packets received by the network device pipeline stage 1300 at input 1304 and input 1310 that are stored in FIFO 1312 and FIFO 1310. The idleness detection circuitry 1324 can detect that the network device pipeline stage is idle when data packets are not being received at input 1304 or input 1308 for a time period. In an embodiment, the time period is greater than ten times the latency of the network device pipeline stage 1300.
Each pipeline stage 1422, 1424, 1426, 1428 in the network device pipeline can receive a pipeline stage clock signal (pipeline stage clock 1 1416, pipeline stage clock N 1440) from the clock subsystem 1328. A voltage-controlled oscillator (VCO) provides a VCO clock signal 1432 to clock dividers (clock divider 1 1436, clock divider N 1418). The frequency of each pipeline stage clock is selected by clock divider settings 1402. Clock divider settings 1402 include Pipeline Stage Clock control status registers for each of N pipeline stages in the network device pipeline. Pipeline stage clock 1 control status registers 1404 and pipeline stage clock N control status registers 1406 include normal mode 1408 and idle mode 1410 registers. The normal mode 1408 and idle mode 1410 registers can store a divider ratio for the respective clock divider. For example, the normal mode 1408 register in pipeline stage clock 1 control registers 1414 can store a divider ratio for clock divider 1 1436 for normal mode and the idle mode 1410 register in pipeline stage clock 1 control registers 1414 can store a divider ratio for clock divider 1 1436 for idle mode. Idle mode indicates a pipeline idle condition during which the clock can be dynamically throttled (reduced). In another embodiment, instead of storing the divider ratio, the normal mode 1408 and idle mode 1410 registers can store an index or pointer to a table of divider ratios.
Pipeline stage 1422 and pipeline stage 1424 share the pipeline stage clock 1 1416. Pipeline stage 1426 and pipeline stage 1428 share the pipeline stage clock N 1440. All pipeline stages that share the same pipeline stage clock must be idle to transition to the idle mode clock frequency. When one of the pipeline stages that share the same pipeline stage clock is no longer idle, the shared stage clock transitions to normal mode. For example, pipeline stage clock 1416 transitions to idle mode when both pipeline stage 1422 and pipeline stage 1424 are idle and pipeline stage clock 1416 transitions to normal mode if either pipeline stage 1422 or pipeline stage 1424 are not idle.
The clock subsystem 1328 receives idle detection(s) 1450 from pipeline stages in the network device pipeline. Idle detection(s) 1450 are coupled to the control inputs of multiplexers 1430, 1434 to control the output of the multiplexers 1430, 1434. The outputs of multiplexers 1430, 1434 are input to clock dividers (clock divider 1 1436, clock divider N 1418) to select the clock frequency of the pipeline stage clocks (pipeline stage clock 1 1416, pipeline stage clock N 1440).
While an idle detection(s) 1450 is asserted, idle mode 1410 is selected via the multiplexer 1430 to transition the pipeline stage clock for the pipeline stages from normal mode to idle mode. While in idle mode, the pipeline stages that receive the lower frequency clock are in a low-power state. When the idle detection(s) 1450 is de-asserted, normal mode 1408 is selected via the multiplexer 1430 to transition the pipeline stage clock for the pipeline stages from idle mode to normal mode.
The network processor 1502 includes a receive pipeline having a plurality of pipeline stages for processing network packets received from the network by a receive (RX) arbiter and a receive (RX) network buffer. The network processor 1502 includes a transmit pipeline having a plurality of pipeline stages for processing network packets to be transmitted to the network by an egress transmit (TX) arbiter and a transmit (TX) network buffer. A host interface (Host interfaces and/or switching (HIF) receives data to be transmitted in a network packet by the network processor 1502.
The receive pipeline can include Ingress Arbiter and Receive (RX) network buffer, Inline Crypto Engine (ICE), Packet Router (PR), Transport layer, Non-Volatile Memory express (NVMe), and receive path schedulers in Remote Direct Memory Access (RDMA), and Local Area Network (LAN) pipeline stages.
The transmit pipeline can include transmit path schedulers in NVMe, RDMA, and LAN, Packet Processor (Flexible Packet Processor (PP), Traffic Shaper (TS), Packet Builder (PB), Inline Crypto Engine (ICE), and TX arbiter and transmit network buffer pipeline stages.
In the embodiment shown in
In the embodiment shown in
The idle power is reduced for the packet processing pipeline in the network device by detecting average long-term idleness as a function of the minimum latency of the packet processing pipeline, which is used to reduce the clock rate of the packet processing pipeline, thereby resulting in power savings for the network device.
Network traffic Quality of Service (QoS) is not impacted because there is no packet delay when entering or exiting idle mode. There is no packet delay because the input First In First Out (FIFO) queue 1312 and input FIFO queue 1310 have sufficient depth to store received data packets while the frequency of the stage clock 1320 is switched from idle mode to normal mode.
Flow diagrams as illustrated herein provide examples of sequences of various process actions. The flow diagrams can indicate operations to be executed by a software or firmware routine, as well as physical operations. In one embodiment, a flow diagram can illustrate the state of a finite state machine (FSM), which can be implemented in hardware and/or software. Although shown in a particular sequence or order, unless otherwise specified, the order of the actions can be modified. Thus, the illustrated embodiments should be understood only as an example, and the process can be performed in a different order, and some actions can be performed in parallel. Additionally, one or more actions can be omitted in various embodiments; thus, not all actions are required in every embodiment. Other process flows are possible.
To the extent various operations or functions are described herein, they can be described or defined as software code, instructions, configuration, and/or data. The content can be directly executable (“object” or “executable” form), source code, or difference code (“delta” or “patch” code). The software content of the embodiments described herein can be provided via an article of manufacture with the content stored thereon, or via a method of operating a communication interface to send data via the communication interface. A non-transitory machine-readable storage media can cause a machine to perform the functions or operations described, and includes any mechanism that stores information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces to any of a hardwired, wireless, optical, etc., medium to communicate to another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface can be configured by providing configuration parameters and/or sending signals to prepare the communication interface to provide a data signal describing the software content. The communication interface can be accessed via one or more commands or signals sent to the communication interface.
Various components described herein can be a means for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of these. The components can be implemented as software modules, hardware modules, special-purpose hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuitry, etc.
Besides what is described herein, various modifications can be made to the disclosed embodiments and implementations of the invention without departing from their scope.
Therefore, the illustrations and examples herein should be construed in an illustrative, and not a restrictive sense. The scope of the invention should be measured solely by reference to the claims that follow.
