Patent Application
20080049024
The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements.
The timing control signals and data lines between graphics controller 106 and display 110 are shown generally as line 112. These may in fact be several separate address, data and control lines but are shown generally as line112, which may be referred to as a bus. It should be recognized that such address and data pathways may be represented throughout the figures as a single line. Host processor 102 performs digital processing operations and communicates with graphics controller 106 and memory 108 over bus 104. In other embodiments, processor 102 communicates over several address, data, and control lines.
In addition to the components mentioned above and illustrated in
Host processor 102 performs digital processing operations and communicates with graphics controller 106. In one embodiment, processor comprises an integrated circuit capable of executing instructions retrieved from memory 108. These instructions provide device 100 with functionality when executed by processor 102. Processor 102 may also be a digital signal processor (DSP) or other processing device. Examples include the Motorola Dragonball series of processors and similar deices made by Intel, Hitachi, NEC, etc.
Memory 108 may be internal or external random-access memory or non-volatile memory. Memory 108 may be non-removable memory such as flash memory or other EEPROM, or magnetic media. Alternatively, memory 108 may take the form of a removable memory card such as ones widely available and sold under such trademarks as “SD Card,” “Compact Flash,” and “Memory Stick.” Memory 108 may also be any other type of machine-readable removable or non-removable media. Memory 108 may be remote from device 100. For example, memory 108 may be connected to device 100 via a communications port (not shown), where a BLUETOOTH® interface or an IEEE 802.11 interface, commonly referred to as “Wi-Fi,” is included. Such an interface may connect device 100 with a remote host (not shown) for transmitting data to and from the remote host. If device 100 is a communications device such as a cell phone, it may include a wireless communications link to a carrier, which may then store data in hard drives as a service to customers, or transmit data to another cell phone or email address. Memory 108 may be a combination of memories. For example, it may include both a removable memory card for storing image data, and a non-removable memory for storing data and software executed by processor 102.
Display 110 can be any form of display capable of displaying a digital image. In one embodiment, display 110 comprises a liquid crystal display (LCD). However, other types of displays are available or may become available that are capable of displaying an image that may be used in conjunction with device 100.
Host processor 102 is in communication with host interface 310, which receives data, address, and control information over bus 104. The host interface 310 will include, among other things, an embedded CPU 312, along with address translation unit 313, and performs such functions as address translation for reading from and writing to graphics controller memory 314 and data transfer between memory 314 and host processor 102. The address translation unit 313 will translate software addresses received from the host processor (CPU) 102 into physical addresses that identify locations in the graphics controller memory 314.
The display buffer 316 will occupy a portion of the physical memory, i.e. graphics controller memory 314, which may be, for example, a 256K byte SRAM. For example, the display buffer 316 may occupy 128K of the physical memory, with the balance being used as data buffers 318, instruction buffers 320, and/or registers 322. It should be noted that for the sake of discussion, registers 322 are shown as a register block in memory 314, but may in fact be distinct hardware registers that are accessible separately from memory 314.
Display data read from the graphics controller memory 314 is transmitted to the display 110 for display on display panel 130 through display interface 360 via bus or signal lines 361. Additional control and timing signals (e.g. Vsync) are exchanged between display panel 130 and display interface 360 via bus or signal lines 361.
The display buffer may form part of the physical memory embedded in the graphics controller chip as shown in
Each area of the display buffer 316 will have starting addresses that are stored in registers 322. Typically the host processor writes image data into the main image memory 324 of the display buffer and also writes border data into the border image memory 326 of the display buffer. For the sake of discussion it will be assumed that the contents of the display buffer 316 comprising the border image memory 326 and the main image memory 324 map directly into the pixel locations in the display panel. However, it will be appreciated that the display buffer must be organized to meet the particular configuration of the display panel so that the pixel locations in the display buffer correspond to the pixel locations in the panel and the correct data is displayed in the proper location. To this end, the software address of display data received from the host processor 102 must be translated into an appropriate physical address in the display buffer 316. This task is performed by and an address translation unit 313 of the host interface 310 and/or the embedded CPU 312.
Generally speaking, the display buffer is organized as a Cartesian matrix of pixels, with a correspondence between a pixel's position in the display buffer and it's position on the display. This correspondence can be programmed for each particular type of display with address and control registers 322 that identify, for example, the start position of the border and increment values which advance to each subsequent position, and the start position of the main image and increment values which advance to each subsequent position. Each horizontal row of pixels is referred to as a raster line and the data is read from the display data in a raster sequence, one horizontal row after another.
The display is formed by pixels, typically color pixels defined in terms of a color space (a mathematical model for describing a gamut of colors). Pixels may be defined in more than one color space. Color displays generally require that pixels be defined in RGB color space, in which a pixel is described by red, green and blue components. The number of bits per pixel may be a function of the display panel, memory size, and size of the data pathways. For example, 16 bits-per-pixel (16 bpp) may be utilized with 5 bits for red, 6 bits for green, and 5 bits for blue (i.e. RGB 5:6:5). Alternately, 24 bpp may be utilized, i.e. (RGB 8:8:8). Input devices, such as a digital camera, may define pixels in a YUV color space, in which a pixel is described by a brightness component (Y), and two color components (U, V). The YUV model permits the use of a lower resolution for the color information in an image. The human eye is more sensitive to brightness than to color so the use of lower color resolution can conserve processing resources with little visual impact. A lower color resolution may be obtained by means of chroma subsampling, in which a sampling format defines how groups of consecutive YUV pixels are sampled. Particular sampling formats include 4:4:4, 4:2:2, 4:2:0, and 4:1:1. Storing an image with lower color resolution, e.g., in the 4:2:2, 4:2:0, and 4:1:1 sampling formats requires less memory than storing the same image in RGB or YUV 4:4:4 format. For the sake of discussion, it will be assumed that all pixel data is in RGB format. However, it will be understood that data input to the graphics controller may be in YUV format, and that data may be stored in the display buffer 316 in a lower resolution YUV format, and that such data must be converted, for example, by mapping through color conversion look-up-tables (LUTs) prior to being sent to the display 110.
An array of pixels may be referred to as a frame and the display generally displays one frame at a time, although multiple images, e.g. a main image and a border image, may be displayed in the same frame. The data to be displayed is read from the display buffer 316 through display interface 360 and driven by display driver circuitry in display 110 at a given rate, typically set at 60 frames per second, which is chosen based on human visual characteristics and the inability to discern rapid changes in the displayed information. Even if the data in the display buffer 316 is not changed, the frame of pixels in the display 110 must be updated, or “refreshed”, every 1/60th of a second. For example, if the same image is to be displayed for several contiguous frames, then new display data may be written into the display buffer 316 at a rate of only 20-30 frames per second, but it will still be read out of the display buffer 316 at a rate of 60 frames per second in order to refresh the display 110. The display 110, e.g. having an LCD display panel 130, will have a timing control circuit associated with it and that circuit will generate a vertical synchronization signal, Vsync, every 1/60th of a second. The display data for one frame is read from the display buffer 316 in synchronization with the display Vsync, which controls a liquid crystal driver circuit to drive the liquid crystal display panel.
Each time the host processor 102 needs to update the display data, it must write new display data into the main image area of the display. Additionally, if it is desired to change the appearance of the border, new border data must be written into the border area of the display. Assuming that a map of a rectangular portion of the display buffer 316 corresponds to a map of pixel locations in the display panel 130, the host processor 102 writes color display data (e.g. 24 bits-per-pixel, RGB 8:8:8) that defines the appearance of the border into that area of the display buffer 316 allocated to the border.
The present invention overcomes this disadvantage by providing a border changing function within the graphics controller. As shown in
In a preferred embodiment, the host processor 102 is programmed by a user to input values into each of registers 510, 512, 514, 516, 518, and 520 via bus 104 and host interface 310. Additionally the host processor 102 activates the border changing circuit 330 with an activation control signal (e.g. ACTIVATE) that is sent via the host interface 310 (
In response to the activation control signal from the host processor 102, the border changing circuit 330 begins operation.
Referring to
As an example, the start border color is red. Assuming 24 bits-per-pixel, 8 bits per RGB color component, the start border color that is written into every border memory location is 11111111, 00000000, 00000000.
The border changing circuit 330 monitors a timing signal TIMING SIG (
The border color change operation continues with step 708 in which the border start address is loaded into the border current address register 522. In step 710, the current color data is then read from the location in border image memory 326 identified by the address in the border current address register 522. The current color data is then incremented by m (the incremental amount of change parameter) in step 712. For example, assume the start border color is red (RGB=11111111, 00000000, 000000000) and the end border color is yellow (a mixture of red and green) (RGB=11111111, 11111111, 00000000). If m=1, for example, after the first increase the border color would be RGB=11111111, 00000001, 000000000, and after the second increase the border color would be RGB=11111111, 00000010, 000000000, and so on. To increase the amount of each change, say m=2, for example, after the first increase the border color would be RGB=11111111, 00000010, 000000000, and after the second increase the border color would be RGB=1111111, 00000100, 000000000, and so on. In this example, the incremental amount of change value is added to the green component of the current RGB value in step 712. Of course, it will be appreciated that if the start border color is yellow and the end border color is red (the reverse of the above example), then the incremental amount of change value is subtracted from the green component of the current RGB value in step 712.
In step 714 the changed color data value is written into the address location specified by the border current address register 522. In step 716, the current border address is compared to the border end address. If they are not equal, then the current address is incremented in step 718 and the process moves to step 710 where the current color is read from the next sequential border location. That color is changed, the changed color is written back into the new location and the process continues until all border locations have been updated with the changed color.
Once the current border address equals the border end address at step 716 (i.e. all border locations have be updated with the changed color), the process continues to step 718 to check if the changed color data equals the end border color. If not, the process goes to step 700, which begins the process of changing the border color by the next incremental amount. Once the changed color data equals the end border color (Yes in step 718), the process goes to step 604 in
In another embodiment, the border color changing circuit 330 can be activated only upon reception of an event signal (EVENT). For example, a battery monitoring circuit 350 can be provided to monitor the state or condition of a battery 353 and generate an event signal such as BATTlow whenever the voltage of battery 352 falls below a certain threshold level. In response to reception of this signal, the border color changing circuit 330 will begin changing the color as described above with reference to
Various other embodiments will become evident to those having ordinary skill in the art. For example, rather that changing the color of the entire border uniformly, distinct groups of pixels in the border can be changed by different amounts. As one example,
As another embodiment, rather than changing the color of the border over time, the shape of the border can be changed over time. Commonly assigned U.S. Patent Application Publication No. 2005/0185852 describes a method and apparatus for generating complex borders in a graphics controller without host processor intervention, which published patent application is incorporated herein by reference in its entirety. Utilizing the principles of the present invention described above, a different shape can be applied to the border over time. For example,
The invention can also be embodied as computer readable code stored on a computer readable medium. The computer readable medium is any data storage device that can store data which can be thereafter read and executed by a computer. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network coupled computer system so that the computer readable code is stored and executed in a distributed fashion.
The above described invention may be practiced with other computer system configurations including hand-held devices, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
