This invention relates generally to the field of electronic circuits and, more particularly, to methods and systems for improving reference voltage accuracy in capacitor arrays that may be used in various electronic circuits.
Technological advances in digital transmission networks, digital storage media, Very Large Scale Integration devices, and digital signal processing have resulted in an increased demand in the conversion of signals from an analog domain to a digital domain and vice-versa.
Over the years, various analog-to-digital converters (ADC) and conversion techniques have been developed for converting electrical signals from an analog domain to a digital domain. Typically, the process of analog-to-digital conversion includes sampling an analog signal and comparing the sampled analog signal to a threshold value. A digital word can be recorded depending upon the result of the comparison.
Currently, Complementary Metallic Oxide Semiconductor (CMOS) integrated circuit technology is becoming more commonplace. CMOS technology is relatively inexpensive and yet versatile in allowing designers to include digital logic circuitry and analog circuitry in the same integrated circuit, which is applicable to ADC's.
As the requirements for precision have continued to increase with respect to ADC's, the use of resistor networks for sampling has been substantially reduced due to the difficulty in producing accurate resistors using CMOS technology. Instead, techniques which utilizes capacitor networks instead of resistor networks have become the most commonly used methodology in CMOS ADC technology.
Capacitor arrays or ladders are commonly employed in analog-to-digital converters, digital-to-analog converters, switched-capacitor filters, or other such circuits. However, in capacitor related circuits, factors such as current surges, parasitic conductor effect, capacitance mismatch, or other such effects can affect the accuracy of reference source voltages that can be included which can in turn degrade performance.
Therefore, there is a need for more efficient methods that can improve the reference voltage accuracy in capacitor related circuits.
Consistent with some embodiments of the present invention, a method for converting an analog input voltage signal to a discrete signal includes generating at least one reference voltage and at least one secondary voltage. The method further includes selecting at least one voltage between the at least one reference voltage and the at least one secondary voltage and generating at least one intermediate voltage based on the at least one voltage and at least one digital code. The at least one intermediate voltage and the analog input voltage further being used to generate at least one comparison signal and the discrete signal being generated based on the at least one comparison signal and the at least one digital code.
In another embodiment, an analog to digital converter (ADC) for converting an analog input voltage to a discrete signal includes a reference generator unit (RGU) for generating at least one reference voltage, a secondary voltage source (SVS) for generating at least one secondary voltage and a multiplexer coupled to receive the at least one secondary voltage and the at least one reference voltage. The multiplexer further configured to select between the at least one reference voltage and the at least one secondary voltage based on a control signal. The ADC further includes a digital to analog converter (DAC) coupled to receive the analog input voltage, at least one voltage from the multiplexer, and at least one digital code. The DAC further generates at least one intermediate voltage based on the at least one digital code. The ADC also includes a comparator coupled to receive the analog input voltage and the at least one intermediate voltage, the comparator further configured to generate at least one comparison signal, and a control logic unit (CLU) coupled to receive a clock signal and the comparison signal, the CLU configured to generate the control signal and the at least one digital code, the CLU further generating the discrete signal.
Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
a and 5b are graphs illustrating performance of an ADC consistent with some embodiments of the present invention.
In the figures, elements having the same designation have the same or similar functions.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like parts.
In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” and/or “coupled” may be used to indicate that two or more elements are in direct physical or electronic contact with each other. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still cooperate, communicate, and/or interact with each other.
It should be understood that various functional units discussed in the following description and claims can, in practice, individually or in any combinations, be implemented in hardware, in software executed on one or more hardware components (such as one or more processors, one or more application specific integrated circuits (ASIC's) or other such components), or in any combination thereof.
As shown in
System 100 can further include an analog to digital converter (ADC) 106 that can be coupled to receive processed signal 105 (from APU 104) and can be configured to convert processed input signal 105 into a discrete signal 107 that can include one or more binary bits. The operation of an ADC such as exemplary ADC 106 will be discussed below with respect to
As shown in
In some embodiments, comparator 204 can be coupled to a sample and hold unit (SHU) 201. SHU 201 can be coupled to receive input signal 105 and can be configured to sample signal 105 to generate a plurality of voltage samples (Vin) associated with signal 105. In some embodiments, comparator 204 can compare inputs via terminals 210 and 212 on a sample by sample basis.
As shown in
As shown in
In some embodiments, DAC 202 can generate intermediate voltage signal VINT by normalizing input voltage Vin to be in a range within reference voltages VRP and VRN. As will be discussed later with respect to
As discussed above, the voltage level that can be generated by the capacitor array in DAC 202 (corresponding to intermediate digital code 216) can be generated by using reference voltages (VRN and VRP) generated by RGU 208. For example, assuming that the intermediate digital code 216 corresponds to a voltage level that has a value of Q volts, and reference voltage generated by RGU 208 equals Vref (where Vref=VRP−VRN) then the actual voltage corresponding to a digital code (such as digital code 216) equals (Vref*Q)/2N.
As discussed above, in order to improve accuracy and performance of ADC 106, reference voltage Vref may be held at a constant predetermined level during all iterations, which may result in a more accurate generation of a digital code (such as digital code 216).
As is shown in
As discussed above, CLU 206 can toggle switches 310, 312, 314, and 316 of capacitor array 301 (via intermediate digital code 216) to generate an appropriate intermediate voltage VINT across terminal 212. Initially, capacitors 302, 304, 306, and 308 can be charged by coupling each capacitor to a reference voltage such as reference voltages VRN and VRP via their respective switch. In some embodiments, one or more capacitors in capacitor array 301 can be charged by coupling with input voltage Vin (via their respective switch). A voltage corresponding to a total charge due to one or more capacitors in capacitor array 301 can be provided to terminal 212 by closing switch 320. CLU 206 can therefore select one or more (charged) capacitors from capacitor array 301 to attain a given voltage across terminal 212 of comparator 204. Therefore, for each iteration of an input voltage sample, capacitors (302, 304, 306, and 308) of capacitor array 301 can be charged (and/or discharged) to one or more voltage levels, and CLU 206 (via digital code 216) can select one or more different combinations of capacitors from capacitor array 301.
As discussed earlier, in order to improve accuracy and performance of ADC 106, reference voltages such as exemplary reference voltages VRP and VRN may be at a constant predetermined voltage. However, due to the repeated charging and/or discharging of capacitors in capacitor array 301, various conditions such as capacitor parasitics, current surges, etc. can exist that can affect the accuracy of reference voltages VRN and VRP generated by RGU 208.
To avoid the unsettling of reference voltages VRN and VRP due to the charging and/or discharging of one or more capacitors in capacitor array 301, in some embodiments CLU 206 can initially couple DAC 202 with SVS 424 by activating MUX 420 via control signal 422. After a given time duration or voltage level, CLU 206 can deactivate MUX 420 via control signal 422, to couple DAC 202 with reference voltages VRN and VRP from RGU 208. Because a final voltage output across capacitor array 301 (not shown in
a and 5b are graphs illustrating the output of ADC 106 discussed in
It should be understood that embodiments disclosed herein can be used in an capacitor related circuit and are not limited in use to ADC's or DAC's.
Other embodiments will be apparent to those skilled in the art from consideration of the specification and practice disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.