Number | Name | Date | Kind |
---|---|---|---|
5195089 | Sindhu et al. | Mar 1993 | |
5404464 | Bennett | Apr 1995 | |
5465333 | Olnowich | Nov 1995 | |
5481681 | Gallo et al. | Jan 1996 | |
5517624 | Landry et al. | May 1996 | |
5555383 | Elazar et al. | Sep 1996 | |
5608878 | Arimilli et al. | Mar 1997 | |
5623694 | Arimilli et al. | Apr 1997 | |
5640518 | Muhich et al. | Jun 1997 |
Entry |
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IBM Technical Disclosure Bulletin, vol. 37, No. 05, May. 1994, Separating the Interaction of Address and Data State during Bus Data Transfers. |
IBM Technical Disclosure Bulletin, vol. 37, No. 06A, Jun. 1994, Address Pipelining with a Flexible Control Mechanism for Shared Bus Protocols. |
IBM Technical Disclosure Bulletin, vol. 39, No. 11, Nov. 1996, Improving L1/L2 Cast-Out Performance in an Inclusive Serial Cache. |