METHOD AND APPARATUS TO REDUCE THE EFFECT OF CROSSTALK IN A COMMUNICATIONS INTERFACE

Abstract

A technique for reducing crosstalk between communications paths includes scrambling data using scrambling functions that reduce or substantially minimizing a probability that worst-case data patterns occur on communications paths adjacent to a potential victim communications path. In at least one embodiment of the invention, a method includes scrambling a plurality of data bits based at least in part on respective ones of a plurality of distinct combinations of one or more taps of a linear feedback shift register (LFSR). The plurality of data bits are scrambled for transmission during a first bit-time on corresponding ones of a plurality of adjacent communications paths.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

FIG. 1 illustrates a block diagram of two integrated circuit devices coupled by a communications link consistent with one or more embodiments of the present invention.

FIG. 2 illustrates a block diagram of portions of an exemplary communications link consistent with one or more embodiments of the present invention.

FIG. 3 illustrates a block diagram of portions of an exemplary communications link consistent with one or more embodiments of the present invention.

FIG. 4 illustrates a block diagram of an exemplary linear feedback shift register (LFSR) consistent with one or more embodiments of the present invention.

FIG. 5 illustrates exemplary taps of the LFSR of FIG. 4 used to generate scramble patterns for a plurality of bit-times of data for transmission on respective ones of a plurality of communications paths and consistent with one or more embodiments of the present invention.

FIG. 6 illustrates a block diagram of portions of an exemplary communications link consistent with one or more embodiments of the present invention.

Claims

1. A method comprising: scrambling a plurality of data bits based at least in part on respective ones of a plurality of distinct combinations of one or more taps of a linear feedback shift register (LFSR), the plurality of data bits being scrambled for transmission during a first bit-time on corresponding ones of a plurality of adjacent communications paths.

2. The method, as recited in claim 1, wherein the LFSR includes 23 taps and represents a polynomial function of x23+x18+1.

3. The method, as recited in claim 1, wherein individual ones of the plurality of distinct combinations of one or more taps include an exclusive-or of two individual taps of the LFSR.

4. The method, as recited in claim 1, wherein the LFSR includes 23 taps, the plurality of transmission lines includes nine transmission lines, and the plurality of distinct combinations of one or more taps include logical functions of taps 13 and 18, taps 10 and 17, taps 12 and 16, taps 8 and 16, taps 9 and 15, taps 9 and 18, taps 11 and 13, taps 11 and 14, and taps 13 and 14.

5. The method, as recited in claim 1, wherein scrambling the plurality of data bits includes performing exclusive-ors of respective ones of the plurality of data bits with corresponding ones of the plurality of distinct combinations.

6. The method, as recited in claim 1, wherein the plurality of distinct combinations of one or more taps substantially minimize a probability that worst case data patterns occur on the plurality of adjacent communications paths with respect to individual ones of the plurality of adjacent communications paths being victims of crosstalk from others of the plurality of adjacent communications path.

7. The method, as recited in claim 1, further comprising: scrambling, concurrently with the scrambling of the plurality of data bits, at least one additional plurality of data bits associated with at least one additional bit-time subsequent to the first bit time,wherein the scrambling the additional plurality of bits is based at least in part on individual ones of the plurality of distinct combinations of one or more taps of the LFSR corresponding to the additional bit time, the additional plurality of data bits being scrambled for transmission during the additional bit-time on corresponding ones of the plurality of adjacent communications paths.

8. The method, as recited in claim 1, further comprising: descrambling a plurality of signals based at least in part on respective ones of the plurality of distinct combinations of one or more taps, the plurality of distinct combinations of one or more taps being generated by another instantiation of the LFSR, the plurality of signals being associated with corresponding ones of the plurality of adjacent communications paths and being descrambled during the first bit-time, thereby recovering the plurality of data bits.

9. The method, as recited in claim 8, further comprising: synchronizing the LFSR to the other instantiation of the LFSR, wherein the scrambling is performed on a first integrated circuit and the descrambling is performed on a second integrated circuit, the first integrated circuit being coupled to the second integrated circuit by the plurality of adjacent communications paths.

10. An apparatus comprising: a plurality of adjacent communications paths; anda scrambling circuit associated with the plurality of adjacent communications paths, the scrambling circuit comprising: a linear feedback shift register (LFSR); anda plurality of logic circuits responsive to respective ones of a plurality of distinct combinations of one or more taps of the LFSR and responsive to corresponding ones of a plurality of data bits for transmission during a first bit-time on corresponding ones of a plurality of adjacent communications paths to generate a plurality of scrambled data signals.

11. The apparatus, as recited in claim 10, further comprising: a descrambling circuit associated with the plurality of adjacent communications paths,wherein the descrambling circuit comprises: an additional instantiation of the LFSR; anda plurality of logic circuits responsive to respective ones of a plurality of signals and responsive to respective ones of the plurality of distinct combinations of one or more taps, the plurality of distinct combinations of one or more taps being generated by the additional instantiation of the LFSR, the plurality of signals being associated with corresponding ones of the plurality of adjacent communications paths and being descrambled during the first bit-time, thereby recovering the plurality of data bits.

12. The apparatus, as recited in claim 10, wherein the LFSR includes 23 taps and represents a polynomial function of x23+x18+1.

13. The apparatus, as recited in claim 10, wherein individual ones of the plurality of corresponding distinct combinations of one or more taps include an exclusive-or of two distinct taps of the LFSR.

14. The apparatus, as recited in claim 10, wherein the LFSR includes 23 taps, the plurality of transmission lines includes nine transmission lines, and the plurality of distinct combinations of one or more taps include logical functions of taps 13 and 18, taps 10 and 17, taps 12 and 16, taps 8 and 16, taps 9 and 15, taps 9 and 18, taps 11 and 13, taps 11 and 14, and taps 13 and 14.

15. The apparatus, as recited in claim 10, wherein the plurality of distinct combinations of taps substantially minimize a probability that worst case data patterns occur on the plurality of adjacent communications paths with respect to individual ones of the plurality of adjacent communications paths being victims of crosstalk from others of the plurality of adjacent communications path.

16. The apparatus, as recited in claim 10, wherein the scrambler circuit scrambles, concurrently with the scrambling of the plurality of data bits, at least one additional plurality of data bits associated with at least one additional bit-time subsequent to the first bit-time, based at least in part on individual ones of the plurality of distinct combinations of one or more taps of the LFSR corresponding to the additional bit-time, the additional plurality of data bits being scrambled for transmission during the additional bit-time on corresponding ones of the plurality of adjacent communications paths.

17. An apparatus comprising: means for coupling a first integrated circuit to a plurality of adjacent communications paths;means for scrambling a plurality of data bits for transmission on corresponding ones of the plurality of adjacent communications paths substantially minimizing a probability that worst case data patterns occur on the plurality of adjacent communications paths with respect to individual ones of the plurality of adjacent communications paths being victims of crosstalk from others of the plurality of adjacent communications paths.

18. The apparatus, as recited in claim 17, wherein the means for scrambling scrambles a plurality of data bits based at least in part on respective ones of a plurality of distinct combinations of one or more taps of a linear feedback shift register (LFSR), the plurality of data bits being scrambled for transmission during a first bit-time on corresponding ones of a plurality of adjacent communications paths.

19. The apparatus, as recited in claim 17, wherein the means for scrambling scrambles a plurality of data bits based at least in part on respective outputs of a plurality of instantiations of a linear feedback shift register (LFSR) polynomial function, individual instantiations of the LFSR being initialized with respective ones of a plurality of distinct seed values.

20. The apparatus, as recited in claim 17, further comprising: means for recovering the plurality of data bits from a signal generated by the means for scrambling.