Claims
- 1. A method of protecting data saved in a memory, in which method at least one memory element and at least one data processing element are combined by means of required interfaces into a data processing entity, the method comprising:
scrambling the form in which the data to be saved in the memory element is represented by means of at least one scrambler connected to the data processing entity; descrambling data saved in the memory element by means of at least one scrambler connected to the data processing entity into plain text when data is taken from the memory element for the use of data processing elements.
- 2. A method according to claim 1, wherein the scrambler is on the same semiconductor chip as the memory element connected thereto.
- 3. A method according to claim 1, wherein the scrambler is in the same package as the memory element connected thereto.
- 4. A method according to claim 1, wherein the scrambler and the memory element connected thereto are on different printed boards.
- 5. A method according to claim 1, wherein at least one data processing element is an ASIC.
- 6. A method according to claim 1, wherein at least one data processing element is a processor.
- 7. A method according to claim 1, wherein the scrambler is implemented by means of an interleaver and a de-interleaver.
- 8. A method according to claim 1, wherein the scrambler is implemented by means of an encoder and a decoder.
- 9. A method according to claim 1, wherein the scrambler is implemented by means of an encryption algorithm.
- 10. A method according to claim 1, the scrambler further comprising a bus adapter element.
- 11. A method according to claim 1, wherein the scrambler processes user data.
- 12. A method according to claim 1, wherein the scrambler processes commands.
- 13. A method according to claim 1, the scrambler further comprising a configuration register.
- 14. A method according to claim 1, wherein all data to be saved in the memory element is protected by means of the scrambler.
- 15. A method according to claim 1, wherein a predetermined part of the data to be saved in the memory element is protected by means of the scrambler.
- 16. A method according to claim 1, wherein data to be saved in different areas of the memory element is protected in different ways by means of the scrambler.
- 17. A method according to claim 1, wherein the scrambler is adapted to buses in such a way that it is a transparent element from the point of view of the data processing entity.
- 18. An arrangement for protecting data saved in a memory, in which arrangement at least one memory element and at least one data processing element are combined by means of required interfaces into a data processing entity, the arrangement comprising:
at least one scrambler connected to the data processing entity, which scrambler scrambles the form in which the data to be saved in the memory element is represented or which scrambler descrambles data saved in the memory element into plain text when data is taken from the memory element for the use of the data processing elements.
- 19. An arrangement for protecting data saved in a memory, in which arrangement at least one memory element and at least one data processing element are combined by means of required interfaces into a data processing entity, the arrangement comprising:
at least one scrambler connected to the data processing entity, which scrambler scrambles the form in which the data to be saved in the memory element is represented and which scrambler descrambles data saved in the memory element into plain text when data is taken from the memory element for the use of the data processing elements.
- 20. An arrangement according to claim 19, wherein at least one data processing element is an ASIC.
- 21. An arrangement according to claim 19, wherein at least one data processing element is a processor.
- 22. An arrangement according to claim 19, wherein the scrambler is implemented by means of an interleaver and a de-interleaver.
- 23. An arrangement according to claim 19, wherein the scrambler is implemented by means of an encoder and a decoder.
- 24. An arrangement according to claim 19, wherein the scrambler is implemented by means of an encryption algorithm.
- 25. An arrangement according to claim 19, wherein the scrambler comprises a bus adapter element.
- 26. An arrangement according to claim 19, wherein the scrambler processes user data.
- 27. An arrangement according to claim 19, wherein the scrambler processes commands.
- 28. An arrangement according to claim 19, wherein the scrambler comprises a configuration register.
- 29. An arrangement according to claim 19, wherein all data to be saved in the memory element is protected by means of the scrambler.
- 30. An arrangement according to claim 19, wherein a predetermined part of the data to be saved in the memory element is protected by means of the scrambler.
- 31. An arrangement according to claim 19, wherein data to be saved in different areas of the memory element is protected in different ways by means of the scrambler.
- 32. An arrangement according to claim 19, wherein the scrambler is adapted to buses in such a way that it is a transparent element from the point of view of the data processing entity.
- 33. An arrangement according to claim 19, wherein the scrambler is adapted to a bus with a compressor/decompressor.
- 34. An arrangement for protecting data saved in a memory, in which arrangement at least one memory element and at least one data processing element are combined by means of required interfaces into a data processing entity, the arrangement is configured to:
scramble connected to the data processing entity, which scrambler scrambles the form in which the data to be saved in the memory element is represented descramble data saved in the memory element into plain text when data is taken from the memory element for the use of the data processing elements.
Parent Case Info
[0001] This application is a continuation of international application PCT/FI01/00146 filed 15 Feb. 2001 which designated the US and was published under PCT article 21(2) in English.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/FI01/00146 |
Feb 2001 |
US |
Child |
10641287 |
Aug 2003 |
US |