Patent Application
20050202798
This nonprovisional application claims priority under 35 U.S.C. § 119(a) on German Patent Application No. DE 102004010890.0 filed in Germany on Mar. 6, 2004, which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to a method and a circuit arrangement for switching an electronic circuit into a power-saving mode by a switchover signal.
2. Description of the Background Art
Switchover into a power-saving mode is necessary in particular for circuits powered by a battery voltage, for example in automotive or mobile radio applications, in order to minimize power consumption during the circuit's inactive phases. “Inactive phases” are, for example, those periods of time during which the circuit, which in particular can be an integrated circuit, e.g. an infrared receiver, transmits no data to other electronic assemblies, e.g. a microcontroller.
In prior art methods and circuit arrangements of the aforementioned type, a connecting pin of a circuit is dedicated exclusively to serve as an input pin for the switchover signal, or else an additional pin is provided for the switchover signal. It can be seen as a disadvantage here that either a pin of the circuit is unavailable for other applications, or the provision of an additional pin entails additional manufacturing expense, and is to be avoided in particular in the course of advancing miniaturization of electronic structures, not least on account of the additional space required.
It is therefore an object of the present invention to provide a method and circuit arrangement such that the above-mentioned disadvantages are avoided.
The object is attained in a method of the aforementioned type in that a data output pin of the circuit is also used as an input pin for an external signal on the basis of which the switchover signal is then produced. In order to achieve the object in a circuit arrangement of the aforementioned type, provision is made that a data output pin of the circuit can also be used as an input pin for an external signal, with the external signal being the basis for producing the switchover signal. In this way the invention allows the function of a power-saving mode without “tying up” a connecting pin of the circuit or requiring the provision of an additional pin.
In a further development of the method according to an embodiment of the invention, provision is made that a potential value at the data output pin is compared with a reference value, by which a first internal control signal is generated. The first internal control signal is then logically combined with a second internal control signal, and the result of the combination is then used as the switchover signal. Here, the second internal control signal preferably represents an activity of data transmission to the data output pin, so that according to the invention switchover to the power-saving mode can only occur if the second internal control signal indicates a state of absence of data activity. In this way the data output pin effectively functions as a switchover control input only when the circuit to be controlled is not active at the time.
In a circuit arrangement according to the invention, corresponding provision can be made to connect a comparator to the data output pin to compare the external signal to a reference signal and generate a first internal control signal as a function of the comparison result, with the circuit arrangement preferably having an additional signal generating means to indicate an activity of the data transmission to the data output pin by a second internal control signal. In order, as already mentioned above, to permit the use of the data output pin for the purpose of a mode switch only during inactivity of the circuit, the inventive circuit arrangement advantageously has a logical combiner for the first and second internal control signals which is further characterized in that the switchover signal can be generated by the combiner.
To further reduce power consumption in the power-saving mode, in a further embodiment of the present invention, it is provided that, once switchover to the power-saving mode takes place, a pull-up resistor connected between the data output pin and a connection for a supply voltage is replaced by a low current source. Thus, a circuit arrangement can have a switch to replace a pull-up resistor that is arranged between the data output pin and a supply voltage connection with a low current source. In the operating mode of the circuit, the pull-up resistor provides for a defined potential at the data output pin, but would otherwise result in too much current as a result of the applied supply voltage. According to an embodiment of the invention, the switch, which is provided by circuitry to replace the resistor, can also be controlled by the switchover signal.
According to an alternate embodiment of the circuit arrangement, the low current source and the pull-up resistor are connected in parallel and the switch are transistors that are connected directly ahead of the low current source and/or directly ahead of the pull-up resistor. The transistors, like the circuit, can be controlled by the switchover signal.
For the purpose of the simplest possible design of the circuit arrangement according to the invention, the low current source can be embodied as a resistor with a high value in comparison to the pull-up resistor.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein the single FIGURE shows a circuit arrangement according to an embodiment of the present invention.
The single FIGURE shows a circuit arrangement according to an embodiment of the present invention for switchover of an integrated circuit (IC) 1 at the direction of an external microcontroller (μC) 2. In the example embodiment shown, the integrated circuit 1 is a circuit designed to receive signals in an infrared (IR) portion of the spectrum, i.e. an IR receiver. During normal operation the integrated circuit 1 draws a current IS from a supply voltage VS, for example a battery voltage, and in a power-saving mode (shutdown mode, SD) draws a current ISD that is reduced in comparison to the current IS.
A circuit arrangement 3 in accordance with the invention is wired in operative connection to the integrated circuit 1. In this regard, the circuit arrangement 3 and the integrated circuit 1 can also be integrated together (monolithic), as indicated in the FIGURE by a dashed line 4 (integrated unit).
In accordance with the example embodiment shown, the circuit arrangement 3 includes a data output pin 1.1 of the IC 1, through which the latter transmits received data DAT to the microcontroller 2. Within the circuit arrangement 3, the data output pin 1.1 is connected to a node 3.1 that lies between a supply voltage VS, for example, a battery voltage in which VS=5V, and a ground potential GND. A first switch, which can be a NMOS transistor 3.2, hereinafter referred to as the output transistor, is connected between the node 3.1 and the ground potential GND. The output transistor 3.2 can have a self-cutoff characteristic, and can function as a pull-down transistor with regard to the node 3.1.
The gate electrode of the output transistor 3.2 is connected to a functional unit 3.3 of the circuit arrangement 3, which can be a demodulator, for example, by which the output transistor 3.2 can be controlled at its gate electrode by a signal D. The signal D can be a binary data signal from the IC 1 that is isolated in the functional unit 3.3 from a carrier wave, e.g., a series of HIGH and LOW level values. Whereby, the output transistor 3.2 is cut off in the case when D=0 and conducts when D=1. In the latter case, the node 3.1 is at the ground potential GND.
Connected between the node 3.1 and a connection for the supply voltage VS, starting from the node 3.1 there are a pull-up resistor R1 and, in series therewith, a second switch, which can be a self-conducting PMOS transistor 3.4. In parallel therewith, the circuit arrangement 3 has a third switch, which can be an additional self-conducting PMOS transistor 3.5, and a current source 3.6 that supplies a low “sense” current IL on, for example, the order of IL=100 nA. Alternatively, the current source 3.6 can also be designed as a resistor R2 with a value that is high relative to the pull-up resistor R1 (e.g., R1=100 kΩ, R2□R1), as is shown in the FIGURE with the aid of the dotted connections. Also starting from the supply voltage VS, there are arranged first the transistor 3.5 and then the current source 3.6/the resistor R2, where the connections of the pull-up resistor R1 and the current source 3.6/the resistor R2, which face the node 3.1, terminate in a common node 3.7.
Additionally, the circuit arrangement 3 has a comparison means in the form of a comparator 3.8 whose inputs for comparison are connected to the node 3.7 and to a reference voltage VR, with VR>GND. An output signal S1 of the comparator 3.8, which functions as a first internal control signal, is connected to one of the inputs of a logical combiner, which can be an AND gate 3.9. The second input of the AND gate 3.9 is connected to the functional unit 3.3 for receiving a second internal control signal S2, by which the functional unit 3.3 indicates an activity of data transmission (hereinafter referred to as data activity) from IC 1 to data output pin 1.1. In the embodiment of the invention shown, for example, S2=1 in the absence of data activity (no data burst to the output pin 1.1).
The output of the AND gate 3.9 is connected to an additional node 3.10, which branches off to a gate electrode of the PMOS transistor 3.4, to a gate electrode of the PMOS 3.5 via an inverter 3.11, and to the IC 1 (signal SD′). In this way, both of the PMOS transistors 3.4, 3.5 (complementary to one another) and also the IC 1 can be controlled by the output of the AND gate 3.9.
In normal operation, the transistor 3.4 conducts. As already mentioned, the output transistor 3.2 is controlled by the functional unit 3.3. Thus, via the pull-up resistor R1 an output signal DAT can be accessed at output pin 1.1 as a direct reproduction of the signal D for further processing by the microcontroller 2. The current Is typically flows at approximately 500 μA.
The circuit arrangement 3 now operates to switch IC 1 into the power-saving mode as follows: the data output pin 1.1 is externally brought to ground potential GND by the microcontroller 2. This process is symbolized in the FIGURE by the arrow SD from the microcontroller 2 to the output pin 1.1. As a result the nodes 3.1, 3.7 drop the voltage at one input of the comparator 3.8 below the reference value VR so that the comparator 3.8 generates the signal S1, here S1=1. This signal is combined with the signal S2 by the AND gate 3.9, with the AND gate then providing a HIGH level output signal to node 3.10 when S1=1 and S2=1 at the same time, which is to say when no data activity is taking place and the external SD signal has been given.
The output signal of the AND gate 3.9 serves firstly as an (internal) shutdown signal SD′ for IC 1. Consequently, the IC 1 can only be switched over into the power-saving mode on the basis of the external signal SD when no data is being transmitted at this moment.
Thus, the data output pin 1.1 of the integrated circuit 1 is used simultaneously as an input pin for the external shutdown signal SD, according to which—as already described in detail above—the internal switchover signal SD′ is subsequently generated.
Secondly, an additional power reduction is achieved on account of the controlling connections from the node 3.10 to the transistors 3.4, 3.5 in the power-saving mode according to the invention. In the event of a HIGH level signal at node 3.10, the PMOS transistor 3.4 cuts off, while the PMOS transistor 3.5 conducts on account of the inverter 3.11. In this way, the pull-up resistor R1 is replaced by the current source 3.6 or the resistor R2. This makes it possible to avoid having an excessively high current I=VS/R1=50 μA flow from the supply voltage VS through the pull-up resistor R1 in the power-saving mode of the IC 1. In contrast, the quiescent current consumption of IC 1 is only approximately ISD=100 nA. According to the invention, on account of IL=100 nA, a total quiescent current in power-saving mode of ISD+IL=200 nA results, which is to say one 250th of the quiescent current through the resistor R1. Alternatively, the same result is achieved using a resistor with a high value R2=50 MΩ in comparison to the pull-up resistor R1.
It is necessary to switch on the current IL or VS/R2 in order to set the output pin 1.1 at a defined potential even in power-saving mode, i.e. in the absence of data activity; without this current, the output pin would float.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| DE 102004010890.0 | Mar 2004 | DE | national |
