METHOD AND CIRCUIT FOR POWER FACTOR CORRECTION

Abstract

A method and circuit for correcting a power factor in an alternating current/direct current power transformer. The circuit has an inductance fed by a rectified AC voltage, and a switch by which the inductance can be charged and discharged by closing and opening the switch, and further has a diode by which the discharge current of the inductance is fed to the output of the circuit. During the discharge phase, a voltage Vmon corresponding to the output voltage VBUS is measured, and the measured values are stored. It is further determined when the discharge current reaches or crosses the zero line at the end of a discharge phase. Switch-on and switch-off signals for actuating the switch are generated by analyzing the information determined. The switch should not be switched on again until a particular minimum switch-off time has been reached.

Description

The present invention relates to a method and an apparatus for active power factor correction (PFC), i.e. by means of a switch clocked actively by a PFC control unit.

The technical field of the present invention is in particular that of power factor correction in AC/DC voltage power converters.

Power factor correction is used to influence the manner in which electrical appliances draw current from the power supply system. The AC mains voltage has a sinusoidal time profile, as is known. Ideally, therefore, the current drawn from the mains should also likewise have a sinusoidal time profile. This ideal case does not always arise, however, with it even being possible for the current to deviate considerably from a sinusoidal envelope. If the current drawn is not sinusoidal, harmonics are produced in the mains current, however. These harmonic currents in the supply system should be reduced with the aid of a power factor correction circuit.

DE 10 2004 025 597 A1 has disclosed a circuit for power factor correction, in which the inductance is charged and discharged repeatedly by means of a switch clocked by a PFC control unit by virtue of said switch closing and opening, and in which the discharging current of the inductance is supplied to the output of the converter via a diode (D). The PFC control unit in the form of an ASIC has only two pins. Control signals are output via one of the pins and parameters which are required for dimensioning the switch-on and switch-off time for the switch are monitored at the other pin. In this case, the switch is switched on again at the end of a switch-off time when the discharging current through the inductance has reached the zero line. This time is determined by monitoring the voltage on the high-potential side of the switch and is measured by means of a voltage divider, which is connected in parallel with the switch. The tap of the voltage divider forms a monitoring point, to be precise the only monitoring point, with said monitoring point being connected to the monitoring pin. The monitored voltage has a downwardly inflected time profile when the discharging current reaches the zero line. This event will be referred to below as a ZCD event (zero crossing detection).

In the known method and the known circuit, therefore, the DC output voltage can be monitored via the monitoring point when the switch is open. The DC output voltage can only be monitored as long as there is still current flowing through the diode, however. When the AC input voltage, i.e. the rectified and, as far as possible, smoothed mains voltage, which still comprises successive sinusoidal half-cycles of the same polarity, however, has a relatively low mean amplitude value, or when the load is low, the time segment within which the diode is conducting can be very short, with the result that the DC output voltage can only be sampled to an insufficient extent.

Circuits for power factor correction of the type under consideration here are normally regulated by virtue of the switch-on time T_ON being altered. Given a predetermined load, T_ON is theoretically constant over the entire angular range of 90 degrees of a mains half-cycle. However, when the load is reduced, T_ON also needs to be reduced correspondingly. Even when the DC output voltage V_BUS is monitored directly, the control range is restricted as a result of the above-mentioned temporally very short sampling pulses. Under such low-load conditions, the procedure which has therefore been adopted in the meantime is that the power correction circuit has been switched off entirely when V_BUS exceeds an upper voltage threshold and switched on again when V_BUS exceeds a lower voltage threshold. With such hysteresis regulation, however, the desired sinusoidal form of the input current can be maintained.

The invention is therefore based on the object of specifying, for a method for power factor correction of the type under consideration here and for the corresponding circuit, possibilities for generating reliable sampled values even at a low AC input voltage and/or under low-load conditions and thus ensuring continuous regulation of the DC output voltage.

The object as regards the method is achieved by the features of claim 1 and the object as regards the circuit is achieved by the features of claim 7.

Configurations of the solutions according to the invention are the subject matter of the dependent claims. In this case, the claims in their full scope should be included within the disclosure of the description so as to avoid repetition.

Exemplary embodiments will be described below with reference to the drawings, in which:

FIG. 1 shows a schematized circuit diagram of a circuit for power factor correction in an AC/DC voltage power converter;

FIG. 2 shows the dependence of the switch-off time T_OFF on the phase of a sinusoidal half-cycle of the rectified AC input voltage V_IN;

FIG. 3 shows a graphical representation of the current I_L flowing through the inductance L as a function of time t with three different ZCD events;

FIGS. 4 (a)-(c) show three oscillograms showing the time profile of the input current I_IN given different parameters;

FIG. 5 shows a further graphical representation of the current I_L flowing through the inductance L as a function of time t in a different view than that in FIG. 3;

FIGS. 6 (a)-(d) show four oscillograms showing the time profile of the input current I_IN given different parameters other than those in FIG. 5;

FIGS. 7 (a) and (b) show a circuit arrangement of two series-connected sample-and-hold circuits for determining V_BUS with the corresponding timing diagrams;

FIG. 8 shows two graphs, of which one shows the time profile of the actual monitored voltage V_BUS and the other shows the time profile of the sampled DC output voltage V_BUS;

FIG. 9 shows a simplified illustration of the PFC-ASIC shown in FIG. 1.

The power correction circuit shown in FIG. 1 is supplied with the sinusoidal mains voltage V_MAINS from the mains. Once it has passed a passive high-frequency filter F, said voltage is supplied to a bridge rectifier G. This results in a voltage comprising sinusoidal half-cycles of identical polarity being produced at the input capacitor C1. Although it could also be referred to as a DC input voltage which pulsates to a greater or lesser extent, it is referred to below as AC input voltage V_IN precisely because of its ripple and the need to match the input current to its waveform.

(In principle, the PFC circuit can also be supplied with power starting from a DC voltage instead of the mains AC voltage, as is the case in emergency lighting devices, for example).

The AC input voltage V_IN is supplied to a series circuit comprising an inductance L, an electronic switch in the form of a FET and a shunt resistor R1. By virtue of repeated closing and opening of the switch or by virtue of the fact that the FET is clocked with perpetual repetition, the inductance L is charged and discharged correspondingly. The current flowing through the inductance in the individual phases is denoted by I_L.

The inductance L is connected to the output of the circuit, represented by the output capacitance C2, via a diode D. The load is connected across the output

A series circuit comprising two resistors R2, R3, which are additionally connected in series with a shunt resistor R1, is connected in parallel with the FET. The shunt resistor R1 is also connected in series with the FET and has a much lower resistance value than R2 and R3. The node between the two resistors R2 and R3 with a higher resistance value is a common measuring point in the circuit for the parameters required for control. This common measuring point is connected to the single monitoring pin PIN 1 of a control unit PFC in the form of an ASIC. The ASIC also has a second pin, which is denoted as PIN 2 and is used for outputting control commands. In the present case, PIN 2 is connected to the gate of the FET and supplies the clock signals thereto, i.e. the commands to close or to open.

When the FET is conducting, the inductance is magnetically charged. The charging current I_L then flows via the FET and the shunt resistor R1 to ground, with the result that the voltage drop across R1 is a measure of the charging current and therefore also of the current I_FET flowing through the FET. This voltage drop is utilized during the charge phase for overcurrent monitoring and for calculating the AC input voltage V_IN. During the charge phase, the switched-on FET short-circuits the series circuit comprising the resistors R2, R3, with the result that V_mon at PIN 1 is a measure of the current I_FET flowing through the FET.

When the FET is switched off, the discharging current I_L flows via the diode D to the load. The diode D is conducting during the discharge phase and correspondingly has a very low resistance. Nevertheless, the DC output voltage V_BUS and the voltage V_S in the form of a voltage drop across the FET upstream of the diode D differ from one another slightly by the voltage drop across the conducting diode D. The voltage difference between V_BUS and V_S is only significant when the discharging current I_L approaches or crosses the zero line. In the case of this ZCD event, V_S demonstrates a downwardly directed inflection in the voltage, while V_BUS remains practically unchanged. The voltage V_mon applied to PIN 1 during the discharge phase is a measure of the voltage V_S in the form of a voltage drop across the series circuit comprising the resistors R1, R2, R3. V_mon therefore represents the DC output voltage V_BUS over the majority of the discharge phase and makes it possible to detect a ZCD event at the end of the discharge phase.

V_BUS is the value which is intended to be kept constant by means of regulation. It therefore needs to be available in digital form as an actual value not only during the discharge phase but also during the charge phase. Since, however, measurement is only possible in the discharge phase, V_BUS is sampled by the PFC-ASIC during the discharge phase, and is converted into a corresponding digital value and stored.

For effective monitoring of V_BUS, the switch-off time T_OFF needs to be long enough for the sampling. FIG. 2 shows the switch-off time T_OFF as a function of the phase angle of a sinusoidal half-cycle of the AC input voltage V_IN, which has a frequency of 100 Hz. In this case, the amplitude of the AC input voltage V_IN (corresponding to the mains voltage) should have a peak value of 230 V, and the DC output voltage V_BUS should have a mean value of 400 V. In the case of a relatively low DC input voltage V_IN or a relatively high DC output voltage V_BUS, the switch-off time is reduced further. A relatively large phase angle means a relatively high DC input voltage V_IN.

In order to be able to sample V_BUS satisfactorily, a minimum switch-off time T_OFF of 2 is assumed. This would mean that one 1 would remain, within which the FET drain voltage reaches the voltage value of V_BUS and can assume this value. It is clear from FIG. 2 that V_BUS sampling pulses cannot be generated over the entire phase angle range. However, when it is possible for sampling pulses to be generated at least over a considerable proportion of the phase angle range, this is sufficient for regulating V_BUS. When T_ON=0.5 μs, T_OFF is above 2 only over a very small proportion of the phase angle range. When, on the other hand, T_ON=2, T_OFF is above 2 over virtually 60% of the phase angle range. Firstly, there is therefore obviously the problem of how to make regulation possible over a sufficiently large proportion of the phase angle range under low-load conditions (resulting in a low T_ON). A second problem is that of how it is possible to guarantee that sampled values taken from V_BUS can be considered as reliable.

One solution to the first problem will be explained below with reference to FIG. 3. The solution consists in extending the switch-off time T_OFF beyond the time at which the diode D ceases to be conducting. This means, for example, that even when T_OFF is restricted to a temporal range of only 2-2.5, the entire temporal range available for the regulation can be much greater.

In FIG. 3, all of the times are related to T₀, namely the time at which the FET switches off, i.e. becomes non-conducting. Within the time period delimited by T₀ and T_GATE, the FET cannot switch on again, i.e. become conducting. This is intended to prevent the FET from switching on again as a result of a fault which has been caused by the FET switching off. T_GATE can therefore be referred to as the interference suppression time and needs to be selected such that it is long enough to avoid erroneous triggering and is short enough to be able to detect reliable trigger signals, in particular when said signals are taken close to the ZCD crossing point, at which the discharging current reaches or crosses the zero line. When a reliable trigger signal falls within the temporal range delimited by T_GATE, the FET should not switch on again until time T_OFF-MAX. For the simulation yet to be explained below, a value of 0.5 μs has been assumed for T_GATE.

If an event ZCD1 is detected before T_OFF-MIN has elapsed (Case1), the FET should not be switched on again without delay. Instead, the control circuit should wait until T_OFF-MIN and only then switch on the FET again.

If no ZCD event is detected before T_OFF-MIN has been reached (Case2), the FET should not be switched on again. The circuit should then continue to operate up to time ZCD2, at which a ZCD event is detected. Then, the FET should be switched on again without a delay.

When no ZCD event is still detected even after T_OFF-MIN, the FET should be switched on again at time T_OFF-MAX (Case3). This ensures that the PFC does not cease to function. In the simulation yet to be explained, a value of 150 μs has been assumed for T_OFF-MAX.

The time profiles shown in FIG. 4 for input currents I_IN for various load conditions have been generated by a simulator, with only the following comments being made in relation to the simulator for reasons of simplicity. The simulator is connected to the monitoring point between the resistors R2 and R3 in FIG. 1 and contains a ZCD detector and an overcurrent detector. Both evaluate the voltage V_mon present at the monitoring point. In addition, the simulator is connected to two control inputs. T_ON can be set at one of these control inputs, and T_OFF-MIN can be set at the other. T_ON is varied over a limited range in order to ensure that V_BUS can be sampled effectively. T_OFF-MIN is increased when the load is low. The variation range of T_OFF-MIN is between 1-150 μs.

The three simulation results in FIG. 4 show the input current I_IN given three different loads over a variation range of approximately 20:1. It can be seen that the regulation is effective over the entire range since all three input currents I_IN illustrated simulate a sinusoidal waveform. This is possible without it being necessary for the PFC mode to be switched off under low-load conditions. Such a result could hardly be achieved with a system in which only T_ON is varied as a manipulated variable.

In the above-described control system, however, there is the risk of faults occurring in the waveform of the current I_L when T_OFF-MIN is increased. As will be shown below, this does not need to be the case.

FIG. 5 illustrates a time T_ACTIVE which defines the end of the time segment in which the diode D is conducting. In addition, a time K·T_ACTIVE, where K>1, is specified in said figure, which defines the end of a time segment which includes a smaller time segment in which there is no current flowing either through the diode D or through the FET.

The mean value I_AV, of the current I_L during the time segment defined by K·T_ACTIVE is as follows:

I _AV =I _PEAK/2·K,

where I_PEAK is the peak current of the current I_L.

By maintaining K as the constant factor over the 90 degrees phase range of the AC input voltage, the mean value of the current I_AV, can be reduced without any interference occurring in the waveform of the current. T_OFF-MIN is now variable and is calculated as follows:

T _OFF-MIN =K·T _ACTIVE −T _ON

Since T_ACTIVE can be measured and T_ON is known, T_OFF-MIN can be calculated easily. It is possible to perform the calculation within the present clock, with the calculation operation being ended by a ZCD event and the event being introduced into the control operation within a few subsequent clocks.

As an alternative to this, a measurement which has been performed within a preceding clock can be used during the present clock for a calculation when there is thus more time available.

FIG. 6 shows the simulated waveforms of the input current I_IN as a function of time t for a PFC controller, wherein the adjustment range for T_ON is 2-5 and K_MAX is limited to the value 15. An entire range of 30:1 is possible when K is limited to 15 and T_OFF-MAX is limited to 150 μs.

If the ZCD signal were to appear before time T_GATE (not illustrate), it would not be taken into consideration. In this case, the switch-off time T_OFF for the FET could be extended to T_OFF-MAX (likewise not illustrated), provided that noise or another interference signal, such as ringing, for example, has not produced a false ZCD trigger signal at the drain electrode of the FET. An interference signal caused by ringing at the drain electrode of the FET has the same effect as a large number of false ZCD trigger signals. As long as a false trigger signal is produced prior to T_OFF-MIN, there is no reversal effect during sampling. For ringing it is probable that false ZCD trigger signals are generated up to T_OFF-MIN. As a result of general noise, on the other hand, false ZCD trigger signals could be generated anywhere.

A PFC-ASIC could in principle be constructed as follows and as shown in FIG. 9 on the basis of the above-explained knowledge. The voltage V_mon is present at the single monitoring PIN 1. This voltage represents the current I_FET flowing through the FET during the charge phase. This current is supplied to one input of an overcurrent comparator. A current threshold value signal is supplied by the FET controller to the other input. The comparator compares the signals and outputs a switch-off signal for the FET at the FET driver when the current threshold value is exceeded.

V_mon is also evaluated during the discharge phase. The output product is the sampled DC output voltage V_BUS. This is supplied to the FET controller, which stores it as an actual value for the control of the DC output voltage, with the result that it is also available during the charge phase.

Finally, V_mon is also evaluated by means of a ZCD (zero crossing detector), which responds to the negative inflection in the voltage V_mon occurring at the end of the discharge phase and generates a ZCD signal, which is likewise supplied to the FET controller.

The FET controller processes the signals supplied thereto and generates from said signals a switch-on signal On for the FET, which it then supplies to the FET driver. The FET driver for its part passes the switch-on signals On and the switch-off signals Off onto the control PIN 2, from where the FET is switched.

The FET controller calculates, on the basis of the information available to it, when the FET needs to be switched on again at the end of a discharge phase, possibly with a delay, and when it needs to be switched off so as to end a charge phase. Correspondingly, it generates switch-on signals On and switch-off signals Off which it supplies to the FET driver, which then for its part switches the FET on or off via PIN 2. The calculation of a possible delay of T_OFF is performed as has been explained above in connection with FIGS. 3 and 5.

Information relating to possible low-load conditions is provided to the FET controller from the monitoring of V_BUS. The information relating to the AC input voltage V_IN is provided to the FET controller by evaluation of I_FET during the charge phase via the two sample-and-hold circuits.

Claims

1. A method for power factor correction for an AC/DC voltage converter, wherein a DC voltage or a rectified AC input voltage feeds an inductance,the inductance is repeatedly charged and discharged by a clocked switch by virtue of said switch closing and opening,the discharging current from the inductance is supplied to the output of the converter via a diode,during the discharge phase, a voltage Vmon corresponding to the DC output voltage VBUS is detected,a temporal range is established at which the discharging current reaches or crosses a zero line at the end of a discharge phase,while evaluating determined information (VBUS and ZCD), switch-on and switch-off signals for clocking the switch are generated, andthe switch is switched on again no earlier than after a specific minimum switch-off time has elapsed.

2. The method as claimed in claim 1, wherein the switch is switched on again no later than after a specific maximum switch-off time has elapsed.

3. The method as claimed in claim 2, wherein ZCD signals which are detected before the minimum switch-off time has elapsed cause the switch to switch on again when the minimum switch-off time has elapsed.

4. The method as claimed in claim 2, wherein ZCD signals which are detected once the minimum switch-off time has elapsed but before the maximum switch-off time has elapsed cause the switch to switch on again without a delay.

5. The method as claimed in claim 2, wherein, when no ZCD signals are detected before the maximum switch-on time has elapsed, the switch is switched on again when the maximum switch-off time has elapsed.

6. A power factor correction circuit for (a) an inductance, which is fed by a DC voltage or a rectified AC input voltage,(b) a clocked switch, by which the inductance is charged and discharged repeatedly by virtue of said switch closing and opening,(c) a diode, via which the discharging current of the inductance is supplied to the output of the converter,(D) means for sampling a voltage Vmon corresponding to the DC output voltage VBUS during the discharge phase,(e) means for establishing a temporal range at which the discharging current reaches or crosses a zero line at the end of a discharge phase,(f) means for evaluating determined information and for generating switch-on and switch-off signals for clocking the switch, and(g) timing means that store the value for a specific minimum switch-off time for switching the switch on again and predetermine said value for generating the clock signal.

7. The power factor correction circuit as claimed in claim 6, wherein the timing means additionally store values for a specific maximum switch-off time and an interference suppression time for switching the switch on again and predetermine said values for generating the clock signal.

8. The power factor correction circuit as claimed in claim 6, further containing an overcurrent comparator, with a voltage being supplied to one input of said comparator, said voltage representing, during the charging phase, the current flowing through the switch, with a voltage being supplied to another input of said comparator, said voltage representing an upper threshold value for the current flowing through the switch, and said overcurrent comparator generating a switch-off signal for the switch when the current flowing through the switch reaches the threshold value.

9. The power factor correction circuit as claimed in claim 6, wherein a series circuit comprising two resistors, which form a voltage divider, is provided upstream of the diode in parallel with the switch, the series circuit is connected in series with a shunt resistor, through which the current flowing through the switch during the charging phase is passed, anda node between the two resistors forming the series circuit forms a common node for monitoring circuit parameters, said node being connected to a control unit.

10. The power factor correction circuit as claimed in claim 9, in which the control unit is in the form of an ASIC with only one common monitoring pin and only one control pin.

11. A PFC-ASIC, containing functional modules of a power correction circuit as claimed in claim 6, and (a) an FET controller having one input with one input connected to the monitoring pin, with another input connected to the FET controller for the purpose of picking up a threshold value for the current flowing through the switch, and which generates, at its output, a switch-off signal for the switch when the current flowing through the switch reaches the threshold value.

12. An operating device for light-emitting means, having a power factor correction circuit as claimed in claim 6.

13. A luminaire, having an operating device as claimed in claim 12 and one or more connected light-emitting means.

14. A luminaire as claimed in claim 13, wherein the light-emitting means is selected from the group consisting of gas discharge lamps, LEDs, and OLEDs.

15. An operating device for light-emitting means, having a a PFC-ASIC as claimed in claim 11.

16. A luminaire, having an operating device as claimed in claim 15 and one or more connected light-emitting means.

17. A luminaire as claimed in claim 16, wherein the light-emitting means is selected from the group consisting of gas discharge lamps, LEDs, and OLEDs.