Patent Application
20180196454
Power management is an issue for circuits having several power supplies, especially when the circuits and power supplies are located on a single chip, such as a system-on-chip (SoC) circuit. Some of these circuits are powered by one or more DC-to-DC converters, which are followed by numerous low dropout regulators (LDOs), wherein each LDO is associated with a power domain. It is not uncommon to have multiple power domains on a single SoC circuit. These power domains may include digital signal processing cores, several banks of memory circuits, analog units, Bluetooth radio, and audio units.
A load step on an LDO occurs when the load powered by an LDO changes. Maintaining the accuracy of voltages output by LDOs during load step conditions from no load to full load is important for proper operation of the power domains. One method of maintaining accuracy during a load step is by the inclusion of an external load capacitor coupled to each LDO. With so many LDOs on each circuit and the circuits becoming smaller, the use of an external load capacitor for each of the LDOs is not practical because of the size and costs of the external capacitors.
Low dropout regulators (LDOs) are disclosed herein. An example of an LDO includes an error amplifier having a first input and a second input, wherein the first input is for coupling to an output of the LDO and the second input for coupling to a reference voltage. The error amplifier has an output with a voltage that is proportional to the difference between the output voltage and the reference voltage. A second amplifier is coupled between the error amplifier and the output of the LDO. A gain boost amplifier is coupled between the error amplifier and the second amplifier. The gain boost amplifier increases DC gain of the LDO in response to a load step on the output.
Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
As circuits become more integrated, they have many different devices, components, and subcircuits that often operate independent of each other or at least partially independent of each other. As used herein, the term circuit can include a collection of active and/or passive elements that perform a circuit function such as an analog circuit or control circuit. The term circuit can also include an integrated circuit where all the circuit elements are fabricated on a common substrate. These different systems typically require their own power source or power domain, with many systems requiring a plurality of power domains. Examples of these different systems include processors, memory devices, radio transmitters and receivers, and audio units. A circuit, such as an integrated circuit, may have several of these systems and may have inputs for only one or two input voltages. These input voltages are coupled to DC-to-DC converters that provide power to a plurality of low dropout regulators (LDOs), wherein each LDO provides power to each of the systems. It is not uncommon to have as many as fifty LDOs in a single circuit.
An LDO converts and regulates a high input voltage to a lower output voltage. A dropout voltage is the amount of headroom required to maintain a regulated output voltage. Accordingly, the dropout voltage is the minimum voltage difference between the input voltage and the output voltage required to maintain regulation of the output voltage. The input voltage minus the voltage drop across a pass element within the LDO equals the output voltage. For example, a 3.3V regulator that has 1.0V of dropout requires the input voltage to be at least 4.3V. Another typical application involving LDOs is for generating 3.3V from a 3.6V Li-Ion battery, which requires a much lower dropout voltage of less than 300 mV.
A voltage divider 108 consisting of resistors R11 and R12 is coupled between the output 104 and a common node, which in the example of
The gate of the pass transistor QPASS is coupled to a pass capacitor C11 and the output of a differential amplifier 110. The differential amplifier 110 has a first input coupled to a reference voltage VREF and a second input coupled to node N11, which has the feedback voltage VFB present during operation of the LDO 100. The output of the differential amplifier 110 is proportional to the difference between the reference voltage VREF and the feedback voltage VFB and serves to drive the gate of the pass transistor QPASS. If the feedback voltage VFB is less than the reference voltage VREF, the differential amplifier 110 drives the gate of the pass transistor QPASS harder to increase the output voltage VOUT. Likewise, if the feedback voltage VFB is greater than the reference voltage VREF, the differential amplifier 110 reduces the drive on the gate of the pass transistor QPASS, which lowers the output voltage VOUT.
Conventional LDOs, such as the LDO 100, require some minimum load capacitance CL and/or minimal ESR, noted as resistor RESR, for stability/compensation. For example, when the LDO 100 undergoes a load step, meaning that a load coupled to the output 104 of the LDO 100 changes, transients with significant settling times can be generated. The trend with conventional LDOs is for lower quiescent current, such as quiescent currents limited to less than ten percent of the maximum load current. The maximum load current is the maximum current that may pass through the pass transistor QPASS. These low quiescent currents, along with other factors, cause the transient reaction time during a load step to be in the microsecond range, which is not acceptable in many applications. Larger load capacitance in the load capacitor CL reduces the transient settling time by improving the compensation of the LDO 100. However, due to limitations in silicon die area, on-chip load capacitors have low capacitance and result in longer transient settling times, which is not acceptable in many applications. Resolving this transient problem requires the use of bulky, off-chip load capacitors which increase board area and component count of the circuit in which the LDO 100 is located. Some LDOs have been developed that can operate with or without a load capacitance and have extremely fast reaction time in response to load steps. However, these fast responding LDOs have low gain for stability purposes, which has the drawback of low accuracy in their output voltages. Increasing the gain of these LDOs increases the accuracy of the output voltage, but it has the drawback of decreasing the stability, which leads to stability problems during load steps.
The LDOs described herein provide stability by way of compensation under load step conditions with high gain, which yields high accuracy. The high gain and stability is achieved without the addition of load or compensation capacitors. The LDOs provide different gains depending on the difference between the input and output voltages. A gain boost amplifier nested within the LDO serves to increase the DC accuracy of the LDO after the load step. Several different circuit schematic diagrams are described herein as examples of the LDOs. These schematic diagrams are not limiting in that variations of the circuits by those skilled in the art may perform the functions of the LDOs described herein.
The outputs of the error amplifier 214 are coupled to the sources of transistors Q25 and Q26 that form a common gate amplifier. Accordingly, the voltages VG1 and VG2 are present at the sources of transistors Q25 and Q26 during operation of the LDO 200. The drains of transistors Q25 and Q26 are coupled to a node N21, which is coupled to a current source 121. Node N21 is also coupled to the gate of a transistor Q27, wherein the drain of transistor Q27 is coupled to the sources of transistors Q21 and Q22 in the error amplifier 214. The voltage on node N21 and the gate of transistor Q27 is a feedback voltage VFB. The source of transistor Q27 is coupled to a node, such as ground as shown in
The gate of the pass transistor QPASS is driven by the output of the error amplifier 214 by way of transistor Q24, which serves as a portion of a second amplifier described herein. A voltage at the gate of the pass transistor QPASS changes the source-to-drain resistance of the pass transistor QPASS. Transient conditions, such as those resulting from load steps on the output 208, are detected by monitoring the error voltage VE, which is the difference between the reference voltage VREF and output voltage VOUT. When the error voltage VE is negligible, the voltages VG1 and VG2 are substantially the same, which causes the current through transistors Q25 and Q26 to be substantially the same. Accordingly, the current through each of transistors Q25 and Q26 is half of the current generated by the current source I21. This sets the currents through the transistors Q21 and Q22 in the error amplifier 214 to be substantially equal. The error amplifier 214 operates in a quiescent state in these conditions. The voltages VG1 and VG2 set the currents in the error amplifier 214 by setting input stage currents.
When the error voltage VE rises, the voltages VG1 and VG2 differ. When the error voltage VE is greater than a predetermined value, the smaller voltage of VG1 and VG2 triggers a higher current in the corresponding transistors Q25 and Q26, which forces the feedback voltage VFB to increase. As a result, the error amplifier 214 leaves its quiescent state. This increase in the feedback voltage VFB increases the tail current ITAIL flowing through transistor Q27 in proportion to the error voltage VE. Thus, the tail current ITAIL in the error amplifier 214 increases in proportion to the error voltage VE, which provides for fast transient response. More specifically, this change in tail current ITAIL results in higher current drive in the input stage to move the gate of the pass transistor QPASS faster during the load step, so as to minimize transients during the load step. Non-linearity in the LDO 200 is provided by the combination of transistors Q28/Q29 and Q23/Q210 during these conditions. In some examples where there is a ratio of four in the transistors, there is 1000x tail current increase for an error voltage VE of 100 mV.
As shown in
In some examples, the gain boosting amplifier 402 is designed to be slowed by the use of resistor R51 and capacitor C51 so that it does not affect the stability of the LDO 500. For example, resistor R51 and capacitor C51 form a filter that slows the amplifier 402. In some examples, the filter is not included in the LDO 500.
Although illustrative embodiments have been shown and described by way of example, a wide range of alternative embodiments is possible within the scope of the foregoing disclosure.
