Claims
- 1. A method of performing an atomic read from a first location in a memory into a first register and a second location in the memory into a second register for use in a processor that does not provide a two word atomic read capability,
- 2. The method in claim 1 wherein:
the loading in step (B) is an advanced speculative load; and the method further comprises: D) testing a success of the advanced speculative load in step (B) after completing the load in step (B).
- 3. The method in claim 1 wherein:
- 4. The method in claim 1 wherein:
- 5. The method in claim 4 wherein:
- 6. The method in claim 4 wherein:
the gate flag corresponding to the first location in the memory is an otherwise unused bit in the first location in the memory.
- 7. The method in claim 4 wherein:
the gate flag corresponding to the first location in the memory is a bit in an array separate from the first location in the memory.
- 8. The method in claim 1 wherein:
- 9. The method in claim 1 which further comprises:
D) performing an advanced speculative load from a third location in the memory into a third register; E) loading a fourth register from a fourth location in the memory after step (D); and F) testing a success of the advanced speculative load in step (E) after completing the load in step (D).
- 10. The method in claim 9 which further comprises:
G) repeating steps (A), (B), and (C) if the advanced speculative load in step (A) was determined in step (C) to have failed; and H) repeating steps (A), (B), (C), (D), (E), and (F) if the advanced speculative load in step (D) was determined in step (F) to have failed.
- 11. Software stored in a Computer Software Storage Medium for performing an atomic read from a first location in a memory into a first register and a second location in the memory into a second register for use in a processor that does not provide a two word atomic read capability,
- 12. The software in claim 11 wherein:
the loading in set (B) includes an advanced speculative load; and the software further comprises: D) a set of computer instructions for testing a success of the advanced speculative load in set (B) after completing the load in set (B).
- 13. The software in claim 11 wherein:
- 14. The software in claim 11 wherein:
- 15. The software in claim 14 wherein:
- 16. The software in claim 14 wherein:
the gate flag corresponding to the first location in the memory is an otherwise unused bit in the first location in the memory.
- 17. The software in claim 14 wherein:
the gate flag corresponding to the first location in the memory is a bit in an array separate from the first location in the memory.
- 18. The software in claim 11 wherein:
- 19. The software in claim 11 which further comprises:
D) a set of computer instructions for performing an advanced speculative load from a third location in the memory into a third register; E) a set of computer instructions for loading a fourth register from a fourth location in the memory after set (D); and F) a set of computer instructions for testing a success of the advanced speculative load in set (E) after completing the load in set (D).
- 20. The software in claim 19 which further comprises:
G) a set of computer instructions for repeating sets (A), (B), and (C) if the advanced speculative load in set (A) was determined in set (C) to have failed; and H) a set of computer instructions for repeating sets (A), (B), (C), (D), (E), and (F) if the advanced speculative load in set (D) was determined in set (F) to have failed.
- 21. A computer readable Non-Volatile Storage Medium encoded with software for performing an atomic read from a first location in a memory into a first register and a second location in the memory into a second register for use in a processor that does not provide a two word atomic read capability,
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is related to our copending patent applications assigned to the assignee hereof:
[0002] “DIFFERENT WORD SIZE MULTIPROCESSOR EMULATION” by David A. Egolf, filed Sep. 8, 1998, with Ser. No. 09/149,261.
[0003] “METHOD AND DATA PROCESSING SYSTEM FOR PERFORMING ATOMIC MULTIPLE WORD WRITES” by Bruce Noyes, filed of even date herewith and assigned to the assignee hereof.