Patent Application
20080263340
Transient faults, triggered by alpha particles or cosmic radiation, are increasingly becoming a problem for integrated semiconductor circuits. Due to diminishing structure widths, declining voltages and higher clock frequencies, there is an increased probability of a voltage peak, caused by an alpha particle or cosmic radiation, falsifying a logic value in an integrated circuit. This may result in an erroneous calculation. It is, therefore, essential that such faults be reliably detected in safety-related systems, particularly in motor vehicles. In safety-related systems, such as in ABS control systems in motor vehicles, which necessitate reliable detection of malfunctions in the electronics, redundancies for detecting faults are typically employed in the relevant control devices of such systems. Thus, for example, in known ABS systems, the complete microcontroller is duplicated in each instance, the entire ABS functions being redundantly calculated and checked for conformity. If there is a discrepancy in the results, the ABS system is switched off.
The essential components of a microcontroller are memory modules (such as RAM, ROM, cache), the cores and the input/output interfaces, the so-called peripherals (for instance A/D converter, CAN interface). Since the memory elements are able to be effectively monitored using check codes (parity or ECC), and the peripherals are frequently monitored as part of a sensor signal path or actuator signal path as a function of the particular application, an additional redundancy approach is provided by merely doubling the cores of a microcontroller.
Such microcontrollers having two integrated cores are also known as dual-core architectures. Both cores execute the same program segment redundantly and in a clock-synchronized mode (lockstep mode); the results of the two cores are compared, and a fault is then recognized in the conformity-check comparison. This configuration of a dual-core system may also be described as a comparison mode.
Dual-core architectures are also used in other applications to enhance performance, thus to increase performance. The two cores execute different programs, program segments and commands, thereby making it possible to increase performance, so that such a dual-core system configuration can also be termed performance mode. Such a system is also known as a symmetrical multiprocessor system (SMP).
These systems are expanded by using software to switch between these two modes, in that a special address is accessed, and specialized hardware devices are used. In the comparison mode, the output signals of the cores are compared to each other. In the performance mode, the two cores function as a symmetrical multiprocessor system (SMP) and execute different programs, program segments or instructions.
In motor vehicle systems in which such a computer system is employed, it is necessary to check the mode in order to safeguard applications. It is, therefore, the object of the present invention to devise methods and means for analyzing such mode information.
A method for analyzing a signal from a computer system having at least two execution units is advantageously employed,
in the computer system, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, characterized in that in the computer system, a mode signal and/or changes in the mode signal, which are indicative of the current operating mode, are generated, and at least the changes in the mode signal and/or this mode signal itself are made available outside of the computer system for analysis purposes.
A method is advantageously employed in which the mode signal and/or the changes in the mode signal is/are analyzed in a component that is external to the computer system.
A method is advantageously employed in which the mode signal and/or the changes in the mode signal is/are analyzed in a safeguarding component, in particular in a watchdog.
A method is advantageously employed in which the mode signal and/or the changes in the mode signal is/are analyzed in a processing unit, in particular in a second computer system.
A method is advantageously employed in which an analysis is carried out to the effect that a specifiable operation is enabled only within a specifiable operating mode as a function of the mode signal and/or the changes in the mode signal.
A method is advantageously employed in which an analysis is carried out to the effect that a specifiable functionality of the external component is enabled only within a specifiable operating mode as a function of the mode signal and/or the changes in the mode signal.
A method is advantageously employed in which the external component monitors the change to the comparison mode.
A method is advantageously employed in which the external component is only driven in a predefinable operating mode, and this is monitored on the basis of the mode signal and/or the changes in the mode signal.
A method is advantageously employed in which the external component contains information indicating those switchover signals, in particular interrupt signals, in response to which the operating modes are changed, and this is monitored on the basis of the mode signal and/or the changes in the mode signal.
A method is advantageously employed in which the external component is only driven in a predefinable operating mode, and this is monitored on the basis of the mode signal and/or the changes in the mode signal.
A method is advantageously employed in which the external component contains information indicating those switchover signals, in particular interrupt signals, in response to which the operating modes are changed, and this is monitored on the basis of the mode signal and/or the changes in the mode signal.
A method is advantageously employed in which, as an analysis, a fault detection is carried out in such a way that a query-reply communication takes place.
A method is advantageously employed in which, as an analysis, a fault detection is carried out in such a way that the mode signal and/or the changes in the mode signal is/are compared to a predefined piece of information and, in the case of divergency or conformity, the existence of faults being ascertained.
A method is advantageously employed in which, as an analysis, a fault detection is carried out in such a way that a piece of information generated as a function of the mode signal and/or the changes in the mode signal is compared to a predefined piece of information and, in the case of divergency or conformity, the existence of faults being ascertained.
A method is advantageously employed in which, on the basis of the mode signal and/or the changes in the mode signal, a change in the operating modes is monitored by a component external to the computer system.
A method is advantageously employed in which the mode signal and/or the changes in the mode signal is/are safeguarded by at least one piece of additional information.
A method is advantageously employed in which the mode signal and/or the changes in the mode signal are safeguarded by at least doubling the mode signal and/or the changes in the mode signal.
A method is advantageously employed in which the mode signal and/or the changes in the mode signal is/are safeguarded as a dual-rail signal.
A method is advantageously employed in which more than two operating modes are provided, between which switchover operations may be carried out.
A method is advantageously employed in which a configurable operating-mode characteristic is provided for indicating the particular operating mode.
A method is advantageously employed in which a configurable indicator variable is provided for indicating the particular operating mode.
A method is advantageously employed in which, on the basis of the mode signal and/or the changes in the mode signal, a fault detection is carried out, within the course of this fault detection, at least one error signal being generated.
A method is advantageously employed in which a counter is employed in the external component.
A method is advantageously employed in which the mode signal is multi-valued in such a way that it is able to represent more than two modes.
A device for analyzing a signal from a computer system having at least two execution units is advantageously employed, in the computer system, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, characterized in that means are contained in the computer system, which are designed in such a way that they generate a mode signal and/or changes in the mode signal, which are indicative of the current operating mode, and at least the changes in the mode signal and/or this mode signal itself are made available outside of the computer system for analysis purposes.
A device is advantageously employed which contains a component external to the computer system that analyzes the mode signal and/or the changes in the mode signal.
A device is advantageously employed in which the external component is a safeguarding component, in particular a watchdog.
A device is advantageously employed in which the watchdog is a decrementing watchdog.
A device is advantageously employed in which the external component is an actuator or a component for controlling an actuator.
A device is advantageously employed in which the mode signal is generated in such a way that it is able to represent more than two modes.
Other advantages and advantageous embodiments are derived from the features of the claims and of the specification.
In a flow chart representation,
In a flow chart in
A processor, a core, a CPU, as well as an FPU (floating point unit), a DSP (digital signal processor), a coprocessor or an ALU (arithmetic logical unit) may all be termed execution unit in the following.
The present invention relates to a multiprocessor system G60, as shown in
In the performance mode, different instructions, program segments or programs are executed in parallel in the different execution units. In this operating mode, comparison unit G20 is deactivated. In this operating mode, switchover unit G50 is configured in such a way that each execution unit G10a, G10b is linked to a system interface G30a, G30b. In this context, execution unit G10a is linked to system interface G30a, and execution unit G10b to system interface G30b.
In the comparison mode, the same or substantially similar instructions, program segments or programs are processed in both execution units G10a, G10b. These instructions are beneficially processed in clock-controlled synchronism, however, a processing in asynchronous operation or with a defined clock pulse offset is also conceivable. The output signals of execution units G10a, G10b are compared in comparison unit G20. In the case of a difference, a fault is detected, and appropriate measures may be taken. These measures may trigger an error signal, initiate a fault handling, actuate switches, or constitute a combination of these and other conceivable measures. In one variation, switchover unit G50 is configured in such a way that only one signal is transmitted to system interfaces G30a, G30b. In another configuration, the effect of the switchover unit is such that only the compared and thus substantially identical signals are transmitted to system interfaces G30a, G30b.
Independently of the currently active mode, desired switchover detection G40 detects a request to switch to a different mode.
In one specific embodiment of the above described subject matter, switchover unit G50 and comparison unit G20 may be combined to form one shared switchover and comparison unit (SCU) G70, as shown in
In another specific embodiment, as shown in
Unless indicated otherwise, it is assumed in the following that a unit for desired switchover detection G40 and a combined switchover and comparison unit G70 are present.
A typical example of the switchover and comparison component, also for use with more than two execution units, is shown in
This figure illustrates how the different conceivable modes may be formed. To this end, the logic component of a switching logic N110 is included in this figure. This component does not necessarily need to be provided as a separate component. What is decisive is that the described functions are realized in the system. Switching logic N110 first establishes how many output signals are actually present. It also establishes which input signals contribute to which output signals. In this context, one input signal may contribute to exactly one output signal. Formulated mathematically, the switching logic thus defines a function that assigns one element of set {N160, . . . , N16n} to each element of set {N140, . . . , N14n}.
For each of outputs N16i, processing logic N120 then establishes the form in which the inputs contribute to this output signal. This component also does not necessarily need to be present as a separate component. Decisive, again, is that the described functions be implemented in the system. To describe the different variations exemplarily, it is assumed, without limiting universality, that output N160 is generated by signals N141, . . . , N14m. If m=1, this simply corresponds to the signal being switched through; if m=2, then signals N141, N142 are compared, as described, for example, with regard to the comparator in
In the case that m≧3, a plurality of options is provided.
A first option provides for comparing all signals, and, if at least two different values are present, for a fault to be detected that may optionally be signaled.
A second option provides for undertaking a k out of m selection (k>m/2). This may be implemented through the use of comparators. An error signal may be optionally generated when it is ascertained that one of the signals is deviant. A possibly differing error signal may be generated when all three signals are different.
A third option provides for supplying these values to an algorithm. This may represent, for instance, the forming of an average value, a median value, or the use of a fault-tolerant algorithm (FTA). Such an FTA is based on deletion of the extreme values of the input values and on a type of averaging of the remaining values. This averaging process may be undertaken for the entire set of the remaining values or preferably for a subset that is easily formed in HW. In such a case, it is not always necessary to actually compare the values. In the averaging operation, it is merely necessary to add and divide, for example; FTM, FTA or median value require partial sorting. If indicated, an error signal may optionally be output here as well, given high enough extreme values.
For the sake of brevety, these various mentioned options for processing a plurality of signals to form one signal are described as comparison operations.
Thus, the task of the processing logic is to establish the exact form of the comparison operation for each output signal, and thus also for the corresponding input signals. The combination of the information of switching logic N110 (that is, the above mentioned function) and the processing logic (that is, the establishment of the comparison operation per output signal, i.e., per functional value) is the mode information; and this determines the mode. Generally, this information is naturally multi-valued, i.e., not representable by only one logic bit. Not all theoretically conceivable modes are practical in a given implementation; preferably, one limits the number of permitted modes. It is important to note that, in the case of only two execution units, where there is only one comparison mode, the entire information may be condensed to only one logic bit.
A switch from a performance mode to a comparison mode is generally characterized in that execution units, which, in the performance mode, are mapped to different outputs, are mapped to the same output in the comparison mode. This is preferably implemented in that a subsystem of execution units is provided, in which, in the performance mode, all input signals N14i, which are to be considered in the subsystem, are directly switched to corresponding output signals N16i, while, in the comparison mode, they are all mapped to an output. Alternatively, such a switchover operation may also be implemented by altering pairings. The explanation for this is that, generally, it is not possible to speak of the one performance mode and the one comparison mode, although, in one specific embodiment of the present invention, the number of permitted modes may be limited in such a way that this general case does apply. However, it is always possible to speak of a switchover from a performance mode to a comparison mode (and vice versa).
Software-controlled, dynamic switchover operations between these modes may be dynamically carried out during operation. In this context, the switchover operation is triggered by the execution of special switchover instructions, special instruction sequences, explicitly identified instructions or in response to the accessing of specific addresses by at least one of the execution units of the multiprocessor system.
Fault-switching logic N130 collects the error signals, which are generated by the comparators, for example, and may optionally switch outputs N16i to passive by interrupting the same via a switch, for instance.
For the most part, however, the examples in the following focus on two execution units suited for presenting most of the concepts.
Different methods may be used for encoding the switchover between the modes. One possible method requires that special switchover commands be used, which are detected by unit for desired switchover detection G40. Another possible method for encoding the switchover operation is defined by the accessing of a special memory area, which is again detected by unit for desired switchover detection G40. In another method, an external signal, signaling a switchover operation, is evaluated in unit for desired switchover detection G40. In the following, a method is described which employs unused bit combinations in the existing instruction set of the processor. A special advantage of this method is that existing development environments (assemblers, compilers, linkers, debuggers) may continue to be used.
Therefore, the existing development environment provided for single-processor systems may be used for the software development. This may be implemented, for example, by defining a macro “SWITCH MODE TO PM” and a macro “SWITCH MODE TO VM” which, at an appropriate location in the code, inserts appropriate bit combinations that are undefined within the above defined meaning.
The use of this combination is then defined as a general “SWITCH” macro. This then effects a change of the current mode, as a function thereof, into the other respective mode. If more than two different modes are present in the system, then this method requires that more such combinations be available; preferably, one may then be used for each mode for purposes of switchover identification.
In accordance with the present invention, the switchover request is then encoded by a bit combination that is not defined in the instruction set. These may not be processed in the usual manner within an execution unit G210a, G210b. For this reason, an additional pipeline stage (REPLACE stage) G230a, G230b is proposed, which recognizes the corresponding bit combinations and replaces them with neutral bit combinations for further processing. To this end, the “NOP” (no operation) instruction is advantageously used. A NOP instruction is characterized in that it does not change the internal state of the execution unit, except for the instruction indicator. In the process, REPLACE stage G230a, G230b is inserted following the typically first stage, FETCH stage G220a, G220b; and non-defined bit combinations in the assembler, which are combined into one unit here, are inserted before the remaining pipeline stages G240a, G240b.
In accordance with the present invention, the implementation, presented here, of a unit for desired switchover detection G40 as special pipeline stage G230a, G230b in a pipeline unit G215a, G215b will generate additional signals G250a, G250b in response to detection of a corresponding bit combination for switchover, thereby signaling to a separate switchover unit and comparison unit G260 that the processing mode must be changed.
REP stages G230a, G230b are preferably situated between FET G220a, G220b and the remaining pipeline stages G240a, G240b in pipeline units G215a, G215b of execution units G210a, G210b. In the process, REP stages G230a, G230b detect the corresponding bit combinations and, in this case, route NOP instructions to the remaining stages G240a, G240b. At the same time, signal G250a or G250b in question is activated. In all other cases, REP stages G230a, G230b have neutral performance characteristics; i.e., all other instructions are passed on, unchanged, to remaining stages G240a, G240b.
In a flow chart representation,
The proposal described here presupposes a unit (designated ID unit) or method which enable each execution unit to ascertain its individual number or unit ID. In a system having two execution units, for example, one execution unit is able to ascertain number 0 for itself, and the other number 1 for itself. In a system having more than two execution units, the numbers are assigned and, respectively, ascertained correspondingly. This ID does not make the distinction between a comparison mode and a performance mode, but denotes an execution unit injectively. The ID unit may be included in the respective execution units, implemented, for example, as a bit or bit combination in the processor status register or as a register of its own, or as a single bit or as a unit that is external to the execution units and that delivers the appropriate ID upon request.
Once the execution units have made the switch to the performance mode in accordance with a switchover request, the comparison unit is, in fact, no longer active, but the execution units still execute the same instructions. This is due to the fact that the instruction indicators, which indicate the place in the program where an execution operation will be performed in the next step or is currently being performed, are not influenced by the switchover operation. To enable the execution units to subsequently execute different SW modules, it is necessary to separate the program flow of the execution units. Therefore, depending on the circumstances, the instruction indicators typically have different values in the performance mode, since independent instructions, program segments or programs are, in fact, processed in accordance with the present invention. In the proposal described here, the program flow is separated based on ascertainment of the particular execution unit number. Depending on the ID possessed by an execution unit, the execution unit executes a specific software module. Since each execution unit has an individual number or ID, this may be used to reliably separate the program flow of the participating execution units.
A flow chart in
One possible method for three execution units is illustrated in
According to this description, this method may also be used for multiprocessor systems having more than three execution units.
Several considerations are involved when the switch is made from the performance mode to the comparison mode. When the switch is made from the performance mode to the comparison mode, it must be ensured that the internal states of the execution units are substantially identical following the switchover operation, otherwise a fault could possibly be detected in the comparison mode if the different starting conditions were to lead to different outputs. This may be implemented by hardware, software, firmware or by a combination of all three. The requirement is that all execution units execute the same or similar instructions, programs or program segments once the switch is made to the comparison mode. In addition, a synchronization method is described which may be applied when it is a feature of the comparison mode that identical instructions are processed and that a bit-precise comparison takes place.
In a flow chart,
Step G610: If the two execution units have separate caches, then it is necessary to align the cache contents before the switchover operation to ensure that, in the comparison mode for one address, a cache hit is not obtained for one execution unit, while a cache miss is obtained for another execution unit. If this is not implemented independently by the cache hardware, it is to be effected, for example, by marking all cache lines as invalid. The process must wait until the cache (or caches) are completely invalid. If needed, this is to be ensured by a wait loop in the program code. This may also be achieved by other means; what is decisive is that the caches are in the same state following this step.
The write buffers of the execution units are emptied in step G620, so that, once the switchover operation is performed, no execution unit activities take place that are still attributable to the performance mode.
The state of the pipeline steps of the execution units is synchronized in step G630. For this purpose, one executes, for example, an appropriate number of NOP (no operation) instructions before the switchover sequence/switchover instruction. The number of NOP instructions conforms to the number of pipeline steps, and is thus a function of the particular architecture. Likewise dependent on the architecture is which instruction is suited as an NOP instruction. If the execution units have an instruction cache, then it must be ensured in the process that this instruction sequence be aligned on the boundaries of a cache line. Since the instruction cache has been marked invalid prior to execution of these NOPs, these NOPs must first be loaded into the cache. If this instruction sequence begins at a cache line boundary, then the data transfer from the memory (e.g., RAM/ROM/flash) to the cache is terminated before the switchover instruction is carried out. This must also be included in the consideration when determining the required number of NOPs.
The instruction step for switching to the comparison mode is actually carried out in step G640.
In step G650, the contents of the particular register files is aligned with each execution unit. To this end, the registers need to be loaded with identical contents before or after the switchover operation. In this connection, following the switchover operation, it is important that the contents of a register in the execution units be identical before the register contents is transferred to external locations and consequently compared by the comparison unit.
In step G660, the interrupt controllers are reprogrammed, so that an external interrupt signal triggers the same interrupt in all of the interconnected execution units.
The interrupts are released again in step G670.
If it is not clear from the program sequence when the switch to the comparison mode is to be made, then it is necessary that the participating execution units be informed about the planned switchover operation. To this end, an interrupt is preferably initiated in the interrupt controllers associated with the particular execution units, e.g. an interrupt is initiated per SW. The interrupt handling then prompts execution of the above-described interconnection sequence.
It is then ensured by hardware that state G700 is always assumed after a reset or power on. This is ensured, for example, in that the reset signal or the “power on” signal is transmitted to the reset input or to the set input of the flip-flop or of the register.
In state G700, the system operates in a performance mode. Thus, execution units G10a, G10b process different instructions, programs or basic blocks. A switchover request may be recognized, for instance, by execution of a special switchover instruction by an execution unit G10a, G10b. It may also be recognized by the access to a special memory address, by an internal signal or even by an external signal. Multiprocessor system G60, and thus also switchover and comparison unit G70 remain in state G700 for as long as no switchover request is present. In the subsequent operation, the switchover request signifies recognition of a switchover condition that is characterized by a switchover request in this special system.
A continuation in state G700 is represented by transition G810. In response to detection of a switchover request by execution unit G10a, switchover and comparison unit G70 goes over to state G710 via transition G820. Thus, state G710 connotes that execution unit G10a has detected a switchover request and is waiting until execution unit G10b has likewise detected a switchover request. For as long as long as this does not occur, switchover and comparison unit G70 remains in state G710, which is represented by transition G830.
Transition G840 takes place when, in state G710, execution unit G10b likewise recognizes a switchover request. Switchover and comparison unit G70 consequently assumes state G730. This state connotes that both execution units G10a, G10b have recognized a switchover request. The synchronization process, which is used to mutually synchronize the two execution units G10a, G10b to enable them to subsequently operate in the comparison mode, takes place in state G730. During this process, switchover and comparison unit G70 remains in state G730, as is represented by transition G890.
If a switchover request is first recognized by execution unit G10b in state G700, then the switch is made via transition G860 to state G720. Thus, state G720 connotes that execution unit G10b has detected a switchover request and is waiting until execution unit G10a has likewise detected a switchover request. For as long as long as this does not occur, switchover and comparison unit G70 remains in state G720, which is represented by transition G870. Transition G880 takes place when, in state G720, execution unit G10a likewise recognizes a switchover request. Thus, the switchover and comparison unit assumes state G730.
If both execution units G10a, G10b simultaneously recognize a switchover request in state G700, then the transition to state G730 is made immediately. This case is represented by transition G850.
When switchover and comparison unit G70 is in state G730, both execution units G10a, G10b have recognized a switchover request. In this state, the internal states of execution units G10a, G10b are synchronized to enable operation in the comparison mode, once these synchronization processes are complete. Transition G900 takes place once these synchronization tasks are complete. This transition indicates the end of the synchronization process. In state G740, execution units G10a, G10b operate in the comparison mode. The completion of the synchronization operations may be signaled by execution units G10a, G10b themselves. This means that transition G900 takes place when both execution units G10a, G10b have signaled that they are ready to operate in the comparison mode. The completion may also be signaled by a preset, fixed time. This means that the length of time the system is to remain in state G730 is permanently encoded in switchover and comparison unit G70. This time is set in a way that ensures that both execution units G10a, G10b have definitely completed their synchronization tasks. Once this time has elapsed, transition G900 is then initiated. In another variant, switchover and comparison unit G70 may monitor the states of execution units G10a, G10b and detect, on its own, when both execution units G10a, G10b have completed their synchronization operations. Once the detection has been made, transition G900 is then initiated.
For as long as no switchover request is detected, multiprocessor system G60 remains in the comparison mode, as represented by transition G910. When a switchover request is recognized in state G740, the switchover and comparison unit is placed in state G700 via transition G920. As previously described, in state G700, the system operates in the performance mode. The program flows may then branch off during the transition from state G740 to state G700, as in the method described.
Each execution unit G410a, G410b advantageously possesses its own interrupt controller G420a, G420b, in order to be able to handle two interrupts simultaneously in the performance mode. This is especially beneficial in systems in which the interrupt handling constitutes a bottleneck in the system performance. In this context, interrupt sources G440a through G440n are advantageously directly connected to both interrupt controllers G420a, G420b, respectively. The effect of this type of connection is that, without applying any additional measures, the same interrupt is triggered on both execution units G410a, G410b. In the performance mode, interrupt controllers G420a, G420b are programmed to permit interrupt sources G440a through G440n in question to be suitably distributed over the different execution units G410a, G410b, as a function of the particular application. This is accomplished by suitably programming of interrupt masking registers G430a, G430b. For each interrupt source G440a through G440n, the masking registers provide one bit in the register. If this bit has been set, the interrupt is blocked; i.e., it is not routed to the connected execution unit G410a, G410b. A given interrupt source G440a through G440n is advantageously processed by exactly one execution unit G410a or G410b in one performance mode. This advantageously applies to at least some of the interrupt sources. This enables a plurality of interrupt sources G440a through G440n to be processed simultaneously without the occurrence of any interrupt nesting (an interrupt processing is interrupted by a second interrupt) or interrupt pending (the processing of the second is delayed until the processing of the first is complete).
In the comparison mode, it must be ensured that interrupt controllers G420a, G420b trigger the same interrupt simultaneously on all execution units G410a, G410b; otherwise a fault would be detected in accordance with a comparison mode. This means that, in the synchronization phase, when the switch is made from the performance mode to the comparison mode, it must be ensured that interrupt masking registers G430a, G430b are identical. This synchronization is described in
In this context, register records G1040a, G1040b are used in the performance mode. In this case, the operation of interrupt controller G1030 is precisely the same as that of the two interrupt controllers G420a, G420b. These performance characteristics are illustrated and described in
Using this basic system as a point of departure, a multiplicity of broadened specific embodiments is conceivable. To begin with, component M500 may be designed as a so-called TSC component (totally self checking). In this case, error signal M530 is routed to the outside via at least two lines (“dual rail”). Also, internal design and fault detection measures ensure that, in every possible case involving fault of the comparison component, this signal is present in a correct or identifiably incorrect form. In the process, a binary signal is provided by a dual rail signal via two lines, preferably in such a way that the two lines are mutually inverted in the error-free case. With regard to utilization of the system according to the present invention, one preferred variant provides for such a TSC comparator to be employed.
A second class of specific embodiments is distinguished by the degree of synchronism required of the two inputs M510, M511 (or M610, M611). One possible specific embodiment is characterized by clocked synchronism, that is, the data comparison process may be carried out in a clock pulse cycle.
A slight modification is necessitated by a fixed phase shift between the inputs, in that a synchronous delay element is used which delays the signals in question, for example, by half-integer or integer clock-pulse periods. Such a phase shift is useful in order to avoid common cause faults, that is, those fault causes capable of influencing a plurality of processing units simultaneously and in a substantially similar manner.
For that reason,
Alternatively or additionally, intermediate buffers M650, M651 may be placed in the input chain, in order to be able to likewise tolerate such asynchronisms, which are not manifested as a pure clock-pulse shift or phase shift. These intermediate buffers are preferably designed as FIFO memories (first-in, first-out). Such a memory has an input and an output and is able to store a plurality of memory words. An incoming memory word is shifted in its position in response to the arrival of a new memory word. Following the last position (the depth of the buffer), it is shifted “out of the memory.” If such a buffer is present, asynchronisms up to the maximum depth of the buffer may also be tolerated. In such a case, an error signal must also be output when the buffer overflows.
Moreover, in the comparator, one may distinguish among specific embodiments by the manner in which signal M520 (or M620) is generated. One preferred specific embodiment provides for applying input signals M510, M511 (or M610, M611) to the output and to make the connection interruptable by switches. This specific embodiment has the special advantage that the same switches may be used for switching between the performance mode and different possible comparison modes. Alternatively, the signals may also be generated from intermediate buffers internal to the comparator.
One last class of specific embodiments may be distinguished by how many inputs are present at the comparator and by how the comparator is to react. In the case of three inputs, a majority voting, a comparison of all three, or a comparison of only two signals may be undertaken. In the case of four or more inputs, correspondingly more specific embodiments are conceivable. A detailed description of the possible specific embodiments is included in the description of
The exact selection of the specific embodiments is preferably to be coupled to the various operating modes of the overall system. This means that when there are a plurality of different performance or comparison modes, then these are preferably coupled to the corresponding mode of the comparator.
There are instances along the line of the present invention where it is necessary or beneficial to deactivate or render passive a comparator or a more general voting/processing/sorting element (for the sake of simplicity, always denoted in the following as comparator). There are many ways to effect this. First of all, a signal may be transmitted to the comparator, to activate or deactivate the same. To this end, an additional logic capable of effecting this is to be introduced into the comparator. Another option provides for not supplying any data for comparison to the comparator. A third option provides for ignoring the error signal of the comparator at the system level. In addition, the error signal itself may also be interrupted. Common to all of the options is that, in the system, it is irrelevant that two or more data to be potentially compared, are different. If this is the case, the comparator is considered to be passive or deactivated.
The following considers an implementation of a change-over switch in conjunction with a comparator, thus a switchover and comparison unit G70. This implementation is particularly beneficial in the case that it is designed, together with execution units G10a, G10b, inside of a chip.
Combining the comparator and change-over switch components produces only very minimal hardware overhead in an implementation within a chip. Therefore, one preferred variant of the implementation provides for combining these two parts in one component. This is a component having at least the input signals (output execution unit 1, output execution unit 2), at least the output signals (output 1, output 2), a logical output signal “total output” (may be physically equivalent to output 1 or output 2) and a comparator. The component has the capability of switching the mode, of allowing passage of all signals in the performance mode, and of comparing a plurality of signals in a comparison mode and, if indicated, to allow passage of one. In addition, other input and output signals are advantageous: An error signal for signaling a detected fault, a mode signal for signaling the mode in which the particular component is at the moment, and control signals from and to the component.
In one preferred exemplary embodiment, the two or more execution units are connected in the performance mode as a master to a bus internal to the processor. The comparison unit is deactivated, or the error signal, which is generated in response to different performance characteristics of the execution units, is masked in one of the conceivable comparison modes. This means that the switchover and comparison unit is transparent to the software. In the comparison mode under consideration, the physical execution units to be compared are treated as one logical execution unit at the bus, that is, only one master appears at the bus. The error signal of the comparator is activated. To that end, the switchover and comparison unit separates all but one execution unit from the processor-internal bus via switches, duplicates the inputs of the one logical execution unit, and makes these available to all of the execution units that are participating in the comparison mode. During the process of writing to the bus, the outputs are compared in the comparison unit and, if there is parity, these data are written to the bus via the one available access.
A variant of the switchover and comparison unit is shown in
In the described drawings, the mode signals or the error signals may be readily routed to the outside. In addition, additional signals may be readily transmitted to the component, in particular to generate the internal mode state.
In summary, a preferred implementation of this component is thus characterized by the provision of a plurality of processing units which are able to write output signals to the bus (e.g. address/data bus). What is important is that the component be able to process at least two of the output signals of the execution units (e.g., by comparing, but possibly also voting or sorting the same), and that the component be able to influence at least one switch which is used to interrupt at least one of the direct bus accesses. This is particularly useful when the execution units are processor cores. It is also advantageous when the state of the influenceable switches characterizes the operating mode of the processing unit.
The system properties, in particular the possible comparison modes, are implemented especially effectively when the component is able to apply a signal to the address data bus. This advantageously constitutes a through connection of one of the output signals from one of the execution units. Alternatively, this may result from the processing of different output signals from the various execution units.
As was already made apparent in the descriptions relating to
The performance characteristics according to the present invention may typically be explained with reference to
This mode signal is preferably protected. An implementation in the base-two system based on the implementation shown in
The mode signal may be employed outside of the component. It may first be used for self-monitoring of the operating system. From an SW point of view, this is responsible for a switchover operation, and should always know the mode the system is currently in, and also bring the system into this mode. This signal may be checked for protection purposes. This may initially be accomplished directly. Alternatively, however, timers or other “independent” units may be used to validate a query of the operating system by this signal.
Typically, this signal may optionally be used in other data sinks of a μC (or more general processing unit) as well. For example, an MPU (memory protection unit) may be programmed to permit specific memory accesses (from specific execution units) only in specific modes. In this context, an MPU is a unit which is able to ensure that only admissible accesses are made to the data/address bus, for instance, by preventing access to certain memory address spaces for certain program parts. By bringing the mode signal to the MPU, by suitably configuring and programming this MPU, and by evaluating these configuration data and the mode signal, an additional protection is able to be provided. Under certain circumstances, this even simplifies the programming, in the case that the mode signal already constitutes sufficient information for checking. A quasi-static programming at the initialization time of the μC then suffices. This may apply correspondingly to peripheral units. Here as well, there are applications in which access to a corresponding peripheral element is only permitted in certain modes. By bringing the mode signal to the peripheral element, properly configuring and programming the peripheral element, and by evaluating these configuration data and the mode signal, an additional protection may be provided. Under certain circumstances, this even simplifies the programming, in the case that the mode signal already constitutes sufficient information for checking. A quasi-static programming at the initialization time of the μC then suffices. Analogously, the evaluation of this signal may also be used at the interrupt controller. Such monitoring may then form the basis or make up an essential component of the security concept. Through proper execution and SW structuring, it may be possible to devise the security concept for an entire fault class in the application under consideration for this mode signal. This is especially advantageous when the mode signal is self-protecting in a suitable form, as described above. In such a case, a further advantage is derived when the component under consideration is capable of transmitting an error signal or of activating a disabling path, if it detects a discrepancy between the mode signal and the access to itself.
Another important intended application pertains to analysis of the mode signal outside of the processing unit. A direct application is the analysis in a decrementing watchdog. Such a “watchdog” is constituted of at least one (counter) register, which may be set to an integer value by the microprocessor. Once this register is set, the watchdog independently decrements the value of the register by a fixed period. If the value of the register is zero, or if an overflow occurs, the watchdog generates an error signal. If it is not intended for the error signal to be generated, then the microprocessor must reset the value of the register in a timely manner. This allows a check to be made (within limits) as to whether the microprocessor is correctly executing the software. If the microprocessor is no longer executing the software correctly, it is assumed in this case that the watchdog is also no longer being operated correctly, and an error signal is thus generated by the watchdog. The integrity of the hardware and the data structures may be reliably checked in a comparison mode. To this end, it must be ensured, however, that the microprocessor is regularly switching back to this mode. Therefore, the task of the watchdog described here is not only to generate an error signal when it is no longer reset within a defined time period, but also when the microprocessor no longer switches back to the defined comparison mode within a defined time period. For example, the watchdog may only be reset when the mode signal indicates the specified comparison mode of the processing unit. This ensures that the processing unit is regularly switching back to this mode. Alternatively or additionally, the value in the register of the watchdog is only decremented when specific interrupts are triggered in the microprocessor. To this end, the external interrupt signals of the μC must be coupled to the watchdog as well. The information on those interrupts which switch the μC to the specified comparison mode is stored in the watchdog. The watchdog is “wound up” as soon as such an interrupt arrives; it is reset by the presence of the correct mode signal.
It is generally useful, particularly in an application for a security concept, to evaluate the mode signal in a μC-external source. An important point to consider in protecting the correct operational sequence of the software on a computer, as described in the present invention, is making the correct changes among the various permitted modes. It is first necessary to check the capacity to change itself, preferably the correct changing process as well. As described above, it is also of interest that a special mode is regularly assumed. Such a method is always particularly advantageous when the mode signal itself is conceived as a self-protecting signal.
One option provides for directing the mode signal to an ASIC or another μC. Using timers and simple logic, this is able to check at least the following points, employing this signal:
Does the processing unit come often enough (at the latest, for example, every 1000 μs) into one or a plurality of defined modes?
Is one specific signal always emitted in response to a change into a mode?
Does the processing unit regularly leave a mode?
Are certain simple patterns of the sequence of the modes valid?
Is a general time pattern valid (for example, on average <70% in mode 1 and <50% in mode 2)?
Any combination of logic, time properties of the mode signal, optionally supplemented by the use of additional signals.
In this context,
Another application of this idea is the evaluation of the mode signal in an actuator control. In many applications in the automotive sector, there is currently a trend to use so-called intelligent actuators. These actuators require a minimal amount of electronics which suffices for receiving an actuator control command, and then for driving the actuator in such a way that this control command is then also executed.
The fundamental idea is illustrated in
| Number | Date | Country | Kind |
|---|---|---|---|
| 102004051937.4 | Oct 2004 | DE | national |
| 102004051950.1 | Oct 2004 | DE | national |
| 102004051952.8 | Oct 2004 | DE | national |
| 102004051964.1 | Oct 2004 | DE | national |
| 102004051992.7 | Oct 2004 | DE | national |
| 102005037222.8 | Aug 2005 | DE | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP2005/055504 | 10/25/2005 | WO | 00 | 2/28/2008 |
