Patent Grant
8384631
The invention relates to an active matrix display panel, comprising a substrate, an array of pixel circuits being arranged in a matrix of at least one column and a plurality of rows on the substrate, each pixel circuit comprising a light-emitting element, capable of emitting light of an intensity determined by the value of a current passed through it, and at least one column line, each column line arranged to conduct a reference current, provided by a current driving circuit, when connected to the panel, wherein the pixel circuits in a column are divided into a plurality of groups of at least one pixel circuit, wherein the active matrix display panel comprises at least one current mirror circuit associated with a first group, comprising a first current mirror, arranged to mirror a reference current flowing through a column line to a first current mirror output, wherein each pixel circuit in the first group comprises at least a first current-memory stage, having an output terminal connected to the light-emitting element, wherein the first current-memory stage is capable of drawing a current determined at least partly by the current mirrored to the first current mirror output through the output terminal.
The invention further relates to a method of driving such an active matrix display panel, comprising receiving information specifying intensity values of a plurality of light-emitting elements to be displayed within a frame period, and setting a reference current flowing through a column line connectable to the first current mirror to a first level, within the frame period.
The invention also relates to a display device, comprising such an active matrix display panel.
The invention also relates to a device for driving such an active matrix display panel.
An example of an active matrix display panel as defined above is known, e.g., from U.S. Pat. No. 5,903,246. In the known panel, a circuit is coupled to a current source for driving a plurality of active organic light emitting diodes (OLEDs) arranged in a column at a desired brightness. The circuit comprises an input leg of a current mirror for establishing a reference current for driving an active OLED, a plurality of selecting means, responsive to a row select signal, for respectively selecting an OLED from the plurality of active OLEDs; an output leg of a current mirror for supplying a mirror of the established reference current to the selected OLED; and a plurality of charging means for supplying a mirror of the established reference current in order to continuously drive the selected O-LED. The known technique includes separate, digitally adjustable current sources on each column line of the array. For each column, the digitally-programmed current flow terminates with a reference OLED and a series transistor forming the input leg of a distributed current mirror. A reference current is used to establish a proper current by way of distributed current mirror circuitry driving any one of the active O-LED pixels in a column. In particular, a column select conductor, which is coupled to a digitally-programmable current source, supplies current to a transistor and to a reference pixel, both coupled to the last pixel in the column.
In the known circuit, as the panel is scaled up, parasitic capacitance, which increases with the length of the column select conductor, provides a limit to the speed at which the digital current source can vary the new current level for each consecutively selected pixel in the column. In particular, large current swings cannot be accurately imposed within the time available for addressing a row. In addition, it becomes more difficult to match the transistors in the distributed current mirror as they lie further apart, so further decreasing the accuracy with which the current level determining the intensity of light emitted by the light-emitting element can be set within the time available for addressing a row.
It is an object of the invention to provide an active matrix display panel, method of and device for driving such a display panel and display device that allow the current drawn through the light emitting element in a pixel circuit to be set within the time available for each pixel with more accuracy at larger intensity level variations between TOWS.
This object is achieved by the active matrix display panel according to the invention, which is characterised in that each current mirror circuit comprises at least one additional current mirror, arranged to mirror a reference current flowing through an associated column line to an additional current mirror output, wherein each additional current mirror output is connected in parallel to the first current mirror output.
Because the first and additional current mirrors are comprised in the current-mirror circuit, the accuracy with which the reference current or currents are mirrored is improved, as current mirror components, such as transistors, situated closely together are more likely to be matched. Because two or more current mirrors are used and their outputs are connected in parallel, the mirrored currents are added. Thus larger variations in intensity from one row to the next can be achieved, without large swings in reference current value on the column line. The influence of parasitic capacitance is therefore smaller, the correct reference current value is arrived at more quickly, and the accuracy with which each pixel in the column can be driven is improved. Because a reference current value is provided through the column line(s) and an intensity of the emitted light is determined by the sum of mirrored currents, voltage drops across the column line from one row to the next do not have to be taken into account when setting reference values on the column line, thus taking away the need to account for such voltage drops in the driving algorithms in order to maintain accuracy.
Preferably, the active matrix display panel comprises a row selection line for each row of pixel circuits, wherein at least the first current-memory stage comprises a row select switch, responsive to a signal on the row selection line, and a storage element for storing a signal value determining a current flowing through the output terminal, wherein the row select switch is comprised in a circuit section for providing a row select signal to the storage element.
Thus, it is possible to program different reference current values in the first current-memory stage and vary the reference current from one row to the next. The pixel circuit of each row can be individually addressed by providing a row select signal and setting the current through the column line to the appropriate level.
A first variant of the active matrix display panel comprises at least N column lines for each column of pixel circuits, N being larger than one, wherein the current mirror circuit comprises at least N current mirrors, each arranged to mirror a reference current flowing through an associated one of the column lines to a current mirror output of the current mirror, and an adder for adding currents flowing through the current mirror outputs.
Thus, it is possible to set the reference currents intended for each current mirror separately and simultaneously. This has the advantage that the voltage and current on each of the column lines settle simultaneously. The reference currents to be mirrored and supplied to the adder, each defining a contribution to the current determining the intensity of emitted light are set at approximately the same time. The fraction of the frame period during which each of the contributions is available for addition and supply to the one or more current-memory stages in the pixel circuits is thus relatively large. In a preferred embodiment of this variant, the current mirror circuit comprises at least one feed select switch, interrupting a connection between a current mirror output of an associated current mirror and a column line and responsive to one of at least one feed select signals, wherein the active matrix display panel comprises addressing circuitry, connectable to a display driver for receiving driving information, and arranged to supply each feed select signal to the feed select switches associated to one of the current mirrors.
Thus, it is possible to drive the active matrix display panel in a digital fashion, by selecting current contributions to be added by the adder by means of the feed select signals. One can thus set the N reference current values to a constant value for the duration of a frame period, and drive the pixel in each row in turn by supplying an appropriate combination of feed select signals in accordance with the intensity of light to be emitted by the pixel. This further reduces the variation of reference current values on each column line, thus allowing more time for accurate driving of the pixels.
Preferably, the addressing circuitry comprises at least one addressing line and at least one decoder, connected to the addressing lines by means of separate inputs, and to each of the current mirror switches associated with each current mirror by means of a separate output for each current mirror, the decoder being arranged to convert a digital value communicated over the addressing lines into a combination of feed select signals encoded by the digital value.
This reduces the number of lines on the active matrix display panel substrate needed to provide the N feed select signals to the N current mirror switches from N to a lower value. Each digital value represents a combination of feed select signals. The decoder is arranged to generate the appropriate combination on the basis of the digital value provided on its inputs.
In one embodiment of the invention, the first group comprises M pixel circuits, M being larger than one, wherein the active matrix display panel comprises a local column line for the first group, connecting an output of the adder in the current mirror circuit to an input of a current mirror in each of the M pixel circuits comprising the first current-memory stage.
Thus, the current mirror circuit with the adder for adding the contributions defined by the reference currents is shared by the M pixel circuits. This represents a significant saving in the amount of circuitry on the substrate, as it is not necessary to provide each of the M pixel circuits with N current mirror circuits. One current mirror circuit per pixel circuit, to mirror the current on the local column line, suffices. It is noted that the column of pixel circuits comprises a plurality of groups, so that the local column line provides a reference current to only a sub-set of the pixel circuits in the column. The local column line is therefore shorter than a column line connectable to each of the pixel circuits would be, so that parasitic capacitance on the local column line is less of a problem. Because the local column line will be connected to adjacent pixel circuits in the column, variations in reference current value are not very likely for a display panel displaying normal images. It is further noted that the presence of a row selection line for each row of pixel circuits prevents the reference current value on the local column line from being provided to the current-memory stage of each pixel circuit in the group at the same time, so that the pixels in the group can still be driven separately.
Preferably, the active matrix display panel comprises at least N current dumping circuit stages, each connectable to one of the N column lines by means of a switch, and responsive to one of the N feed select signals supplied to the feed select switches controlling an associated current mirror, such that a connection between a column line and a current dumping circuit stage is established when the connection between the column line and each of the current mirror outputs is interrupted.
By these means, it is ensured that the impedance into each column line remains substantially constant, irrespective of whether the current provided through the column line is drawn by a current mirror or not. Thus, when a current mirror switch is switched on so that the reference current is mirrored by the associated current mirror, the current dumping circuit stage is disconnected and vice versa. This helps to suppress variations in voltage and current through the column line, making shorter settling times possible.
In a further variant of the active matrix display panel, which can be combined with any of the embodiments of the previously described variant, each pixel circuit in the first group comprises K current mirrors, K being larger than one, each having an input and a current-memory stage comprising an output connected to the light-emitting element, a storage element for storing a signal value determining a current flowing through the output and a sub-frame select switch, responsive to one of K sub-frame select signals, wherein each sub-frame select switch is comprised in a circuit section between the input of the current mirror and the storage element, wherein the active matrix display panel comprises addressing circuitry, having at least one input terminal for receiving driving information from a display driver connected to the active matrix display panel, and arranged to supply each sub-frame select signal to an associated one of the K sub-frame select switches.
This variant allows a method of driving the active matrix display panel in which current contributions are added, as in the previously described variant, because each of the K current-memory stages has an output connected to the light-emitting element. However, because each current-memory stage comprises the storage element, and because each current-memory stage is separately programmable, by supplying a sub-frame select signal to only the current-memory stage being programmed, it is possible to sequentially program the various current contributions. It is thus possible to supply a first reference current determining a first contribution during a first sub-frame period, and a second reference current determining a second contribution during a second sub-frame period. The first contribution is maintained, thanks to the storage element, and added to the second contribution, because both current-memory stages comprise an output connected to the light-emitting element. Because contributions can be added, it becomes possible to supply smaller reference currents, thus avoiding the above-described problems caused by the parasitic capacitance of the column line(s).
One embodiment of this variant comprises at least one reset line, and at least one current-memory stage comprises a reset switch, responsive to a reset signal on the reset line to adjust the signal value stored by the storage element to a default value.
Thus, after programming a contribution increasing the current flowing through the light-emitting element, it is also possible to take away a contribution to the total current, thus decreasing the total current flowing through the light-emitting element. This is useful, as it allows each of the current contributions to be present for a different sub-period of the frame time. Because the observed light intensity depends also on the length of time during which light is emitted, as well as on the current flowing through the light-emitting element (the eye of an observer functions as an integrator), the number of different intensity levels is effectively increased. Because the active matrix display panel comprises a reset line in addition to column lines, and the reset line controls a switch, resetting is effectively done by means of a digital signal. This is much faster than setting a reference current value on a column line to the default value.
According to another aspect of the invention, the method of driving an active matrix display panel according to the invention is characterised by, within the frame period, setting a reference current flowing through a column line connectable to an additional current mirror comprised in the current mirror circuit and arranged to mirror a reference current flowing through the column line to an additional current mirror output connected in parallel to the first current mirror output, to a second level.
The first and second level may be the same. The method has the advantage that the current determining the light-intensity is determined by the sum of the two levels, so that each level can be relatively low. Therefore, large swings in current and voltage on the column line(s), which occur when one pixel is to emit light at a high intensity and a next pixel at a very low intensity, are prevented. Thus, the negative effects of the column capacitance are prevented. The method thus allows larger differences in intensity, or longer column lines, i.e., more pixel circuits in a column, since the time needed to allow each reference current to settle to the intended level is shorter.
In one variant of the method, wherein the active matrix display panel comprises at least N column lines for each row of pixels, N being larger than one, wherein the current mirror circuit comprises N current mirrors, each connectable to an associated one of the N column lines and arranged to mirror a reference current flowing through an associated one of the N column lines to a current mirror output of the current mirror, wherein the current mirror circuit comprises an adder for adding currents flowing through the N current mirror outputs, a reference current is set on each of the column lines.
Thus, the reference currents intended for each current mirror are set separately and simultaneously. This has the advantage that the voltage and current on each of the column lines settle simultaneously. The reference currents to be mirrored and supplied to the adder, each defining a contribution to the current determining the intensity of emitted light, are set at approximately the same time. The fraction of the frame period during which each of the contributions is available for addition and supply to the one or more current-memory stages in the pixel circuits is thus relatively large.
Preferably, the method comprises selectively connecting the N current mirrors to the associated N column lines in accordance with the received information.
Thus, because the N current mirrors are selectively connected, it is possible to select the particular contributions to the total current that flows through the light-emitting element. It is thus possible to set different total currents for each pixel whilst varying the reference currents flowing through the column lines only slightly or not at all. This means that less time is needed to allow reference currents to settle, so more of the frame time is available for actually driving the pixels circuits.
In another variant of the method of the invention, which may be combined with the embodiments described above, wherein the active matrix display panel comprises a row selection line for each row of pixel circuits, wherein at least the first current-memory stage comprises a row select switch, responsive to a signal on the row selection line, and a storage element for storing a signal value determining a current flowing through the output terminal, wherein the row select switch is comprised in a circuit section for providing a signal to the storage element, the frame period comprises a plurality of sub-frame periods and the method comprises providing a row select signal closing the row select switch on each row selection line in turn within each sub-frame period.
Thus, each pixel circuit is addressed at least twice every frame period, which allows a greater number of different intensity levels.
A preferred embodiment, wherein each pixel circuit comprises K current mirrors, each comprising a current-memory stage, K being larger than one, each current-memory stage having an output connected to the light-emitting element and a storage element for storing a signal value determining a current flowing through an output, comprises selectively providing a signal value for storage in the storage element to a different one of the K current-memory stages substantially simultaneously with the row select signal.
Thus, it is possible to make use of the fact that the perceived intensity also depends on the length of time during which light is emitted. By being able to set the current through the light-emitting element to a certain value for the duration of only part of the frame period the number of different perceived intensities that can be displayed is effectively increased.
Another embodiment of the method according to the invention comprises providing a reset signal to at least one of the current-memory stages, to adjust the signal value stored by the storage element to a default value, within the frame period.
Thus, after programming a contribution increasing the current flowing through the light-emitting element, a contribution to the total current is taken away again, within the frame period, thus decreasing the total current flowing through the light-emitting element. This is useful, as it allows each of the current contributions to be present for a different sub-period of the frame time. Because the observed light intensity depends also on the length of time during which light is emitted, as well as on the current flowing through the light-emitting element (the eye of an observer functions as an integrator), the number of different intensity levels is effectively increased.
Preferably, the method comprises providing at least one further reset signal to at least a further one of the K current-memory stages, to adjust the signal value stored by the storage element of the further current-memory stage to a default value, within the frame period.
Thus, the intensity of light emitted by a pixel during a frame period is increased in steps and at least two of the contributions to the total current determining that intensities are subtracted again from the total before the end of the frame period.
In a preferred embodiment, the method comprises providing each reset signal at a separate point in time, and in an even more preferred embodiment, in each sub-frame period, a signal value for storage in the storage element is selectively provided to a different one of a number of the K current-memory stages in order, and the reset signals are provided to each of the number of current-memory stages in reverse order.
Thus, a gradual resetting scheme is realised. The scheme has the advantage of eliminating artefacts, which occur especially when the active matrix display is used to display moving images and the current-memory stages are abruptly reset.
According to another aspect of the invention, there is provided a display device, comprising an active matrix display panel according to the invention.
Such a display device, which can be implemented in the shape of a television screen or computer monitor, can be addressed at higher frequencies for a given column size, i.e., number of pixels per column. Of course the invention can also be used to achieve the advantage of having more pixel circuits in a column connected to a single column line for a given frequency. In this case, the effect is to decrease the number of column lines per column of pixel circuits. The amount of driving circuitry is thus reduced, since separate current drivers are needed for each column line.
According to a further aspect of the invention, there is provided a device for driving an active matrix display panel according to the invention, having an input for receiving information specifying intensity values of a plurality of light-emitting elements to be displayed within a frame period, and arranged to carry out a method according to the invention.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
The invention will now be explained in further detail with reference to the accompanying drawings, in which:
In
Each of the embodiments of the invention is used to display a sequence of frames on the active matrix display panel. The description of the invention will focus on how a frame is built up on the active matrix display panel. The driving circuitry that drives the pixel circuits in a group within a column receives a set of data including an intensity value for each pixel circuit in the group at a certain point in time. This is the information encoding a frame as it is understood in the context of this description. The next frame in the sequence, for which the driving circuitry receives another set of data, is to be displayed at a next period in time. The interval in between these periods determines the frame period, i.e., the time available for adjusting the current flowing through the light-emitting element in each pixel circuit in accordance with one received set of data.
The embodiment shown in
Thus, each current mirror 4 determines a contribution to the current determining the intensity of light emitted by the OLED 2. This, in itself, already confers the advantage that the reference current Iref is approximately one fourth of what it would be if the pixel circuits 1 were to comprise only one current mirror 4. Thus, the difference in current Iref between a pixel that is fully on and one that is fully off is much smaller, so that the parasitic capacitance of the column line 3 has a much smaller influence on the accuracy with which a current through the OLED 2 can be set. To allow sequential driving, however, the current-memory stages in the current mirrors 4 further comprise a storage element for storing a signal value determining a current flowing through the output of that current-memory stage, and thus the output of the current mirror 4. For each row of pixel circuits 1a-1d, there is also a row selection line 6a-6d. Each current-memory stage in each of the pixel circuits 1a-1d comprises a row select switch, responsive to a signal on the associated one of the row selection lines 6a-6d. The row select switch is comprised in a circuit section for providing a signal to the storage element. Each of the current mirrors 1a-1d further comprises a sub-frame select switch connected to and responsive to one of K sub-frame select signals sk. The sub-frame select switch is comprised in a circuit section between the input of the current mirror 4 and the storage element. Thus, it is possible to set each of the signal values stored in the K current-memory stages in turn, by closing the sub-frame select switches in turn and providing the appropriate reference current Iref on the column line 3. When the sub-frame select switch is then opened again, the signal value is maintained, and consequently the same current is drawn through the output of the current mirror 4, regardless of subsequent values of Iref.
In the embodiment of
The pixel circuits 2 may be implemented in various ways.
The composition of a current mirror 8 will be explained with reference to the first current mirror 8a. The composition of the second current mirror 8b is substantially the same. The first current mirror 8a comprises a matched input transistor 13 and output transistor 14. Because the input transistor 13 and output transistor 14 are both located in the pixel circuit, matching is relatively easy to achieve, since they are close together on the substrate. It is noted that variants of all embodiments of the invention are possible in which there is a well-defined matching ratio between input transistor 13 and output transistor 14, and in which the matching ratio varies in a defined manner between the current mirrors 8a, 8b in the pixel circuit. In this variant, one reference current value can be provided through the column line 9, but the current drawn through the node 11 varies according to the current mirror 8 that is selected to mirror the reference current Iref Thus, the current drawn through the OLED 12 is a sum of weighted contributions, selected in accordance with the driving information.
The first current mirror 8a comprises a current-memory stage, formed by the output transistor 14 and a storage capacitor 15. A row select switch 16 and a first sub-frame select switch 17 are connected between the input transistor 13 and the storage capacitor 15. Another type of analogue storage device or circuit may be used in the place of the storage capacitor 15, but the shown embodiment has the advantage of simplicity. A second sub-frame select switch 18 is connected between the input of the first current mirror 8a and the input transistor 13. The row select switch 16 is responsive to a signal on a row selection line 19, whereas the first and second sub-frame select switches 17, 18 are responsive to the sub-frame select signal on a first data bit select line 10a. When both the row select switch 16 and the first and second sub-frame select switches 17, 18 are closed, the reference current Iref flowing through the column line 9 is mirrored to the output of the first current mirror 8a. Simultaneously, the storage capacitor 15 is charged to the voltage differential between gate and source of the output transistor 14. When any one of the switches 16-18 is opened, the voltage differential is maintained by the storage capacitor 15, which thus determines the current drawn by the first current mirror 8a when it is not being addressed. The OLED 12 is connected to a common power supply 20, which is the same for each pixel circuit. The person skilled in the art will realise that the pixel circuit shown in
As mentioned, the display driver will usually be external to the substrate, or at least located at the edge of the surface area on which the pixel circuits are arranged. Therefore, the data bit select lines 7 (
In the embodiment of
It is noted that two or more pixel circuits 23 may share a decoder 22, in order to reduce the number of decoders 22, and thus the complexity of the active matrix display panel. There is no danger of pixel circuits 23 in the same column being simultaneously programmed by means of a reference current Iref, as each current mirror 24 comprises a row select switch and is connected to a separate one of four row selection lines 26a-26d.
The active matrix display panel of
In the shown embodiment, there are four column lines 30a-30d, through which four reference currents Iref1-Iref4 with the same or a different value can be provided by a display driver. The pixel circuits 29 are identical to those of the embodiment shown in
Note that, as was the case for the embodiments of
In view of the similarity between sub-frame select signals and feed select signals, it will come as no surprise to those skilled in the art that the decoders 22 of
In use, reference currents Iref1-Iref4 flow through column lines 39a-39d. Within a frame period a row select signal is provided to a pixel circuit 36 through one of four row selection lines 40a-40d. Simultaneously, a binary code is serially provided through the clock line 38 to the decoders 37. By means of the shift register, the binary code can be converted into a combination of feed select signals, which are provided to current mirrors 41a-41p in the pixel circuits 36. If the pixel circuit 36 is addressed via a row selection line 40, then the reference currents Iref1-Iref4 are selectively mirrored by the current mirrors 41a-41p, in accordance with the feed select signals provided by the decoder 37. After the pixel circuit 36 is deselected, the mirrored currents are maintained. As the outputs of the current mirrors 41 in a pixel circuit 36 are connected in parallel at a node 42 in the pixel circuit 36, the sum of the mirrored or maintained currents is drawn through an OLED 43 in the pixel circuit 36.
It will be recalled that in all of the described embodiments, the current mirrors in the current mirror circuit are selectively connected to the associated column line (purely sequential) or column lines (parallel), in accordance with the driving information supplied by the current driving circuit. Thus, whenever a pixel circuit in a certain row is selected by means of a signal on the associated row selection line, a reference current flowing through a column line is either mirrored to an adder or not. This depends on the driving information, which translates into a number of binary feed select signals (parallel) or sub-frame select signals (purely sequentially driven display panel). If no measures were to be taken, then the current driver supplying the reference current would see a different input impedance when the reference current is mirrored from when it is not. In order to keep the input impedance substantially constant, the various embodiments of the invention comprise a number of current dumping circuit stages corresponding at least to the number of column lines, and each connectable to an associated one of the column lines by means of a switch responsive to one of the feed select signals supplied to the current mirror switches controlling an associated current mirror, such that a connection between a column line and a current dumping circuit stage is established when the connection between the column line and each of the current mirror outputs is interrupted.
In use, whenever the pixel circuit is addressed by means of a signal on a row selection line 69 associated with the pixel circuit, the first and second row select switches 61, 62 close. Thus, a connection between the input transistor 59 and the first column line 65a is established. If a feed select signal is also supplied by means of the first bit select line 66a, then the feed select switch 63 is closed, and the reference current is mirrored. Otherwise, the reference current is not mirrored, but the input transistor 59 is still connected to the first column line 65a, so that the input impedance as determined by the input transistor 59 is independent of the position of the feed select switch 63. Thus, the input transistor 59 functions as a local current dump.
In the embodiment of
Returning to
Note that the layout of the first and second current mirrors 84a, 84b corresponds substantially to that of the first and second current mirrors 8a, 8b shown in
Returning to
Although the parasitic capacitance of the local column line 99 may affect the speed at which the M pixel circuits 70 may be addressed, it is noted that the local column line 99 can be much shorter, as the current mirror circuit 73 will be situated at a shorter distance to the M pixel circuits 70 than to the edge of the display panel and need only connect the inputs of the current mirrors 83 in each of the pixel circuits 70 to the output of the current mirror circuit 73.
It is further noted that the embodiment can be further refined by providing further local current adders for each group of M pixel circuits and a number of local column lines corresponding to the number of local column lines. Thus, differently valued reference currents can be provided in parallel to the M pixel circuits. Local addressing circuitry and extra feed select switches in the current mirrors of the pixel circuit are used in such an embodiment to selectively mirror the reference currents provided via the local column lines.
The current mirrors 74 in the current mirror circuit 73 may comprise current dumping circuit stages. In that case, they comprise a variant of the first current mirror 58a of
It will be appreciated that the number N of bit select lines 98a-98d, as well as the number K of data bit select lines 100a-100c can be reduced by making use of decoders such as the decoder 22 described in connection with
In
The first current mirror 106a comprises first and second sub-frame select switches 112, 113, responsive to a sub-frame select signal on a first data bit select line 114a. Second and third data bit select lines 114b, 114c convey sub-frame select signals to the second and third current mirrors 106b, 106c respectively. The first current mirror 106a further comprises first and second row select switches 115, 116, responsive to a row select signal on a row selection line 117. Both row select switches 115, 116 are comprised in a circuit section of the first current mirror that supplies a voltage to the storage capacitor 109. Note that the voltage stored in the storage capacitor 109 determines the value of the current drawn through the output of the current-memory stage comprised in the first current mirror 106a.
The current-memory stage comprised in the first current mirror 106a further comprises a reset switch 118, responsive to a reset signal on a reset line 119. When a reset signal is supplied through the reset line 119, the storage capacitor 109 is discharged. Thus, the voltage value is adjusted to the default value of 0 V. The gate to source voltage differential over the output transistor 108 is therefore also set to the default value of 0 V, so that substantially no current will flow through the output of the current-memory stage. Other default reset values are, of course, possible.
When no reset signal is supplied to the reset switch 118, a connection between an input transistor 120 and the second sub-frame select switch 113 and second row select switch 116 is maintained, so that the current-memory stage can be programmed in the usual way, as described above.
The second and third current mirrors 106b, 106c correspond in layout to the first current mirror 106a.
Each of the current mirrors 123a-123d comprises a current-memory stage with an output coinciding substantially with the current mirror output and connected to the OLED 124. Each current-memory stage comprises a storage element for storing a signal value determining a current flowing through the output. Each current-memory stage further comprises a sub-frame select switch, responsive to one of four sub-frame select signals. In
Each current mirror 123 further comprises a reset switch, responsive to a reset signal on the reset line 122, to adjust the signal value stored by the storage element to a default value, e.g., a value determining that substantially no current is to be drawn through the current mirror output. The reset switch is only operative when the current mirror is simultaneously also supplied with a sub-frame select signal.
In
Apart from the decoder 130, the pixel circuit 129 of
Each current mirror 132 further comprises a reset switch, responsive to a reset signal on the reset line 137, to adjust the signal value stored by the storage element to a default value, e.g., a value determining that substantially no current is to be drawn through the current mirror output. The reset switch is only operative when the current mirror 132 is simultaneously also supplied with a sub-frame select signal.
The methods that may be used to drive the various embodiments of the active matrix display panel discussed will now be explained in further detail. In each of the embodiments, for each pixel circuit, a reference current through a column line is set to a first level within a frame period and mirrored by a first current mirror, so that it is drawn through a light-emitting element in that pixel circuit and, within the same frame period a reference current is mirrored by at least one further current mirror connected in parallel to the first current mirror, and the mirrored currents are added. For each embodiment, it may be advantageous to insert a non-emissive period within the frame time to avoid motion time artefacts. In this case the time diagram should be adjusted to incorporate this possibility.
To explain a manner of driving the active matrix display panel according to the invention in a purely sequential fashion, reference will be made to
In the shown embodiment, the frame period is divided into K sub-frame periods Δtk and K current settling periods. In
In the shown embodiment, a different value reference current Iref is set for each sub-frame period Δtk and the values are binary weighted, with the most significant value being provided first, i.e., being selectively mirrored during the first sub-frame period Δti. The second reference current value is half the level of the first, the third half of that, etc. Thus, the current settling periods may be different for proper settling to the intended level.
In the shown embodiment, currents to be drawn through the OLEDs 2a-2d can be programmed by means of a digital value. For example, the value to be supplied to the OLED 2a in the first pixel circuit 1a is programmed as ‘1100’, the value of the current through the second OLED 2b is programmed as ‘0000’, the value of the current through the third OLED 2c is ‘1010’ and that through the fourth OLED 2d is ‘0001’.
Due to the inclusion of a current-memory stage in each of the current mirrors 4, a current mirrored during the first sub-frame period of one frame period is maintained until at least the first sub-frame period of the next frame period, i.e., for the duration of one frame period. Note that this is not necessarily the case when the embodiments of
Suppose that no current flows through the OLED 2a of the first pixel circuit 1a at the start of the shown frame period. If the current level corresponding to the least significant bit is 10 nA, then the current flowing through the OLED 2a at the end of the frame period is: 1. times. 80 nA+1. times. 40 nA+0. times. 20 nA+0. times. 10 nA=120 nA.
In
For example, if the pixel circuit 121 of
At the start of the second sub-frame period Δt2, the process is repeated for the second current mirror 123b in the pixel circuit 121. The current mirrored (and thereafter maintained) by the second current mirror 123a adds to the current drawn by the first current mirror 123b, so that the current through the OLED 124 is now 2I0 No sub-frame select signals are provided at the start of the third and fourth sub-frame periods Δt3, Δt4, because the value to be programmed happens to be ‘1100’.
At the start of the sub-frame reset period Δtr, a sub-frame reset signal is provided over reset line 122, together with a row select signal over row selection line 127 and sub-frame select signals on all four data bit select lines 126a-126d. Thus, the values determining the current drawn by each of the four current mirrors comprising a current memory stage with a reset switch is reset to the default value of zero. No more current is drawn through the OLED 124. Note that, also due to the fact that the sub-frame periods are of varying length, the most significant bit in the value ‘1100’ corresponds to the highest contribution to the overall perceived intensity, as it determines that a current contribution I0 is to be drawn through the OLED 124 for the duration of the entire frame period minus the reset period Δtr.
Using the method of driving an active matrix display panel illustrated in
In this variant of the driving method, a signal value for storage in the storage element is selectively provided to a different one of a number of the current-memory stages in each sub-frame period in order, and wherein the reset signals are provided to each of the number of current-memory stages in reverse order. As is shown in
Assume again that the pixel circuit 121 of
During the first sub-frame period Δt1, a row select signal is provided on row selection line 127. Simultaneously, a sub-frame select signal is provided on the first data bit select line 126a, corresponding to the most significant bit in the digital value to be programmed. This activates the first current-mirror 123a to mirror a reference current equal to Io to its output, and thus to source the current to the OLED 124. A storage element in the first current mirror 123a stores a signal value determining that the current I. is to be maintained when the first current-mirror 123a is no longer selected. Within the first frame period Δt1, a first sub-frame select signal is also selectively provided to the other three pixel circuits. At the start of the second sub-frame period Δt2, a sub-frame select signal is provided on the second data bit select line 126b simultaneously with a row select signal on row selection line 127. This activates the second current mirror 123b, so that the reference current with value Io is also mirrored by the second current mirror 123b. The total current through the OLED 124 is now 2I0. At the start of the third and fourth sub-frame periods Δt3, Δt4, no sub-frame select signal is provided on third and fourth data bit select lines 126c, 126d. After a period of time corresponding to the fourth sub-frame selection period Δt4, a row select signal is provided on row selection line 127, a reset signal is provided on reset line 122 and a sub-frame select signal is provided on the fourth data bit select line 126d, to reset the current-memory stage in the fourth current mirror 123d. Note that this has no effect in this specific example, as no current was being drawn by the fourth current mirror 123d anyway. Variants of the method are possible in which the reset signal is only provided to current mirrors that are drawing a current with a non-default value. However, this would require extra logic and memory in the display driver. At the start of the second reset period Δtr2, a reset signal and row select signal are again provided to the pixel circuit 121. A sub-frame select signal is provided on the third data bit select line 126c. At the start of the third reset period Δtr3, a row select signal is provided on the row selection line 127, a reset signal on the reset line 122 and a sub-frame select signal on the second data bit select line 126b. Thus, the current through the OLED 124 is reduced from 2I0 to I0. In the shown variant, no reset signal is provided to the first current mirror 123a. However, a variant in which this is done is also within the scope of the invention.
Although it has been assumed throughout this description, that the reference current on a column line stays constant for at least the duration of a sub-frame period, embodiments of the invention are possible in which the reference current through a column line is modulated. This further increases the range of available grey levels. When the modulation is limited to a fraction of the total current to be stored, the associated voltage swing of the current reference line is small and a fast settling can be obtained. The modulation fraction is chosen to compromise between number of grey-levels, circuit complexity and settling time.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim. The word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0309402.6 | Apr 2003 | GB | national |
This application is a divisional application of U.S. patent application Ser. No. 10/554,324, filed Oct. 24, 2005 now U.S. Pat. No. 7,859,493, which status is allowed, which is a US national phase application, and claims benefit, of a PCT application No. PCT/IB2004/001227, filed Apr. 15, 2004, which claims the priority of GB Patent Application No. 0309402.6, filed on Apr. 25, 2003, the disclosures of which are incorporated herein in their entireties by reference.
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| 6433488 | Bu | Aug 2002 | B1 |
| 6501466 | Yamagishi et al. | Dec 2002 | B1 |
| 6731273 | Koyama et al. | May 2004 | B2 |
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| Number | Date | Country | |
|---|---|---|---|
| 20110109670 A1 | May 2011 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10554324 | US | |
| Child | 12947510 | US |
