Patent Application
20070286194
The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
A method and device for processing data packets are provided. Conveniently, the device and method apply multiple hash functions on a key to provide multiple hashed values. These multiple hashed values are used to access multiple hash tables. Conveniently, the multiple hash tables are stored in dynamic memory units, such as but not limited to DDR memory units.
Conveniently, the multiple hash tables are stored in multiple memory banks, especially DDR memory banks. The access to the different memory banks is staggered such that while one or more memory banks are accessed one or more other memory banks are refreshed, thus increasing the utilization of the memory unit.
DDR memories are cheaper than SRAMs and are also subjected to extensive development efforts, due to their importance to the personal computer market. Thus it is expected that their performances will increase while their cost will decrease.
Conveniently, one or more DDR memory units are partitioned to multiple memory banks, each storing a hash tables, and each hash table is accessed by a hashed value that is generated by applying a unique hash function. Different hash tables are accessed by hashed values generated by applying different hash functions.
Conveniently, collisions are managed by accessing different hash tables. If the usage of multiple hash tables is not sufficient additional solutions can be applied. These additional solutions can include at least one of the following solutions, as well as a combination of two or more of these solutions: chaining, using a CAM, assigning another memory entry to a colliding key, overwriting existing entries, and the like.
The inventors found that using multiple hash tables within multiple memory banks solves most cases of collisions and that the mentioned above additional solutions are usually required for solving a relatively small amount of unsolved collisions. For example, a sixteen-entry CAM unit can usually manage unsolved collisions when there are 32,000 hash table entries, and a commodity DDR size is used.
Conveniently, when a new key is provided to the device it simultaneously generates multiple hashed values, accesses multiple hash tables and reads the content of the corresponding hash table entries. If the value does not exist in any of the hash table entries the key can be inserted to the hash table entry with the smallest number of items. In the special case where the hash table depth is one, one of the empty hash table entries can be selected in a random manner. In a better instantiation of this process, the empty hash table is selected according to a fixed priority order of the tables.
It is noted that more than a single hash table can be stored within a single memory bank, although conveniently a memory bank stores one hash table.
According to an embodiment of the invention if a collision is not solved by using the multiple hash tables and a CAM unit is not full, the colliding key is written to the CAM unit. If the CAM unit is full, then the system and method can determine whether to overwrite a hash table entry or a CAM entry. The selection can be responsive to various selection rules.
According to an embodiment of the invention the selection involves applying a probabilistic process. The process includes selecting at random (with probability Ph) an entry of hash table out of the multiple hash tables. The key is written to the selected hash table entry. The process also includes selecting (with probability Pc, wherein 2Ph+Pc=1) an entry of the CAM unit and writing to this entry the colliding key. It is noted that other relationships between Pc and Ph can exist.
The values of Pc and Ph can be set such as to prefer overwriting entries of the hash tables (smaller Pc values) or to prefer overwriting entries of the CAM unit (larger values of Pc).
According to an embodiment of the invention the entries within at least one hash table and/or the entries of the CAM unit undergo a refreshing process in which old entries are deleted (or can be overwritten). An entry is regarded as an old entry after a predefined expiration period expires. Each hash table can have its own expiration period. Conveniently, the expiration period can be responsive to the number of accesses to that entry.
According to an embodiment of the invention the additional solution includes overwriting existing hash table entries if the hash tables entries that are accessed by the multiple hashed values are not vacant. This solution does not require a CAM unit. Conveniently, flags that indicate empty hash table entries can be used to speed up the insertion process.
According to an embodiment of the invention multiple hash table entries are accessed by using multiple hashed values generated by applying multiple hash functions from the same key. Conveniently, if more than one accessed hash table entry is vacant various selection rules can be applied for selecting between the vacant accessed hash table entries. For example, the selection can apply a random or pseudo random process. Yet for another example the hash tables are sorted in a certain order and the selection can be responsive to the order of the hash tables. Thus, if there are B hash tables and they have hash table identifiers that range between 1 and B then the selection can involve selecting the hash table that has the lowest identifier value, the highest identifier value and the like. The selection can be adapted to evenly (or unevenly) distribute the keys among the different vacant hash tables.
For simplicity of explanation only a single memory unit that includes two memory banks is illustrated. The number of memory banks can exceed two. The number of memory units can exceed one. The number of hash tables per memory bank can exceed one. The memory unit can differ from a DDR memory unit. It can be another type of dynamic memory unit but this is not necessarily so. Yet for another embodiment of the invention a combination of static and dynamic memory units can be used.
Device 100 includes a communication controller 10 that is connected to a memory unit such as DDR memory unit 20. DDR memory unit 20 includes two memory banks 21 and 22, wherein the first memory bank 21 stores a first hash table 30 and the second memory bank 22 stores a second hash table 40. Each memory bank can be accessed independently. Furthermore, while one memory bank is accesses the second memory bank can be refreshed.
The communication controller 10 includes multiple input/output ports. For simplicity of explanation only two I/O ports (19 and 19′) are shown as being connected to the DDR memory unit 20, and only two I/O ports (11 and 11′) are illustrated as being connected to additional devices (not shown) for receiving and for outputting data streams.
Communication controller 10 is illustrated as having two data paths, although the number of data paths can exceed two and or be equal to one.
Communication controller 10 includes two interfaces 12 and 12′ that are connected to I/O ports 11 and 11′ respectively, for receiving and storing data packets on one hand and also for storing and outputting data packets. It is noted that the data paths can include different transmit data path and a receive data path but this is not necessarily so.
Interfaces 12 and 12′ are connected to hashing and comparing unit 14. The hashing and comparing unit 14 receives a data packet, generates a key, applies two different hash functions on the key to provide two hashed values, sends the two hashed values to interfaces 18 and 18′. Interface 18 receives a first hashed value and send it via I/O port 19 to memory unit 20 where it is used to access an entry (such as entry 31) of the first hash table 30. The content of that entry (or a content of a group of entries) is sent back to the hashing and comparing unit 14 via I/O port 19 and interface 18.
Interface 18′ receives a second hashed value and send it via I/O port 19′ to memory unit 20 where it is used to access an entry (such as entry 42) of the second hash table 40. The content of that entry (or a content of a group of entries) is sent back to the hashing and comparing unit 14 via I/O port 19′ and interface 18′.
Conveniently, these two access operations are executed in a sequential manner. While the first memory bank 21 is accessed the second memory bank 22 is refreshed and vice verse. Conveniently, if multiple accesses are made per hashed value then the accesses are made in a pipelined manner.
The hashing and comparing unit 14 compares the content of the accessed entries to the generated key. If a match is found than the entry that stored the key is defined as a selected entry. The selected entry either has information indicating how to process the data packet or include a pointer to such information.
If, for example, no match was found then the hashing and comparing unit 14 can determine whether to store the newly generated key in one of the hashing tables.
It is noted that the communication controller 10 can be configures to apply additional solutions to solve collisions. For example, device 100 can include a CAM, such as CAM 70 of
Device 100″ includes four different memory banks 21-24, stored within a single DDR memory unit 20′. The even memory banks (22 and 24) can be accessed in parallel while the odd memory banks (21 and 23) are refreshed and vice verse. It is noted that other combinations of memory banks can be accesses concurrently.
Method 200 starts by stage 210 of receiving a key associated with the data packet. Stage 210 may include extracting information control fields from the data packet and generating a key, manipulating information stored in the data packet to provide the key and the like.
Stage 210 is followed by stage 220 of applying multiple hash functions to provide multiple hashed values. Conveniently, the hash functions differ from each other.
Stage 220 is followed by stage 230 of accessing a group of hash tables using the multiple hashed values. Conveniently, each hashed value is used to access a single hash table.
Conveniently, stage 230 of accessing includes accessing different hash tables that are being stored in different memory banks.
Conveniently, stage 230 of accessing includes accessing different hash tables that are being stored in different dynamic memory banks.
Conveniently, stage 230 of accessing includes accessing at least one hash table stored in at least one dynamic memory bank while refreshing at least one other dynamic memory bank that stores at least one other hash table.
Conveniently, stage 230 also includes searching the key in a content addressable memory. The search can be executed in parallel to the access to the hash tables.
Stage 230 is followed by stage 240 of determining a data packet processing operation in response to the content of accessed entries of the multiple hash tables. If a hash table entry stores the key then the action is selected in response to the content of that entry. For example if the entry also stores an output port number, a flow identifier and the like then this stored information is used during the forwarding of the data packet. Yet for another example the hash table entry can point to a data structure that is processed in order to determine how to manage the data packet, and the like.
Conveniently, stage 240 includes retrieving a data structure associated with an accessed hash table entry if the hash table entry stores the key.
Stage 240 can be followed by stage 250 of deleting old hash table entries or otherwise dynamically updating a content of the hash table entries. Stage 250 can be executed in parallel to any stage out of stages 210-240.
Method 300 starts by stage 310 of receiving a key.
Stage 310 is followed by stage 320 of applying multiple hash functions to provide multiple hashed values.
Stage 320 is followed by stage 330 of accessing a group of hash tables using the multiple hashed values.
Stage 330 may include accessing multiple hash tables stored within different memory banks, accessing multiple hash tables stored within different dynamic memory banks, accessing at least one hash table stored in at least one dynamic memory bank while refreshing at least one other dynamic memory bank that stores at least one other hash table, and the like.
Stage 330 is followed by stage 340 of associating between the key and an accessed vacant entry of a hash table out of the group of hash tables. Conveniently, each hashed value is used to access a set of hash table entries. If one or more hash table entries are full the key can be associated with a remaining vacant hash table entry. This usage can include allocating a set of hash table entries per hash value.
Conveniently, method 300 includes stage 350 of overwriting old hash table entries. Stage 350 can follow stage 340 and can be executed in parallel to any stage of stage 210-240.
Conveniently, stage 340 is followed by stage 360 of storing a key within a content addressable memory if the multiple hashed values generated from the key point to full hash table entries.
Conveniently, method 300 includes stage 370 of determining whether to overwrite hash table entries or to overwrite content addressable memory entries. Stage 370 can be followed by stage 380 of overwriting at least one entry in response to the determination.
Method 400 starts by stage 410 of receiving a key.
Stage 410 is followed by stage 420 of applying multiple hash functions to provide multiple hashed values.
Stage 420 is followed by stage 430 of accessing a group of hash tables using the multiple hashed values.
Stage 430 is followed by stage 440 of providing a search result in response to a content of at least one accessed entries of multiple accessed entries of the multiple hash tables.
While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made.
