Patent Application
20150249679
The present invention relates to devices or products executing sensitive processes or cryptographic algorithms and sensitive to fault attacks, and for which a fatal reaction (such as “card suicide”) cannot be implemented or cannot be used in specific scenarios.
The aim of a fault attack (or injection) may be determination of a secret or a ciphering/deciphering or cryptographic key or modification of a value to get additional rights (such as access or credits).
A fault attack is a type of physical attack that consists in submitting a device (comprising hardware and software capable of executing a sensitive process) to unusual environmental conditions to modify the execution of this sensitive process and to deduce sensitive information from its alter behaviour or results and/or to modify the attacked sensitive process. A fault may produce either a permanent effect which may permanently prevent execution of a sensitive process or modify the content of a memory or register, or a transient effect which may disappear after a reset.
An unusual environmental condition may result from incident particles, an unusual external temperature, an unusual electromagnetic interaction with an external device, incident waves having an unusual frequency, for instance, and may induce an unusual internal power consumption, the use of an unusual radio frequency, an internal temperature modification, or an unusual internal electromagnetism effect, for instance.
As it is known by the man skilled in the art when a device or product is sensitive to fault attacks and does not or cannot implement a fatal reaction (such as card suicide), the fault detection mechanism it usually implements is generally based on a sanction principle, like mute or a wrong return status/data, without any fatal reaction. This sanction principle is interpreted by the attacker as the consequence of its successful fault injection, so that he is very comfortable to perform other attacks until an exploitable fault attack path is found with one or several faults injected.
Moreover, mutes or a wrong return status/data give information for safe-error attack scenarios and enable to set up multi-fault scenario attacks path. Thus there is no limit in numbers of faults injected.
Several solutions have been proposed to avoid prosperity of fault attacks.
A first solution consists in setting up a reaction mechanism which is randomly delayed to avoid temporal knowledge of efficient fault injection. However, if the attacker just uses his fault as an “oracle” for safe-error attack scenario, such a solution is not efficient.
A second solution consists in increasing code complexity with more redundancy, more memory and more data integrity checks. Document “Error detection and error correction procedures for the advanced encryption standard (AES)” from M. Czapski and al. discloses such a solution where the sensitive process is modified as can be seen on
Regarding safe-error attack scenarios, as soon as there is a different reaction (or code execution) between a normal execution and a faulty one, there is no long term protection.
So, an objective of the invention is to propose a new way to react after fault detection.
More precisely, the invention provides a method, intended for protecting an electronic device (comprising hardware and software capable of executing a sensitive process) against fault attack(s), and comprising the steps of:
(i) detecting a fault effect into the electronic device, resulting from at least one fault attack of an attacker during execution of the sensitive process, preferably by at least comparing a result after execution of the sensitive process to a correct result, and
(ii) correcting this detected fault effect, preferably by replacing the result by correct result, before it may be detected by the attacker, so that set up of the fault be considered as missed by this attacker.
In the meaning of the invention, the term “result” covers any element of a state of the electronic device after execution of the sensitive process. The “result” in the meaning of the invention does not correspond to the result of the sensitive process properly speaking but refers to any element resulting from the execution of the sensitive process, faulty or not.
As stated in the first claim, the invention consists in correcting a fault effect during or after the execution of the sensitive process. With the invention, the sensitive process itself is not at all corrected but only the effect of the fault. The sensitive process itself in its original definition is not modified and it authorizes a flexible implementation of the invention. The invention further applies to any kind of faults like fault concerning a program counter, a key, a round counter, an hardware register altered etc. All these elements are results in the meaning of the invention as the execution of the sensitive process, faulty or not, is susceptible to modify one or several of them.
Besides, it can be noticed that the invention does not present any limitations in terms of number of faults.
The method according to the invention may include additional characteristics considered separately or combined, and notably:
In this first embodiment, the first value is the result in first memory obtained after execution of the sensitive process compared to a correct result. As more precisely disclosed later, the correct result is an initial value as obtained before the detected fault effect occurs (i.e. at the end of the last sensitive process execution).
In this second embodiment, the result is the modification. A supplemental comparison is performed between a received information and a confidential information. If the modification has not been induced while an erroneous information was received, the correct result, which is the predetermined modification, is forced.
In this third embodiment, the correct result is selected after several executions of the predetermined algorithm and of the other algorithm. The selected result is the one that was obtained the more important number of times.
Results are thus compared with each other and each result is thus compared to the selected one. Each result of the algorithm differing from this correct result is discarded and the determined correct result is kept whatever being the situation. Here a supplemental comparison is performed between a current value in a predetermined register and a predetermined value. In step (i), in case where execution of the sensitive process comprises execution of a triple Data Encryption Standard (DES) algorithm triggered by a predetermined value in a predetermined register, one may compare the current value in this predetermined register with the predetermined value, and in step (ii), if the current value differs from the predetermined value and is intended for triggering a simple DES, one may execute the simple DES three times, then one may execute the triple DES at least two times, then one may compare results of executions of the three simple DES and of the triple DES, and one may keep the result appearing at least two times and replace the current value with the predetermined value;
This implementation induces the execution of the simple DES three times which gives the result of a triple DES. The correct result which is the one of the triple DES will thus be obtained tree times, one through the three executions of simple DES and two through the use of the two triple DES. The result which is obtained at least two times is thus kept as the correct result.
With this fourth embodiment, the correct result is the result of the algorithm that is the most obtained Each result of the algorithm differing from this correct result is discarded and corrected with the correct result determined after the successive execution of the sensitive process.
According to the invention, the sensitive process itself is not corrected but its result only, in a large understanding, is always corrected.
With the invention, correction actions are performed by default if there is fault or not. This is in order not to introduce any difference in term of algorithm execution leakage if there is a fault or not. Correcting the content of a register, a modification triggering or a final result on a compulsory base insures that the fault is corrected before the detection of the fault by the attacker and before any output is sent outside the electronic device. The detection of the fault is not at properly speaking useful for the triggering of the correction but for counting faults and generating a countermeasure if a given number of faults is reached.
The invention also provides a protection device, intended for equipping an electronic device comprising hardware and software capable of executing a sensitive process, and comprising:
The protection device according to the invention may include additional characteristics considered separately or combined, and notably:
The invention also provides an electronic device comprising hardware and software capable of executing a sensitive process, and a control device such as the one above introduced.
This electronic device may be chosen from a group comprising at least a smart card, a memory card reader, a telecommunication device, and a portable memory means.
Other features and advantages of the invention will become apparent on examining the detailed specifications hereafter and the appended drawing, wherein the unique figure schematically and functionally illustrates an example of electronic device with a microprocessor comprising a protection device according to the invention coupled to a sensitive process.
The appended drawing may serve not only to complete the invention, but also to contribute to its definition, if need be.
The invention aims, notably, at offering a protection method, and an associated protection device PD, intended for protecting an electronic device ED from fault attack(s) of attacker(s).
The invention concerns electronic devices ED comprising hardware and software capable of executing a sensitive process SP and for which a fatal reaction (such as “card suicide”) cannot be implemented or cannot be used in specific scenarios.
In the following description it will be considered that the electronic device ED is a smart card. For instance, it may be a credit card or an electronic identity card or else an electronic passport. But the invention is not limited to this type of electronic device. It concerns a lot of secured devices, and notably card readers, software protection dongles, telecommunication devices (for instance smart phones or electronic tablets), portable memory means (for instance USB keys), and secure modules present in a machine-to-machine communication in smart-metering devices.
In the example illustrated in the unique figure the electronic device ED comprises a microprocessor MP, which comprises hardware and software capable of executing a sensitive process SP, and a protection device PD according to the invention coupled to this sensitive process SP in order to protect it against fault attack(s) of attacker(s).
It is important to note that the protection device PD is not mandatorily located into the microprocessor MP (or any equivalent means, such as integrated circuits, for instance). Indeed, it may be a device that is coupled to the microprocessor MP and may access to the sensitive process SP that is running in it. Such a device PD may be also located into another device of the electronic device ED.
So a protection device PD can be made of software modules, at least partly, or of electronic circuit(s) or hardware modules, or else of a combination of hardware and software modules (in this last case the protection device PD comprises also software interfaces allowing interworking between its hardware and software modules). In case where it is made of software modules it can be stored in a memory means or in any computer software product which can be read by an electronic device.
As illustrated, a protection device PD, according to the invention, comprises at least a detection means DM and a correction means CM.
The detection means DM watches over at least a part of the electronic device ED and notably hardware and software that are concerned by the execution of the sensitive process SP. This watch is intended for detecting a fault effect into the electronic device ED, which results from at least one fault attack of an attacker during execution of the sensitive process SP.
Any type of fault effect induced by an unusual environmental condition of the electronic device ED may be detected by the detection means DM, and notably a modification of a value stored into a memory means (memory or register), the reception of an erroneous code, or an erroneous result of an algorithm or process. Generally speaking a fault effect may be a detected physical variation or the detected consequence of a physical variation.
When the detection means DM detects a fault effect, it may inform the correction means CM by means of a dedicated message describing this detected fault effect.
The correction means CM is arranged for correcting a detected fault effect before it may be detected by the attacker, so that set up of the fault be considered as missed by this attacker.
So, the sensitive process SP appears to “answer” correctly even if the fault injected has been efficient, but for the attacker the fault set up cannot be considered as such because it observes a correct answer to its fault attack(s).
Note that the correction is preferably carried out before any output is sent outside the electronic device ED. If this last condition is fulfilled the protection device PD may allow avoiding multi-faults set up. Indeed, the first fault injection effect being quickly corrected, the attacker does not know that it has been efficient, and therefore he may give up to its multi-faults attack or this may be a blocking event for his multi-faults set up.
The correction will depend of the detected fault effect. Some examples of detection and the corresponding correction are described hereafter.
A first example concerns the fault attacks that induce a modification of a first value that is stored in a first memory means (memory or register) of the microprocessor MP, that may be subject to a fault attack.
In this first example, the detection means DM compares the first value (stored in the first memory means) with an initial value stored in at least one second memory means that it comprises or that belongs to the microprocessor MP. One means here by “initial value” a value that was correct before the detected fault effect occurs (i.e. at the end of the last sensitive process execution). Then, the correction means CM replaces this first value with the initial value into the first memory means if this first value differs from the initial value (it is recalled that this last information is given by the detection means DM). The correction means CM could also regularly rewrites the initial value into the first memory means. In this case the value stored into the first memory means is regularly refreshed with the initial value got from at least one second memory means.
This first example concerns notably the register fault attacks. For instance, a register may be associated to a hardware special function and may contain, for instance, a hardware countermeasure set up which defines security mechanisms that must be activated during the sensitive process SP. So, an attacker could want to modify the content of this register by a single fault injection, for example to remove a memory scrambling, a random delay or a current scrambler, in order to be able to perform a side channel analysis or another analysis on the sensitive process SP. In this case, the protection device PD can enable either a regular adapted rewriting of the register content or a check during execution of the sensitive process SP, in order to restore the correct initial value. Thus the attacker will never see its fault effect on the side channel leakage and will not be able to exploit his fault injection.
A second example concerns the fault attacks that induce acceptance of an erroneous information by a sensitive process SP whose execution requires a confidential information, while reception of such an erroneous information should have induced a predetermined modification.
In this second example, the detection means DM compares each information received by the electronic device ED with the confidential information and determines if this information reception has induced the predetermined modification. Then, if the received information differs from the confidential information and has not induced the predetermined modification, the correction means CM triggers this predetermined modification.
For instance, in case where execution beginning of the sensitive process requires a confidential information which is a confidential code and reception of an erroneous information should induce a predetermined modification which is an increment of a current value of a counter, the detection means DM compares each code received by the electronic device ED with the confidential code, and compares the counter value after this code reception with the counter value before this code reception. Then, if the received code differs from the confidential code and if the counter value after the code reception is identical to the counter value before the code reception, the correction means CM increments the counter value.
This second example concerns notably PIN code verifications. Indeed, if an erroneous PIN code is received and does not induce increment of the corresponding counter value, due to a fault injection, the correction means CM increments this counter value.
A third example concerns the fault attacks that induce execution of an algorithm (for instance a ciphering (or cryptographic) one) that is simpler than the predetermined one which can be triggered by a predetermined value in a predetermined register.
In this third example, the detection means DM compares the current value in the predetermined register with the predetermined value. Then, if this current value differs from this predetermined value and is intended for triggering another algorithm, the correction means CM triggers execution an odd number of times, at least equal to three, of this other algorithm, then it triggers execution at least two times of this predetermined algorithm, then it compares results of executions of the other algorithm and of the predetermined algorithm, then it forces the result appearing at least two times as a correct result, and triggers replacement of the current value with the predetermined value.
In this third example, the detection means DM compares the current value in the predetermined register with the predetermined value which is intended for triggering a triple Data Encryption Standard algorithm (or TDES), for instance. Then, if this current value differs from the predetermined value and is intended for triggering a simple Data Encryption Standard algorithm (or DES), the correction means CM may trigger execution of this simple Data Encryption Standard algorithm three times, then it may trigger execution of the triple Data Encryption Standard algorithm at least two times, then it may compare results of executions of the three successive simple Data Encryption Standard algorithms and of the triple Data Encryption Standard algorithms, then it may force the result that appears at least two times as a correct result, and finally it may trigger replacement of the current value with the predetermined value.
A fourth example concerns the fault attacks that induce modification of the result of one sensitive process execution amongst at least three kind of successive executions that should normally provide three times the same correct result without any fault attack.
In this fourth example, the detection means DM compares the respective results of the successive executions and considers that the result which appears at least two times is the correct result. Then the correction means CM replaces each execution result which differs from this correct result with this correct result. So the execution redundancy is advantageously used to determine which execution is correct (as it has been done at least twice in the same way). This principle can be also applied to ciphering (or cryptographic) algorithms, such as TDES and AES (Advanced Encryption Standard), and to low-level functions used in public algorithms, such as modular operations.
The invention can also be considered in terms of a protection method for an electronic device ED. Such a method may be implemented by means of a protection device PD such as the one above described with reference to the unique figure. Therefore, only its main characteristics will be mentioned hereafter.
The protection method according to the invention comprises the steps of:
(i) detecting a fault effect into the electronic device ED, resulting from at least one fault attack of an attacker during execution of a sensitive process SP, and
(ii) correcting this detected fault effect before it may be detected by the attacker, so that set up of the fault be considered as missed by this attacker.
The invention offers several advantages, amongst which:
The invention is not limited to the embodiments of protection method, protection device and electronic device described above, only as examples, but it encompasses all alternative embodiments which may be considered by one skilled in the art within the scope of the claims hereafter.
| Number | Date | Country | Kind |
|---|---|---|---|
| 12305185.6 | Feb 2012 | EP | regional |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2013/052460 | 2/7/2013 | WO | 00 |
