Patent Application
20250079977
This application claims the benefit of Chinese Patent Application No. 202311103016.0 filed on Aug. 28, 2023, the whole disclosure of which is incorporated herein by reference.
The present disclosure relates to methods and devices to control a power factor corrector (PFC).
A power factor corrector (PFC) is commonly used as a front-end converter, which ensures power supply units having a high power factor and a low input current distortion (i.e., good input current total harmonic distortion (iTHD)).
Theoretically, the output voltage Vbulk of the PFC should have an output voltage ripple with a ripple frequency equal to 2 times the line frequency. It is because the input voltage and current are rectified AC with 2 times the line frequency, and charging and discharging the PFC output capacitor in each AC half cycle creates the voltage ripple. The voltage control loop response should be slow, so that it will not respond to the voltage ripple in the output voltage Vbulk. That means the bandwidth of the voltage control loop is much lower than 2 times the input line frequency. If the voltage control loop respond is too fast, the control output VCLop will be changed continuously within a half AC input cycle. This will distort the current reference signal Iref and will affect the iTHD and the power factor of the PFC.
Good output dynamic load response is a common requirement for the DC/DC converter 105. Some computer systems even require 5% to 100% step load change within a milli-second with an output voltage drop of less than 1%. The output dynamic load response depends on the DC/DC controller 107 and also on the steadiness of the output voltage Vbulk. When a high step load occurs in the DC/DC converter output, the PFC output also experiences a high step load, which increases overshoot or undershoot of the output voltage Vbulk of the PFC, because the PFC voltage control loop has a slow response.
The large undershoot and overshoot of the output voltage Vbulk disrupt stability of the DC/DC converter 105, thereby affecting the output dynamic load response of the DC/DC converter 105. Therefore, it is desired to provide an effective method to keep the stability of the output voltage Vbulk of the PFC when the output of the DC/DC converter 105 experiences a high step load.
Example embodiments of the present invention provide methods and devices to eliminate overshoot or undershoot of an output voltage Vbulk of a PFC when a DC/DC converter output experiences a high step load.
An example embodiment of the present invention provides a method of controlling a power factor corrector (PFC), where the PFC is configured or programmed to receive an input power and to supply a power to a load via a DC/DC converter, the method is executable by a PFC controller configured or programmed to control the PFC, and the PFC controller includes a voltage controller.
The method includes receiving a first signal transmitted from a DC/DC controller configured or programmed to control the DC/DC converter, the first signal indicating the load; deriving a second signal based on the first signal, the second signal being an expected output control signal of the voltage controller under the load indicated by the first signal, and configuring the voltage controller according to the second signal so as to keep an output voltage Vbulk of the PFC to the DC/DC converter stable.
According to an example embodiment of the present disclosure, the voltage controller may be configured or programmed to generate an output control signal VCLop, where the configuring the voltage controller according to the second signal includes according to the second signal, selectively generating the output control signal VCLop based on a difference between a reference voltage signal and the output voltage Vbulk of the PFC, or setting the output control signal VCLop to be equal to the second signal.
According to an example embodiment of the present disclosure, the PFC controller may further include a current controller, the current controller may be configured or programmed to receive a difference of a current IPFC of the PFC and a product of a reference current signal and a constant K as an input so that the current IPFC of the PFC is controlled to be equal to the product of the reference current signal and the constant K, where the constant K may be a constant scaling factor.
According to an example embodiment of the present disclosure, the first signal may be an output power Pout of the DC/DC converter.
According to an example embodiment of the present disclosure, the deriving a second signal may include obtaining the second signal by dividing the output power Pout by a product of an efficiency η and a constant K, where the efficiency η indicates an efficiency of supplying the power to the load from the input power, the constant K may be a constant scaling factor, and a current IPFC of the PFC is controlled to be equal to a product of a reference current signal and the constant K.
According to an example embodiment of the present disclosure, there is no root mean square (RMS) filter in the PFC controller, and the second signal is obtained by dividing the output power Pout by a product of a square of a root mean square value of the input voltage Vin, the efficiency η and the constant K.
According to an example embodiment of the present disclosure, the configuring the voltage controller according to the second signal may include when an absolute value of a difference between the second signal and the output control signal VCLop is greater than a threshold value, setting the output control signal VCLop to be equal to the second signal, and changing a related state variable of the voltage controller so that the voltage controller jumps to a state that matches a latest input power.
According to an example embodiment of the present disclosure, the threshold value may be a specific percentage of a value of the output control signal VCLop at a steady state full load.
According to an example embodiment of the present disclosure, the voltage controller may use a proportional-integral-derivative PID control, and the configuring the voltage controller according to the second signal may include when the absolute value of the difference is less than or equal to the threshold value, determining a sum of a proportional variable, an integral variable, and a derivative variable as the output control signal VCLop, and when the absolute value of the difference is greater than the threshold value, setting the output control signal VCLop to be equal to the second signal, and setting the integral variable to be equal to the second signal.
According to an example embodiment of the present disclosure, the first signal transmitted from the DC/DC controller is received via a signal transmitter across a safety isolation barrier between the PFC controller and the DC/DC controller.
According to an example embodiment of the present disclosure, the first signal is transmitted in a digital form, and the transmission of the first signal, including an encoding and a decoding, is completed within a half milli-second.
An example embodiment of the present invention provides a power factor corrector (PFC) controller configured or programmed to control a power factor corrector PFC, where the PFC may be configured or programmed to receive an input power and to supply a power to a load via a DC/DC converter. The PFC controller may include a voltage controller and may be configured or programmed to receive a first signal from a DC/DC controller, the first signal indicating the load, derive a second signal based on the first signal, the second signal being an expected output control signal of the voltage controller under the load indicated by the first signal, and configure the voltage controller according to the second signal, so as to keep an output voltage Vbulk of the PFC to the DC/DC converter stable.
An example embodiment of the present invention provides a power supply apparatus, including a DC/DC converter, a power factor corrector PFC configured or programmed to receive an input power and to supply a power to a load via the DC/DC converter, a DC/DC controller configured or programmed to control the DC/DC converter and transmit a first signal; and a PFC controller configured or programmed to receive the first signal from the DC/DC controller, the first signal indicating the load, derive a second signal based on the first signal, the second signal being an expected output control signal of a voltage controller included in the PFC controller under the load indicated by the first signal, and configure the voltage controller according to the second signal so as to keep an output voltage Vbulk of the PFC to the DC/DC converter stable.
According to an example embodiment of the present disclosure, the stable output voltage Vbulk improves the dynamic response of output voltage Vout of the DC/DC converter, and at the same time keeps the PFC voltage control loop respond slow so that the input power factor and the iTHD performance are not affected.
The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the example embodiments with reference to the attached drawings.
Hereinafter, the example embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are only illustrative and not intended to limit the scope of the present disclosure. In addition, in the following explanation, descriptions of well-known structures and techniques are omitted to avoid unnecessary confusion with the concepts of the present disclosure.
The terms used here are only intended to describe specific example embodiments and are not intended to limit the present disclosure. The words “a”, “one”, “the” etc. used here should also include the meanings of “multiple” and “a plurality of”, unless the context clearly indicates otherwise. In addition, the terms “include”, “contain”, etc. used here indicate the existence of the features, steps, operations, and/or components, but do not exclude the existence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used here have the meaning commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used here should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.
As mentioned above, good output dynamic load response is a common requirement for the DC/DC converter. Some computer systems even require 5% to 100% step load change within a milli-second with an output voltage drop of less than 1%. The dynamic load response depends on the DC/DC controller and also on the steadiness of the output voltage Vbulk. When a high step load occurs in the DC/DC converter output, the PFC output also experiences a high step load, which increases the overshoot or undershoot of the output voltage Vbulk, because the PFC voltage control loop has a slow response.
In order to solve one or more of the above problems, the example embodiments of the present disclosure provide concepts to achieve output control of the PFC through the feedforward function.
The power supply unit may include a PFC 401, a PFC controller 403, a DC/DC converter 405, and a DC/DC controller 407. The PFC 401 may typically be connected to the DC/DC converter 405 and may receive an input power and may supply a power to a load via the DC/DC converter 405. The PFC controller 403 may include a voltage controller. In addition, the DC/DC converter 405 may typically have a safety isolation barrier. However, the concepts of the present disclosure are applicable regardless of the presence or absence of the safety isolation barrier.
According to an example embodiment of the present disclosure, the PFC controller 403 may further include a current controller. The current controller may be configured or programmed to receive a difference of a current IPFC of the PFC 401 and a product of a reference current signal and a constant K as an input so that the current IPFC of the PFC 401 may be controlled to be equal to the product of the reference current signal and the constant K. In this example embodiment, the constant K may be a constant scaling factor and a positive number. Depending on the scaling, the constant K may be greater than or less than 1.
According to an example embodiment of the present disclosure, the DC/DC controller 407 may acquire the output voltage Vout and the output current Iout signals for control purposes so that it may transmit an additional output power Pout signal (or the output current Iout signal assuming the output voltage Vout is unchanged) to the PFC controller 403. However, the present disclosure is not limited to this. The DC/DC controller 407 may transmit other signals to the PFC controller 403, as long as these signals enable the PFC controller 403 to achieve the stability of the output voltage Vbulk when the DC/DC converter output experiences the high step load.
In order to have a fast response of the output voltage Vbulk to the change of the output load, the transmission of output power Pout should be fast. It is better for the DC/DC controller 407 to output a continuous analog output power Pout signal and to input the output power Pout signal to the PFC controller 403. If there is a safety isolation barrier between the two controllers, some high-speed analog signal transmission devices with input/output isolation should be used.
Therefore, according to an example embodiment of the present disclosure, the power supply unit may further include a signal transmitter 409. This may be an advanced isolated analog signal transmitter or may be a signal transmitter using a high-frequency pulse width modulation (PWM) signal together with an optical or magnetic isolator.
The latter signal transmitter converts the output power Pout signal to a high frequency PWM signal (e.g. the duty cycle is proportional to output power Pout). The PWM signal is transmitted to the PFC controller through an opto-coupler or a signal transformer and then filtered back to an analog signal. The output power Pout signal may also be transmitted in a digital form, but transmission, encoding, and decoding speeds must be fast enough (e.g. complete within a half milli-second).
In the following, a method executed by the PFC controller 403 is described with reference to
In step S502, a first signal transmitted from a DC/DC controller may be received. The first signal may indicate the load.
In an example embodiment of the present disclosure, the first signal may be an output power Pout of the power supply unit. In this example embodiment, in a case that there is a safety isolation barrier between the PFC controller and the DC/DC controller, the first signal from the DC/DC controller may be received via the above-mentioned signal transmitter.
In step S504, a second signal is derived based on the first signal (e.g. the output power Pout). In an example embodiment of the present disclosure, the second signal may be an expected output control signal of the voltage controller under the load indicated by the first signal.
Referring to
In this example embodiment, let η be an efficiency of the power supply unit, and the efficiency η may represent the efficiency of supplying the power to the load from the input power, that is:
where Pin is the input power of the power supply unit, and Pout is the output power of the power supply unit.
In addition, the current IPFC of the PFC may be controlled by the current controller mentioned above to meet the following equation with the reference current Iref:
where K may be a constant scaling factor and a positive number. Depending on the scaling, the constant K may be greater than, equal to, or less than 1.
The input power (Pin=Vin(rms)×IPFC(rms)) of the power supply unit may thus be calculated by the following equation:
where the subscript rms may represent a root mean square value of the variable, for example, Vin(rms) may represent the root mean square value of input voltage Vin.
In addition, according to an example embodiment of the present disclosure, as a signal that may replace the normal voltage controller output VCLop, as shown in the example in
Therefore, Iref(rms) may be derived as follows:
By combining equations 1, 2, and 3, the following equation may be derived:
Therefore, in this example embodiment, deriving the second signal (i.e., the Vc signal) may include obtaining the second signal by dividing the output power Pout by a product of an efficiency η and the constant K.
However, the example embodiments of the present disclosure is not limited to this. For other PFC controllers having different methods to calculate the reference current Iref, the idea is still applicable. For examples, if there is no RMS filter in the PFC controller, then:
By combining equations 1, 2, and 3a, the following equation may be derived:
Therefore, according to an example embodiment of the present disclosure, if there is no RMS filter in the PFC controller, the second signal may be obtained by dividing the output power Pout by a product of a square of a root mean square value of the input voltage Vin, the efficiency η, and the constant K.
Back to
According to an example embodiment of the present disclosure, the voltage controller may be configured or programmed to generate an output control signal VCLop. In this example embodiment, configuring the voltage controller according to the second signal may include, according to the second signal, selectively generating the output control signal VCLop based on a difference between a reference voltage signal and the output voltage Vbulk of the PFC, or setting the output control signal VCLop to be equal to the second signal.
When the PFC controller 403 receives the output power Pout signal from the DC/DC controller 407, the PFC controller 403 may select whether using the Vc signal or the VCLop control signal for reference current Iref calculation. To avoid interfering with normal PFC operation with a steady load, the Vc signal can be used to replace the VCLop control signal only if their values have a big difference. For example, the power supply output dynamic load is good in 20% (of full load) load step even without this new output power Pout feedforward function, but the power supply output dynamic load is worse due to increased overshoot/undershoot of the output voltage Vbulk when it has more than a 20% load step. Then, the PFC controller 403 may set the VCLop control signal to be equal to the Vc signal.
Therefore, according to an example embodiment of the present disclosure, configuring the voltage controller according to the second signal (i.e. the Vc signal) may include, when an absolute value of a difference between the second signal and the output control signal VCLop of the voltage controller is greater than a threshold value, setting the output control signal VCLop to be equal to the second signal. The threshold value may be a specific percentage of a value of the output control signal VCLop at a steady state full load. In this example embodiment, the threshold value may be 20% of the value of VCLop at the steady state full load. Note that “20% of full load” is just a reference suggestion, and the present disclosure is not limited to this. The criteria to apply the Vc signal (i.e., the second signal) may be dependent on various applications, and different criteria are included in the present disclosure.
It may be assumed that the voltage control loop is implemented with proportional-integral-derivative (PID) control. However, the present disclosure is not limited to this. The present disclosure is also applicable to different kinds of controllers.
In the following, a detailed description of how to configure the voltage controller according to the Vc signal under the PID control is provided.
The PID algorithm refers to the proportional-integral-derivative control, which is a common “stability keeping” control algorithm. Conventional PID control may involve a proportional variable, an integral variable, and a derivative variable.
Proportional variable (n)=Kp×Verr(n), where Kp is a proportional gain. As shown in
Integral variable (n)=integral variable (n−1)+Ki×Verr(n), where the constant Ki is an integral gain.
Derivative variable (n)=Kd (Verr (n)−Verr (n−1)), where the constant Kd is a derivative gain.
Therefore, when abs(VCLop−Vc)≤VCLop_FL×20%, where VCLop_FL is the value of VCLop at the steady state full load:
VCLop=Proportional variable+Integral variable+Derivative variable.
When abs (VCLop−Vc)>VCLop_FL×20%:
VCLop=Vc, and the integral variable=Vc.
The purpose of updating the integral variable is to make the voltage controller jump to the state that matches the latest input power. Then the voltage controller may continue working in this state without waiting for slow integral term changing to the expected value (for example, Verr will be near zero after applying Vc).
For controllers other than the PID controller, the related state variables may be changed to make the voltage controller jump to the state that matches the latest input power.
Therefore, according to an example embodiment of the present disclosure, when setting the output control signal VCLop to be equal to the second signal, related state variables of the voltage controller may be changed at the same time so that the voltage controller jumps to a state that matches the latest input power.
Therefore, as mentioned above, the PFC controller executing the method 500 according to the example embodiment may eliminate the overshoot or undershoot in the output voltage Vbulk when the DC/DC converter output experiences a high step load. The stable output voltage Vbulk improves the output voltage Vout dynamic response of the DC/DC converter, and at the same time keeps the PFC voltage control loop response slow so that the input power factor and the iTHD performance are not affected.
The present disclosure refers to the block diagrams and/or flowcharts of computer-implemented methods, apparatuses (systems and/or devices), and/or computer program products to describes exemplary example embodiments. It should be understood that blocks in block diagrams and/or flowcharts and the combination of blocks in block diagrams and/or flowcharts may be achieved through computer program instructions executed by one or more computer circuits. These computer program instructions may be provided to processor circuits such as general-purpose computer circuits, specialized computer circuits, and/or other programmable data processing circuits to generate machines, so that transistors, values stored in memory locations, and other hardware components within such circuits are converted and controlled via instructions executed by processors of computers and/or other programmable data processing apparatuses, to achieve the functions/actions specified in the block diagrams and/or flowcharts, thereby creating apparatuses (functional entities) and/or structures for achieving the functions/actions specified in the block diagrams and/or flowcharts.
These computer program instructions may also be stored in tangible computer-readable mediums, which may guide computers or other programmable data processing apparatuses to function in specific ways, such that the instructions stored in the computer-readable mediums generate products, including instructions that achieve the functions/actions specified in the blocks of the block diagrams and/or flowcharts. Therefore, the example embodiments of the present disclosure may be achieved on hardware and/or software (including firmware, resident software, microcode, etc.) running on processors such as digital signal processors, which may be collectively referred to as “circuits”, “modules”, or variants thereof.
The references to “an example embodiment”, “example embodiment”, etc. in the present disclosure indicates that the described example embodiments may include specific features, structures, or characteristics, but not every example embodiment must include the specific features, structures, or characteristics. Furthermore, these phrases may not necessarily refer to the same example embodiment. In addition, when describing specific features, structures, or characteristics in conjunction with example embodiments, it should be considered that implementing such features, structures, or characteristics in conjunction with other example embodiments (whether explicitly described or not) is within the knowledge scope of those skilled in the art.
It should be understood that although the terms “first”, “second”, etc. may be used in the present disclosure to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish elements from each other. For example, within the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used in the present disclosure, the term “and/or” includes any and all combinations of one or more of the relevant listed items.
While example embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311103016.0 | Aug 2023 | CN | national |
