Charge-coupled devices (CCDs) are well known for their use as sensors in digital imaging and video processing. Specifically, they consist of an array of linked or coupled capacitors, where sampled values of an analog signal are stored as charge. The charge can be shifted along the capacitor array by an applied or clock voltage, thus propagating the charge through the array. The charge is eventually transferred from the CCD as an output signal. Amplification of the output signal is usually required, however, because the signal may be too weak to be accurately read or used in a later stage, or because subsequent operations require a certain threshold voltage. An off-chip amplifier is conventionally used for this process, connected in sequence with the output of the CCD.
Conventional amplifiers achieve low noise by using large input transistor structures to average noise sources. One of the primary difficulties with using conventional amplification techniques is that signal gains made as a result of amplification can also result in an increase in the amount of noise present. This can cause problems in signal clarity, distortion of the output signal in relation to the input signal, or degeneration of the signal through unintentional negative feedback. For this reason, noiseless amplification of signals is desired, particularly in a CCD-based structure.
Within a paper entitled, “Discrete-Time Parametric Amplification Based on a Three-Terminal MOS Varactor: Analysis and Experimental Results” by S. Ranganathan and Y. Tsividis, a parametric technique of increasing voltage gain in an MOS varactor was disclosed. This technique utilizes discrete-time parametric amplification to receive an input voltage that is held on a capacitor, as shown in
VO=(C1/CO)*VI.
Thus, the voltage across the capacitor corresponds to a ratio between the initial capacitance value CI and the output capacitance value CO. The technique of amplification described above does involve a noise factor kT/C associated with the sampling process, although the amplification process is essentially noiseless as it is performed after sampling the signal.
Embodiments of the present invention provide a device with an integrated low-noise parametric amplifier using a CCD-based structure with minimal noise gain. The CCD-based structure may be integrated into an IC chip for a medical monitoring and/or diagnostic device. The amplification of the signal is achieved by using a method of capacitance modulation by varying the surface area of the capacitor plates which are used to convey the charge rather than conventional amplification techniques utilizing transistor transconductance. The corresponding voltage gain introduces very little noise, because no additional sources of noise such as active components are introduced in the charge amplification process while shifting the charge from the larger CCD gate to the smaller CCD gate. The CCD capacitance ratio approach is essentially forming a varactor with a very large turn-down ratio.
A discrete sample of an analog input signal is first taken by the CCD-based structure and converted into a charge, for instance, using a well known method such as a “fill-and-spill” technique. The charge is stored below the surface as minority carriers. By applying a clock voltage to the gates in the device, potential wells are created and shifted accordingly to the voltage input to the gates. The charge present within the potential wells is also transferred as the clock voltage is cycled. The charge can also be referred to as a charge packet as it is a small amount of charge held underneath the gate when a voltage is applied. By moving the charge packet from a gate with a larger surface area to one with a smaller surface area, a voltage gain can be produced because the amount of charge remains the same while the effective capacitance is reduced. The charge can then be outputted from the CCD using either a floating diffusion region or floating gate connected to a sense transistor.
Advantageously, a CCD-based amplifier using the present approach can be implemented in a smaller area than a comparable CMOS process. The gain obtained by the method of this invention can greatly relax noise requirements for any later amplification by transistors, and thus the area occupied by the transistor can also be reduced significantly. This aids in the integration of the CCD-based structure into a larger silicon device incorporating several functions.
One specific application of the current invention is for use in amplifying signals taken from electrocardiogram (ECG) electrodes. One electrode is commonly used as a reference voltage, and the other electrode is used as a signal voltage. Both electrodes are attached to a patient's body, and their respective ends are connected to gates in the CCD which control the input of charge into the CCD. A charge packet equal to the difference in voltages can be created and amplified by the method as described in this invention. Alternatively, a single electrode can be used as the input to create a charge packet of a size equivalent to the voltage input from the electrode and then amplified. The difference between electrode inputs can be calculated at a later point after output from the CCD. Because the electrode connections preferably are directly inputted into the CCD, this results in a high impedance value. This is desirable to avoid any adverse reaction from the patient as a result of the electrical connection to the CCD.
In accordance with an aspect of the present invention, a method of amplifying a signal comprises inputting a signal to a CCD-based device which includes a first gate forming a first capacitor and a second gate forming a second capacitor, the first capacitor having a surface area larger than a surface area of the second capacitor; converting the input signal into a charge packet having a voltage associated therewith; transferring the charge packet from the first capacitor to the second capacitor of the CCD-based device, the voltage associated with the charge packet being multiplied by a ratio of the surface area of the first capacitor divided by the surface area of the second capacitor; and producing an amplified output signal from the multiplied voltage.
In some embodiments, inputting the signal comprises connecting an end of a first electrode to a human or animal body and another end of the first electrode to the CCD-based device. Inputting the signal comprises supplying charges from the first electrode to a diffusion region of the CCD-based device; and converting the signal into a charge packet comprises converting the charges from the first electrode in the diffusion region to the charge packet for the first capacitor, the charge packet being proportional to a voltage associated with the first electrode.
In specific embodiments, inputting the signal comprises connecting an end of a second electrode to a human or animal body and another end of the second electrode to the CCD-based device. Inputting the signal comprises connecting the end of the first electrode to the first gate and connecting the end of the second electrode to a third gate of the CCD-based device, the first electrode having a first voltage associated therewith and the second electrode having a second voltage associated therewith; and converting the signal into a charge packet comprises applying a voltage to a diffusion region of the CCD-based device to generate the charge packet for the first capacitor which is proportional to a difference between the first voltage and the second voltage.
In some embodiments, the method further comprises sampling the signal to create a discrete sample of the input signal prior to converting the discrete sample of the input signal into a charge packet. The charge packet is transferred from the first capacitor to the second capacitor in a substantially noiseless manner. The input signal is used to generate a plurality of charge packets in a plurality of input cycles; and the plurality of charge packets are transferred to and stored in the second capacitor to generate the multiplied voltage before producing the amplified output signal from the multiplied voltage. Producing the amplified output signal comprises transferring the charge packet to a floating diffusion region or a floating gate of the CCD-based device.
In accordance with another aspect of the invention, a method of amplifying a signal comprises inputting a signal to a CCD-based device which includes a plurality of gates forming a plurality of capacitors; converting the input signal into a charge packet having a voltage associated therewith; transferring the charge packet during an input cycle to a storage capacitor associated with one of the plurality of gates; storing multiple charge packets in the storage capacitor over a plurality of input cycles by not resetting the storage capacitor during each of the plurality of input cycles, an accumulated voltage associated with the charge packets being equal to a sum of the voltages associates with each of the multiple charge packets stored in the storage capacitor; and producing an amplified output signal from the accumulated voltage.
In some embodiments, inputting the signal comprises connecting an end of at least one electrode to a human or animal body and another end of the at least one electrode to the CCD-based device. The method may further comprise sampling the signal to create a discrete sample of the input signal prior to converting the discrete sample of the input signal into a charge packet. The charge packets are transferred to the storage capacitor in a substantially noiseless manner. A programmable voltage gain is obtained from the accumulated voltage by varying the number of charge packets accumulated in the storage capacitor before resetting the storage capacitor.
In accordance with another aspect of this invention, a device comprises a CCD-based device including a first gate forming a first capacitor and a second gate forming a second capacitor, the first capacitor having a surface area larger than a surface area of the second capacitor; and a controller configured to input a signal to the CCD-based device; convert the input signal into a charge packet having a voltage associated therewith; transfer the charge packet from the first capacitor to the second capacitor of the CCD-based device, the voltage associated with the charge packet being multiplied by a ratio of the surface area of the first capacitor divided by the surface area of the second capacitor; and produce an amplified output signal from the multiplied voltage. The CCD-based device may comprise a single polysilicon structure or a double polysilicon structure.
In accordance with another aspect of the present invention, a device comprises a CCD-based device including a plurality of gates forming a plurality of capacitors; and a controller configured to convert the input signal into a charge packet having a voltage associated therewith; transfer the charge packet during an input cycle to a storage capacitor associated with one of the plurality of gates; store multiple charge packets in the storage capacitor over a plurality of input cycles by not resetting the storage capacitor during each of the plurality of input cycles, an accumulated voltage associated with the charge packets being equal to a sum of the voltages associates with each of the multiple charge packets stored in the storage capacitor; and produce an amplified output signal from the accumulated voltage.
In addition to the CCD-based structure,
Additionally, it is desirable that all gate voltages are of a sufficient magnitude to form a channel region below them. The voltage V2, however, is of a large enough magnitude to form a much deeper depletion region. In conventional operation, electrons are trapped at the silicon-SiO2 interface. As long as these trap sites remain filled, they will not affect operation. However, if the channel is ever depleted of charge when the signal equals zero, the trap sites will over time recombine with electrons and leave empty traps. The first charge packets to progress down the depletion region will lose some of their electrons to re-fill the traps, and restore the potential level. To avoid this error, the depletion regions are typically clocked with some minimum level of charge greater than zero, commonly known as a “Fat Zero.” With the relatively small input amplitudes expected, it is important to keep some minimum charge moving through the channel to keep the traps filled.
A surface potential plot corresponding to the CCD cross-section is also shown in
When an input signal charge has been fixed and trapped on the capacitor formed by the voltage gates and the inversion region in the substrate, a voltage is produced. Because capacitance of a parallel-plate capacitor is proportional to the area of the plates, a decrease in the area of the capacitor can cause the capacitance value to be reduced while holding the same charge. As applied in the equation Q=CV, if the capacitance value decreases while the same charge is held, the voltage associated with the charge packet must increase. Thus, by moving the trapped charge packet from one gate element to another gate element that has a much smaller capacitance by design, the voltage associated with the charge packet is increased according to the capacitance ratio of the two gate elements.
In
While the current drawings show the surface area of V2 as compared to V3 and the corresponding voltage gain associated with the packet in a 3 to 1 ratio, it is to be understood that other surface areas could also be employed with similar results. For example, charge transfer from a gate with surface area two times as large as the second gate could also be employed, with a corresponding 2 to 1 gain in the voltage associate with the signal charge. Similarly, a charge transfer from a gate with a surface area 10 times as large as a second gate could be employed, with a 10 to 1 gain. The CCD-based structure or amplifier may be designed to provide any desired gain, although a practical limitation may exist in that any increase in the surface area of the gates being used also results in a similar increase in difficulty of integration and added complexity for manufacturing techniques.
Once the input voltage has been sampled and held, the method used for voltage gain does not involve resistors or active components and thus the amplification ideally is virtually noiseless. There are, however, contributors to noise present in a practical application. For a surface CCD implementation as described above, surface interface traps at the silicon-oxide interface can cause low frequency noise and carrier ballistics can cause high frequency noise. Nonetheless, the significant reduction in noise presents an important advantage over prior techniques.
One additional contributor to noise particularly relevant to this application is “Dark Current,” or the accumulation of charge in the potential wells between samples, as introduced by either thermal or photo generation mechanisms. This accumulation rate is at a minimum when there is little or no photocurrent. If the clock rate is slow, this current may be significant in creating charge buildup. To minimize the effect of dark current, the clocks can be run at a faster rate and the actual sample can be after several clock cycles, enough to flush the channel. The CCD-based structure can be cooled to a low temperature with liquid nitrogen or shielded from light to reduce this effect. Ideally, the dark current noise should be reduced to a point where its contribution is negligible over a typical exposure time.
The use of capacitance modulation to increase voltage in the CCD-based structure is similar to the use of a varactor with a very high turn-down ratio. A varactor is a specific kind of diode where voltage can be used to control a variable capacitance formed by the migration of electrons and holes in p-n junction. In the present embodiment, the gate voltage inputted is used to control the transfer of charge between gates of different surface areas, and thus capacitances.
Another method of achieving voltage gain is to input multiple charge packets into a storage capacitor (e.g., capacitor associated with V2 in
After the voltage associated with the signal charge has been amplified, the signal is outputted for further processing. Any suitable output method may be employed. Two methods for charge output are shown in
In
In
In
One specific application of the current invention is for use in amplifying signals taken from electrocardiogram (ECG) electrodes in a medical monitoring and/or diagnostic device which may be implanted into a patient or an animal. The CCD-based structure can be integrated into the circuit or IC chip of the medical device. One ECG electrode is commonly used as a reference voltage, and the other ECG electrode is used as a signal voltage. Both electrodes are attached to a patient's body, and their respective ends are connected to gates in the CCD-based structure which control the input of charge into the CCD-based structure. A charge packet equal to the difference in voltages can be created and amplified by the method described above. Advantageously, a CCD-based amplifier using the present approach can be implemented in a smaller area than a comparable CMOS process.
The electrode connections preferably are directly inputted into the CCD. This results in a high impedance value. This is advantageously because the biological signal sources have a fairly significant impedance. Electrodes that do not load down the source can be an advantage in that maximum signal can be obtained. Commonly, one of the ECG electrodes is connected to the housing of the battery and/or housing of the medical device, so that having high impedance in both electrodes is not completely necessary. Although having high impedance in both sensing electrodes can be helpful in that it results in high flexibility of ECG electrode connections. In some specific situations, there may be no choice in physiological location of the housing (or battery) connection and yet there may be a need to sense differentially at some other location of the body. In cases like this, two high impedance electrodes would be useful or even required. Another reason high impedance electrodes are desirable is the problem of “electroplating” where dc currents in the electrode system can result which in turn cause physiological damage to tissues (i.e., a burning or reddening at the electrode sites). If the electrodes are low impedance, then some means of blocking DC currents is required, usually a blocking capacitor. Even with high impedance electrodes, it is desirable to incorporate a blocking capacitor, but it can be much smaller and it can be integrated onto the IC chip sometimes, providing a significant size/weight advantage. For use in small research animals, such as mice, even the capacitor size can be significant. Furthermore, if there is a requirement to sense all the way down to dc (i.e., 0 frequency), then no blocking capacitor is used and very high impedance electrodes simplify the interfacing.
While the description and drawings illustrate the invention as being implemented in an surface-channel CCD device, it is to be understood that the invention could also be implemented in alternative CCD configurations, such as buried-channel CCDs, bulk-channel CCDs, or MOS-type CCDs. The drawings show the device as being formed with a n-channel implementation, but the device could also be formed with a p-channel implementation as well.
It is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims alone with their full scope of equivalents.
This application claims the benefit of U.S. Provisional Patent Application No. 60/575,528, filed May 28, 2004, the entire disclosure of which is incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
60575528 | May 2004 | US |