Claims
- 1. An in-process floating gate memory device comprising:a floating gate layer; a silicon dioxide layer overlying said floating gate layer; a siliconized nitride layer overlying and contacting said silicon dioxide layer, said siliconized nitride layer having a lower portion which is not siliconized and an upper portion which is siliconized; and a concentration of silicon atoms in said upper portion, wherein said silicon atom concentration in said upper portion of said nitride layer increases throughout said siliconized upper portion of said nitride layer.
- 2. The in-process device of claim 1 further comprising:said lower portion of said siliconized nitride layer having a formula of Si3N4; and said upper portion of said siliconized nitride layer having a formula of SixN4, where x>3.
- 3. The in-process device of claim 2 further comprising said siliconized nitride layer having a thickness of about 100 Å.
Parent Case Info
This application is a division of Ser. No. 09/205,140 filed Dec. 02, 1998 now U.S. Pat. No. 6,297,092.
US Referenced Citations (12)
Non-Patent Literature Citations (2)
Entry |
Cohen, et al. “A novel double metal structure for voltage programmable links” IEEE Electron Device Letters (Skept. 1992) vol. 13, No. 9, pp. 488-490.* |
Cohen, et al. “A novel double metal structure for voltage programmable links” IEEE Electron Device Letters (Skept. 1992) vol. 13, No. 9, pp. 488-490(Abstract). |