Patent Application
20240370623
As integrated circuit (IC) technologies are continually progressing to smaller technology nodes, such as a 32 nm technology node and below, simply scaling down similar designs used at larger nodes often results in inaccurate or poorly shaped device features due to the resolution limit of conventional optical lithography technology. Examples of inaccurate or poorly shaped device features include rounding, pinching, necking, bridging, dishing, erosion, metal line thickness variations, and other characteristics that affect device performance.
Further, in a large-scale IC, multiple layout blocks (or active regions) may be used. A space (or inactive region) is provided between some layout blocks to accommodate printing inaccuracy such as line end rounding, as well as to meet certain spacing requirements for IC manufacturing. It is desirable to minimize such space.
Aspects of the present disclosure are best understood from the following detailed description when they are read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The design house (or design team) 120 generates an IC design layout 122. The IC design layout 122 includes various geometrical patterns designed for the IC 150. An example IC design layout 122 is shown in
The various geometrical device patterns in the IC design layout 122, such as the device patterns 302′ 304′, 306′, 308′, 310′, 312′, and 314′, may correspond to patterns of metal, oxide, or semiconductor layers that make up various components of the IC 150 to be fabricated. The various components may include active regions, source and drain features, gate electrodes, metal lines or vias of an interlayer interconnection, and openings for bonding pads, which are to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. In the present embodiment, the device patterns 302′, 304′, 306′, 308′, 310′, 312′, and 314′ define a mandrel pattern that will be used for etching a substrate (with or without using spacers) to form fins for fin field effect transistors (FinFETs) or other types of multi-gate transistors such as gate-all-around transistors. In an embodiment, the device patterns 302′, 304′, 306′, 308′, 310′, 312′, and 314′ are transferred to a mandrel structure used in a patterning process for IC 150 fabrication. In some embodiments, dummy patterns are added outside the layout blocks 302, 304, 306, 308, 310, 312, and 314 to improve pattern density, which will be described in more details later. The design house 120 implements a proper design procedure to form the IC design layout 122. The design procedure may include logic design, physical design, and/or place and route. The IC design layout 122 is presented in one or more data files having information of the geometrical patterns. For example, the IC design layout 122 can be expressed in a GDSII file format, a DFII file format, or another suitable computer-readable data format.
The mask house 130 uses the IC design layout 122 to manufacture one or more masks to be used for fabricating various layers of the IC 150. The mask house 130 performs mask data preparation 132, mask fabrication 134, and other suitable tasks. The mask data preparation 132 translates the IC design layout 122 into a form that can be physically written by a mask writer. The mask fabrication 134 then fabricates a plurality of masks that are used for patterning a substrate (e.g., a wafer). In the present embodiment, the mask data preparation 132 and mask fabrication 134 are illustrated as separate elements. However, the mask data preparation 132 and mask fabrication 134 can be collectively referred to as mask data preparation.
In the present embodiment, the mask data preparation 132 prepares a pattern layout to be used in a patterning process. The preparation of the pattern layout includes inserting dummy patterns outside the layout blocks 302, 304, 306, 308, 310, 312, and 314 (e.g., in the operation 204); moving a portion of the dummy patterns (e.g., in the operation 206) closer to corners or edges of the layout blocks 302, 304, 306, 308, 310, 312, and 314, the moved portions of the dummy patterns are collectively referred as the third patterns; extending lengths of the third patterns (e.g., in the operation 208); connecting the dummy patterns in same lines. The pattern layout defines a mandrel pattern in a first exposure.
The mask data preparation 132 may further include other operations, such as extending the device patterns and creating cut patterns. The cut patterns may be used for cutting certain patterns during photolithography or removing certain features in an IC during fabrication.
The mask data preparation 132 may further include optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, or other process effects. The mask data preparation 132 may further include a mask rule checker (MRC) that checks the IC design layout with a set of mask creation rules which may contain certain geometric and connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, etc. The mask data preparation 132 may further include lithography process checking (LPC) that simulates processing that will be implemented by the IC manufacturer 140 to fabricate the IC 150. The processing parameters may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process.
It should be understood that the above description of the mask data preparation 132 has been simplified for the purposes of clarity, and data preparation may include additional features such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to the IC design layout 122 during mask data preparation 132 may be executed in a variety of different orders.
After mask data preparation 132 and during mask fabrication 134, a mask or a group of masks are fabricated based on the modified IC design layout. For example, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask can be formed as a transmissive mask, a reflective mask, or other types of mask. In an embodiment, the mask is formed using binary technology, where a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using a phase shift technology. In the phase shift mask (PSM), various features in the pattern formed on the mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM.
The IC manufacturer 140, such as a semiconductor foundry, uses the mask (or masks) fabricated by the mask house 130 to fabricate the IC 150. The IC manufacturer 140 is an IC fabrication business that can include a myriad of manufacturing facilities for the fabrication of a variety of different IC products. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (i.e., front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (i.e., back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business. In the present embodiment, a semiconductor wafer 142 is fabricated using the mask (or masks) to form the IC 150. The semiconductor wafer 142 includes a silicon substrate or other proper substrate having material layers formed thereon. Other proper substrate materials include another suitable elementary semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The semiconductor wafer may further include various doped regions, dielectric features, and multilevel interconnects formed at various manufacturing steps. The mask may be used in a variety of processes. For example, the mask may be used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etching regions in the semiconductor wafer, and/or other suitable processes.
In operation, the mask design system 136 is configured to manipulate the IC design layout 122 before it is transferred to a mask 139 by the mask fabrication 134. In an embodiment, the mask data preparation 132 in
The method 200 may be implemented in the various components of the IC manufacturing system 100. For example, the operations 202, 204, 206, 208, 210 and 212 may be implemented in the mask data preparation 132 of the mask house 130; the operation 214 may be implemented in the mask fabrication 134 of the mask house 130; and the operations 216, 218, and 220 may be implemented in the IC manufacturer 140. The method 200 is merely an example for illustrating various aspects of the provided subject matter. Additional operations can be provided before, during, and after the method 200, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method 200. The method 200 in
At operation 202, referring to
In the present embodiments, the IC design layout 122 includes the layout blocks 302, 304, 306, 308, 310, 312, and 314 that are distributed (or disposed, placed) in the IC design layout 122 by design requirements. For example, the layout blocks 310, 312, and 314 are disposed apart from other layout blocks without sharing edges (or common edges, common borders). In an alternative example, the layout blocks 306 and 308 of the same shape and size are disposed adjacent to each other with a shared edge in a symmetric manner. In another example, the layout blocks 320 and 304 of the same shape but different size are positioned together with a common edge MN. A corner α of the larger layout block 302 protrudes away from the smaller layout block 304 along the common edge MN. The edge MO, a portion MQ of the edge MN, and an edge QP form a Z shape OMQP. In the present embodiments, the Z shape OMQP is a right-angle Z shape. The layout blocks 320 and 340 each include a plurality of device patterns 302′, 304′, 306′, 308′, 310′, 312′, and 314′ respectively, designed according to restrictive design rules (RDR). An example IC layout according to RDR includes parallel line patterns extending in the same direction and spaced by a line pitch where the line width and line pitch are designed so as to improve image printing quality by utilizing constructive light interference. In the present embodiments, the device patterns 302′, 304′, 306′, 308′, 310′, 312′, and 314′ are line patterns oriented lengthwise along the X direction.
In some design, dummy patterns are disposed outside the layout blocks to adjust the pattern density. Well-controlled pattern density throughout the IC improve product quality and reduce processing complexity. For example, adequate pattern density prevents or reduces dishing effect during chemical mechanical planarization (CMP) in fabrication processes, thereby achieving better topography after CMP. In another example, suitable pattern density and device density improve etching uniformity during etching processes.
To adjust pattern density across the IC, dummy patterns are inserted outside the layout blocks and are designed to have the same or very similar densities as the patterns (which may include device patterns and/or dummy patterns) inside the layout blocks. In general, space outside the layout blocks is divided into multiple regions (e.g., rectangular regions) such that the dummy patterns in each region have uniform sizes, line pitches, and column distances. Such design provides balances between pattern density and process complexity. However, due to the irregular distribution and non-uniform sizes of the layout blocks, dummy patterns may not be properly inserted and/or distributed in the areas near the corner and/or edge of the layout blocks, leaving empty space between the regions of dummy patterns and affecting the pattern density and device density. Embodiments of the present disclosure provides methods of improving the pattern density by inserting dummy patterns in the empty space near the corners and edges of the layout blocks. For example, by moving and elongating dummy patterns next to the corners and edges of the layout blocks to reduce the empty space.
At operation 204, referring to
The multiple regions may include arrays of dummy patterns of same or different sizes and shapes. For example, region 301 includes an array of patterns 400 next to an edge OM of the layout block 302, and region 303 includes an array of patterns 402 next to the edge MN of the layout block 302 and the edge QP of the layout block 304. The region 301 is the only region next to the edge OM. Similarly, the region 303 is the only region next to the edges MQ and QP. In some embodiments, the line pitches and the column distances of different arrays of dummy patterns may differ. In the present embodiments, the line pitches, column distances, pattern line width, and pattern line length are the same in different regions. For example, as shown in
A height h1 from the edge OM to a bottommost line of patterns 400 in the region 301 is less than a sum of the width w1 and pitch p1. The height h1 can be less than the sum of the width w1 and pitch p1 because the way region 301 is designed and positioned. For example, the region 301 is a rectangular shaped and is the only region disposed above the edge OM along the entire length of the edge OM. In the case where height h1 is greater than the sum of the width w1 and pitch p1, an additional line of the patterns 400 is inserted between the region 301 and the edge OM. Similarly, the height h2 from the bottommost patterns 402 to the edge QP of the layout block 304 is less than a sum of the width w2 and pitch p2.
An irregular (or non-rectangular) space 405 is disposed between the region 301 and the region 303. The irregular space 405 has a width D3 at a top portion and a width D0 at a bottom portion. The width D3 is defined from the rightmost column 401 in the region 301 to the leftmost column 403 in the region 303, where D3 is less than a sum of the length L1 and two times of the distance D1 in the present embodiments. An additional column may be inserted to the region 301 and/or the region 303 in the case where D3 is greater than a sum of the length L1 and two times of the distance D1. The distance D0 is defined from the column 403 to the common edge MN. The distance D0 is less than the distance D3. The irregular space 405 is also defined by a corner α of the layout block 320, edges OM and MQ of the corner α, and an edge QP of the layout block 304. The edges OM, MQ, and QP forms a Z shape OMQP with a corner α. In the present embodiments, the corner α is a 90° angle, i.e., the Z shape OMQP is a right-angle Z shape OMQP.
At operation 206, referring to
Still referring to
A distance D4 between the column 401 and the column 403 may be any user defined value for improving pattern density. In the present embodiments, the distance D4 is designed to be the same as the distance D1 to simplify the subsequent operations, such as adding connecting patterns 412 to connect dummy patterns in the same line as shown in
In one embodiment, D3 is less than a sum of the length L1 and the distance D1, and the distance D4 equals to the distance D1, such that a sum of a moving distance Dm of column 401 and a moving distance Dm′ of column 403 is less than a sum of the width w1 and the distance D1. In some embodiments, the distance Dm is different from the distance Dm′. In the present embodiments, the distance Dm is the same as the distance Dm′ for process simplification. In this case, a distance D5 between the patterns 402′ and the nearest patterns 402 in the same line is less than a sum of 0.5 times L1 and 1.5 times D1 after the moving of the column 401 and the column 403. A distance D7 between the column 403 after the moving is less than the distance D0 before the moving as shown in
At operation 208, referring to
The length L3 of the patterns 404 and the length L4 of the patterns 406 may be any user defined value to achieve design requirements. For example, L3 may be different from (i.e., greater than or less than) L4. In the present embodiments, the length L3 equals to the length L4 for process simplicity. A distance D5 between the patterns 404 and the patterns 400 and a distance D9 between the patterns 406 and the patterns 402 are related to the lengths L3 and L4. In the present embodiments, the D8 and D9 are designed to be the same as the distance D1, the lengths L3 and L4 are designed such that the distances D8 and D9 are designed to be the same as the distance D1. In an example where the distance D5 is less than a sum of 0.5 times L1 and 1.5 times D1 as explained above (
At operation 210, referring to
Referring to
At operation 212, referring back to
At operation 214, the method 200 manufactures a mask with the pattern layout. In some embodiments, the mask may be a transmissive mask (e.g., for deep ultraviolet lithography) or a reflective mask (e.g., for extreme ultraviolet lithography), and may include imaging enhancement features such as phase shifting. In embodiments where maskless lithography, such as e-beam direct writing, is used, operation 214 is bypassed or involves data preparation for the particular direct writer without fabricating an actual mask. In the present embodiments, the mask carries the pattern layout including the layout blocks 302, 304, 306, 308, 310, 312, and 314 and the device patterns disposed therein and the dummy patterns outside the layout blocks including the extended line patterns.
At operation 216, referring to
Referring to
The mandrel structure 560 is formed by patterning the dielectric layer 540 with a procedure including a lithography process and an etching process. For example, a photoresist (or resist) layer (not shown) is formed on the dielectric layer 540 using a spin-coating process and soft baking process. Then, the photoresist layer is exposed to a radiation using the mask manufactured in the operation 214. The exposed photoresist layer is developed using post-exposure baking, developing, and hard baking thereby forming a patterned photoresist layer over the dielectric layer 540. Subsequently, the dielectric layer 540 is etched through the openings of the patterned photoresist layer, forming the mandrel structure 560. The etching process may include a dry (or plasma) etching, a wet etching, or other suitable etching methods. The patterned photoresist layer is removed thereafter using a suitable process, such as wet stripping or plasma ashing. During the above photolithography process, the density and uniformity of the mandrel structure 560, including device mandrel lines inside the layout blocks and the dummy mandrel lines outside the layout blocks, help improve pattern critical dimension uniformity in view of optical proximity effect.
In some embodiments, the mandrel structure 560 is used directly as a mask to fabricate components (such as fins) on the substrate. Alternatively, derivatives of the mandrel structure 560, such as spacers, may be formed and then used to fabricate components (such as fins) on the substrate. For example, the spacers may be formed on sidewalls of the mandrel structure 560 and completely surrounds the mandrel structure 560. In an embodiment, the spacers have a substantially uniform thickness. The spacers include one or more materials different from the mandrel structure 560. In an embodiment, the spacers may include a dielectric material, such as titanium nitride, silicon nitride, or titanium oxide. The spacers can be formed by various processes, including a deposition process and an etching process. For example, the deposition process may include a CVD process or a PVD process. For example, the etching process may include an anisotropic etch such as plasma etch. In the embodiment depicted in
At operation 218, referring to
At operation 220, the method 200 performs further processes to complete the fabrication of the final IC 150. For example, the operation 220 may form isolation structure 600 as shown in
The operation 220 may also form gate stacks (not shown) over the device fins and dummy fins using a gate-first process or a gate-last process. Thereafter, the operation 220 may form source and drain regions (not shown) in the fins using ion implantation, epitaxial growth, and/or other suitable methods. Other processes include forming source and drain contacts, forming gate contacts, and forming via and metal interconnects, and so on.
Although not intended to be limiting, the present disclosure provides many benefits to the manufacturing of an IC. For example, the present disclosure includes a method of forming dummy patterns outside layout blocks to increase the pattern density. Specifically, space around corners and/or edges of the layout blocks are filled with dummy patterns by moving nearby columns of patterns from adjacent regions, extending the lengths of the moved patterns along a direction opposite to the moving direction, and connecting the patterns in same lines. The present embodiments improve pattern density and device density to improve IC processes, such as reducing dishing effect during CMP and increasing etching uniformity.
In one aspect, the present disclosure provides a method that includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block has a corner, adding first patterns along a first edge of the corner, adding second patterns along a second edge of the corner, moving a first column of the first patterns closest to the second edge horizontally toward the second edge, moving a second column of second patterns closest to the second edge horizontally toward the second edge, extending lengths of the first and second patterns in the first and second columns, and outputting a pattern layout in a computer-readable format, where the pattern layout includes the first patterns and the second patterns.
In another aspect, the present disclosure provides a method of forming a pattern layout for semiconductor fabrication that includes providing an integrated circuit (IC) design layout including a first layout block and a second layout block sharing a common edge with the first layout block, where a first edge of the first layout block connected to the common edge is parallel to a second edge of the second layout block connected to the common edge, adding first patterns over the first edge, adding second patterns over the second edge, moving a first column of the first patterns nearest to the common edge laterally toward the common edge, moving a second column of the second patterns nearest to the common edge laterally toward the common edge, adding third patterns contacting each of the first patterns in the first column extending away from the common edge, adding fourth patterns contacting each of the second patterns in the second column extending away from the common edge, and outputting a pattern layout in a computer-readable format, where the pattern layout includes the first, the second, the third, and the fourth patterns.
In yet another aspect, the present disclosure provides a pattern layout for semiconductor fabrication that includes a layout block having a border. The border includes a first edge, a second edge parallel to the first edge, and a third edge perpendicular to and connecting the first and the second edges, where the first edge and the second edge are disposed on opposite sides of the third edge. The pattern layout further includes a first column of first patterns disposed over and parallel to the first edge, a second column of second patterns disposed over and parallel to the second edge, and third patterns between the first patterns and the second patterns. The third patterns are disposed in a third column and a fourth column, where the fourth column includes more patterns than the third column.
The foregoing outlines features of several embodiments so that those having ordinary skill in the art may better understand the aspects of the present disclosure. Those having ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those having ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims priority as a continuation to application Ser. No. 17/566,472 filed Dec. 30, 2021, which in turn claims priority to U.S. Provisional Patent Application Ser. No. 63/214,889 filed on Jun. 25, 2021, the entire disclosures of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63214889 | Jun 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17566472 | Dec 2021 | US |
| Child | 18772161 | US |
