Method And System For A Low-Voltage Integrated Silicon High-Speed Modulator

Abstract

Methods and systems for a low-voltage integrated silicon high-speed modulator may include an optical modulator comprising first and second optical waveguides and two optical phase shifters, where each of the two optical phase shifters may comprise a p-n junction with a horizontal section and a vertical section and an optical signal is communicated to the first optical waveguide. A portion of the optical signal may then be coupled to the second optical waveguide. A phase of at least one optical signal in the waveguides may be modulated utilizing the optical phase shifters. A portion of the phase modulated optical signals may be coupled between the two waveguides, thereby generating two output signals from the modulator. A modulating signal may be applied to the phase shifters which may include a reverse bias.

Description

FIELD

Certain embodiments relate to semiconductor processing. More specifically, certain embodiments relate to a method and system for a low-voltage integrated silicon high-speed modulator.

BACKGROUND

As data networks scale to meet ever-increasing bandwidth requirements, the shortcomings of copper data channels are becoming apparent. Signal attenuation and crosstalk due to radiated electromagnetic energy are the main impediments encountered by designers of such systems. They can be mitigated to some extent with equalization, coding, and shielding, but these techniques require considerable power, complexity, and cable bulk penalties while offering only modest improvements in reach and very limited scalability. Free of such channel limitations, optical communication has been recognized as the successor to copper links.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY

A system and/or method for a low-voltage integrated silicon high-speed modulator, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

Various advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A is a block diagram of a photonically enabled CMOS chip comprising low-voltage, high-speed modulators, in accordance with an example embodiment of the disclosure.

FIG. 1B is a diagram illustrating a CMOS chip, in accordance with an example embodiment of the disclosure.

FIG. 1C is a diagram illustrating a CMOS chip coupled to an optical fiber cable, in accordance with an example embodiment of the disclosure.

FIG. 2 is a schematic illustrating an electro-optic modulator, in accordance with an example embodiment of the disclosure.

FIG. 3 illustrates a vertical p-n junction optical phase shifter, in accordance with an example embodiment of the disclosure.

FIG. 4 illustrates a horizontal junction optical phase shifter, in accordance with an example embodiment of the disclosure.

FIG. 5 illustrates modeling results for a horizontal junction optical phase shifter, in accordance with an example embodiment of the disclosure.

DETAILED DESCRIPTION

Certain aspects of the disclosure may be found in a method and system for a low-voltage integrated silicon high-speed modulator. Exemplary aspects of the disclosure may comprise an optical modulator comprising first and second optical waveguides and two optical phase shifters, where each of the two optical phase shifters comprise a p-n junction with a horizontal section and a vertical section, and where an optical signal is communicated to the first optical waveguide. A portion of the optical signal may then be coupled to the second optical waveguide. A phase of at least one optical signal in the first and second waveguides may be modulated utilizing the optical phase shifters. A portion of the phase modulated optical signals may be coupled between the two waveguides, thereby generating two output signals from the modulator. A modulating signal may be applied to the phase shifters. The p-n junction of the phase shifters may be reverse biased for modulating the phase of the at least one optical signal. The horizontal and vertical sections of the p-n junction may form an “L” shape. The p-n junction may comprise three rectangular sections, a first section being an p-type semiconductor layer, a second section being a portion of an n-type semiconductor layer coplanar with the first section, and a third section being another portion of the n-type semiconductor layer but formed above the first and second sections. The p-n junction may be reverse biased such that a depletion width of the p-n junction extends across most but not all of the third section. The modulator may be integrated in silicon. The horizontal and vertical sections of the p-n junction may be formed in a waveguide rib. The modulator may be integrated in a CMOS chip. The p-n junction may be formed by ion implantation.

FIG. 1A is a block diagram of a photonically enabled CMOS chip comprising low-voltage, high-speed modulators, in accordance with an example embodiment of the disclosure. Referring to FIG. 1A, there is shown optoelectronic devices on a CMOS chip 130 comprising optical modulators 105A-105D, photodiodes 111A-111D, monitor photodiodes 113A-113H, and optical devices comprising directional couplers 103A-103K, optical terminations 115A-115D, and grating couplers 117A-117H. There are also shown electrical devices and circuits comprising amplifiers 107A-107D, analog and digital control circuits 109, and control sections 112A-112D. The amplifiers 107A-107D may comprise transimpedance and limiting amplifiers (TIA/LAs), for example.

Optical signals are communicated between optical and optoelectronic devices via optical waveguides 110 fabricated in the CMOS chip 130. Single-mode or multi-mode waveguides may be used in photonic integrated circuits. Single-mode operation enables direct connection to optical signal processing and networking elements. The term “single-mode” may be used for waveguides that support a single mode for each of the two polarizations, transverse-electric (TE) and transverse-magnetic (TM), or for waveguides that are truly single mode and only support one mode whose polarization is TE, which comprises an electric field parallel to the substrate supporting the waveguides. Two typical waveguide cross-sections that are utilized comprise strip waveguides and rib waveguides. Strip waveguides typically comprise a rectangular cross-section, whereas rib waveguides comprise a rib section on top of a waveguide slab.

The optical modulators 105A-105D comprise Mach-Zehnder or ring modulators, for example, and enable the modulation of the continuous-wave (CW) laser input signal. The optical modulators 105A-105D comprise high-speed and low-speed phase modulation sections and are controlled by the control sections 112A-112D. The high-speed phase modulation section of the optical modulators 105A-105D may modulate a CW light source signal with a data signal. The low-speed phase modulation section of the optical modulators 105A-105D may compensate for slowly varying phase factors such as those induced by mismatch between the waveguides, waveguide temperature, or waveguide stress and this low-speed adjustment or modulation is referred to as the passive phase, or the passive biasing of the MZI.

The electro-optical modulator is one of the main building blocks in silicon photonic transceiver circuits. In general, both phase and intensity can be used to modulate light. A conventional phase modulator on a silicon platform is a p-n junction embedded into a waveguide. It is often used in a Mach-Zehnder interferometer configuration, which consists of two arms receiving similar optical intensity after a power splitter. With each arm endowed with a phase modulator, it is then possible to achieve intensity modulation by interfering the outputs of the two arms, using a power combiner, as shown in FIG. 2.

The phase modulators may have a dual role: to compensate for the passive biasing of the MZI and to apply the additional phase modulation used to modulate the light intensity at the output port of the MZI according to a data stream. The former phase tuning and the latter phase modulation may be applied by separate, specialized devices, since the former is a low speed, slowly varying contribution, while the latter is typically a high speed signal. These devices are then respectively referred to as the LSPM and the HSPM. Examples for LSPM are thermal phase modulators (TPM), where a waveguide portion is locally heated up to modify the index of refraction of its constituting materials, or forward biased PIN junction phase modulators (PINPM) where current injection into the PIN junction modifies the carrier density, and thus the index of refraction of the semiconductor material. An example of an HSPM is a reversed biased PIN junction, where the index of refraction is also modulated via the carrier density, but which allows much faster operation, albeit at a lower phase modulation efficiency per waveguide length.

The outputs of the modulators 105A-105D may be optically coupled via the waveguides 110 to the grating couplers 117E-117H. The directional couplers 103A-103K may comprise four-port optical couplers, for example, and may be utilized to sample or split the optical signals generated by the optical modulators 105A-105D, with the sampled signals being measured by the monitor photodiodes 113A-113H. The unused branches of the directional couplers 103D-103K may be terminated by optical terminations 115A-115D to avoid back reflections of unwanted signals.

The grating couplers 117A-117H comprise optical gratings that enable coupling of light into and out of the CMOS chip 130. The grating couplers 117A-117D may be utilized to couple light received from optical fibers into the CMOS chip 130, and the grating couplers 117E-117H may be utilized to couple light from the CMOS chip 130 into optical fibers. The grating couplers 117A-117H may comprise single polarization grating couplers (SPGC) and/or polarization splitting grating couplers (PSGC). In instances where a PSGC is utilized, two input/output, waveguides may be utilized.

The optical fibers may be epoxied, for example, to the CMOS chip, and may be aligned at an angle from normal to the surface of the CMOS chip 130 to optimize coupling efficiency. In an example embodiment, the optical fibers may comprise single-mode fiber (SMF) and/or polarization-maintaining fiber (PMF).

In another exemplary embodiment, optical signals may be communicated directly into the surface of the CMOS chip 130 without use of optical fibers by directing a light source on an optical coupling device in the chip, such as the light source interface 135 and/or the optical fiber interface 139. This may be accomplished with directed laser sources and/or optical sources on another chip flip-chip bonded to the CMOS chip 130.

The photodiodes 111A-111D may convert optical signals received from the grating couplers 117A-117D into electrical signals that are communicated to the amplifiers 107A-107D for processing. In another embodiment of the invention, the photodiodes 111A-111D may comprise high-speed heterojunction phototransistors, for example, and may comprise germanium (Ge) in the collector and base regions for absorption in the 1.3-1.6 μm optical wavelength range, and may be integrated on a CMOS silicon-on-insulator (SOI) wafer.

The analog and digital control circuits 109 may control gain levels or other parameters in the operation of the amplifiers 107A-107D, which may then communicate electrical signals off the CMOS chip 130. The control sections 112A-112D comprise electronic circuitry that enable modulation of the CW laser signal received from the splitters 103A-103C. The optical modulators 105A-105D may require high-speed electrical signals to modulate the refractive index in respective branches of a Mach-Zehnder interferometer (MZI), for example. In an example embodiment, the control sections 112A-112D may include sink and/or source driver electronics that may enable a bidirectional link utilizing a single laser.

In operation, the CMOS chip 130 may be operable to transmit and/or receive and process optical signals. Optical signals may be received from optical fibers by the grating couplers 117A-117D and converted to electrical signals by the photodetectors 111A-111D. The electrical signals may be amplified by transimpedance amplifiers in the amplifiers 107A-107D, for example, and subsequently communicated to other electronic circuitry, not shown, in the CMOS chip 130.

Integrated photonics platforms allow the full functionality of an optical transceiver to be integrated on a single chip, such as the CMOS chip 130, for example. A transceiver chip comprises optoelectronic circuits that create and process the optical/electrical signals on the transmitter (Tx) and the receiver (Rx) sides, as well as optical interfaces that couple the optical signal to and from one or more fibers. The signal processing functionality may comprise modulating the optical carrier, detecting the optical signal, splitting or combining data streams, and multiplexing or demultiplexing data on carriers with different wavelengths. In another example scenario, a plurality of chips may be utilized, with an optical interposer for receiving electronics chips and photonics chips, in instances where the electronics chips and photonics chips are manufactured in different CMOS nodes.

The light source may be external to the chip or may be integrated with the chip in a hybrid scheme. It is often advantageous to have an external continuous-wave (CW) light source, because this architecture allows heat sinking and temperature control of the source separately from the transceiver chip 130. An external light source may also be connected to the transceiver chip 130 via a fiber interface.

An integrated transceiver may comprise at least three optical interfaces, including a transmitter input port to interface to the CW light source, labeled as “CW Laser In 101”; a transmitter output port to interface to the fiber carrying the optical signal, labeled “Optical Signals Out”; and a receiver input port to interface to the fiber carrying the optical signal, labeled “Optical Signals In”.

In an example scenario, the optical modulators 105A-105D may comprise low-voltage, high-speed modulators with a horizontal p-n junction design, as shown in at least FIG. 4, which may result in improved modal overlap of the depletion region with the propagating optical mode. This may be compared to a vertical p-n junction design as shown in FIG. 3.

FIG. 1B is a diagram illustrating an exemplary CMOS chip, in accordance with an exemplary embodiment of the invention. Referring to FIG. 1B, there is shown the CMOS chip 130 comprising electronic devices/circuits 131, optical and optoelectronic devices 133, a light source interface 135, CMOS chip front surface 137, an optical fiber interface 139, and CMOS guard ring 141.

The light source interface 135 and the optical fiber interface 139 comprise grating couplers, for example, that enable coupling of light signals via the CMOS chip surface 137, as opposed to the edges of the chip as with conventional edge-emitting devices. Coupling light signals via the CMOS chip surface 137 enables the use of the CMOS guard ring 141 which protects the chip mechanically and prevents the entry of contaminants via the chip edge.

The electronic devices/circuits 131 comprise circuitry such as the amplifiers 107A-107D and the analog and digital control circuits 109 described with respect to FIG. 1A, for example. The optical and optoelectronic devices 133 comprise devices such as the directional couplers 103A-103K, optical terminations 115A-115D, grating couplers 117A-117H, optical modulators 105A-105D, high-speed heterojunction photodiodes 111A-111D, and monitor photodiodes 113A-113H.

In an example scenario, the optical modulators 105A-105D may comprise low-voltage, high-speed modulators with a horizontal p-n junction design with improved modal overlap of the depletion region with the propagating optical mode.

FIG. 1C is a diagram illustrating a CMOS chip coupled to an optical fiber cable, in accordance with an exemplary embodiment of the invention. Referring to FIG. 1C, there is shown the CMOS chip 130 comprising the CMOS chip surface 137, and the CMOS guard ring 141. There is also shown a fiber-to-chip coupler 143, an optical fiber cable 145, and an optical source assembly 147.

The CMOS chip 130 comprising the electronic devices/circuits 131, the optical and optoelectronic devices 133, the light source interface 135, the CMOS chip surface 137, and the CMOS guard ring 141 may be as described with respect to FIG. 1B.

In an example scenario, the optical modulators 105A-105D may comprise low-voltage, high-speed modulators with a horizontal p-n junction design with improved modal overlap of the depletion region with the propagating optical mode.

FIG. 2 is a schematic illustrating an electro-optic modulator, in accordance with an example embodiment of the disclosure. Referring to FIG. 2, there is shown an optical modulator 200 comprising optical waveguides 201A and 201B and optical phase shifters 203A and 203B. There is also shown an input signal P_in 205 and output signals P_out 207A and 207B.

The waveguides 201A and 201B may comprise materials of differing dielectric constants such that optical signals are confined. For example, a silicon waveguide with air and/or silicon dioxide cladding may carry optical signals and may come into close proximity at two locations in the optical modulator 200 as shown in FIG. 2, which may result in a transfer of a portion of the optical mode from one waveguide to the other.

The optical phase shifters 203A and 203B may comprise optoelectronic devices that may be operable to shift the phase of received optical signals. For example, p-n junctions formed in the waveguides 201A and 201B may be utilized to shift the phase of optical signals that travel through the depletion region, since the index of refraction is changed with respect to the non-depleted regions of the waveguides. Reverse-biased p-n junctions result in an increased depletion width and thus more phase shift.

Optical modulation amplitude (OMA) is one of the key performance parameters of an electro-optic phase modulator used in digital communication systems. The OMA directly influences the system bit error rate (BER) and hence is desired to be as large as possible. In bi-level optical signaling schemes, the higher level represents a binary one, and the lower power level represents a zero (maximum and minimum of Po in FIG. 2). OMA is defined as the difference between the high and low levels: OMA=max(P_out)−min(P_out).

The magnitude of OMA depends on phase shift difference accumulated between the two arms, waveguides 201A and 201B, of the optical modulator 200 as well as the optical loss that the beam suffers passing through the waveguides. The following equation describes this relation:

OMA(L)=P_ine^−α·L sin(θ·L)

where P_in is the input optical power, α is the optical loss per unit length, L is the length of the modulator and θ is the difference in phase shift between two arms per unit length. As can be seen from the relation, OMA increases with increasing phase shift and decreases by increasing loss. As a result, there is an optimal modulator length, beyond which the OMA no longer improves.

FIG. 3 illustrates a vertical p-n junction optical phase shifter, in accordance with an example embodiment of the disclosure. Referring to FIG. 3, there is shown a p-n junction optical phase shifter 300 comprising p-region 305, n-region 307, contacts 301A and 301B, a p+ region 303 and an n+ region 309. There is also shown an anode and a cathode where electrical connections may be made.

The contacts 301A and 301B may comprise metal layers formed on the p+ region 303 and the n+ region 309, for providing a low-resistance electrical connection to the p-n junction. The p+ region 303 and n+ region may comprise p-type and n-type doped regions, respectively, with higher doping than the p-region 305 and the n-region 307. This higher doping may be useful for reducing the resistance of electrical contact to the p-n junction formed by the p-region 305 and the n-region 307. In another example scenario, a p++ region and an n++ region may be optionally formed under the contacts 301A and 301B, respectively, for better electrical contact, i.e., lower contact resistance.

The waveguide rib shown in FIG. 3 may be formed by etching portions of the p+ region 303, the p-region 305, the n-region 307, and the n+ region 309, with what may considered a “shallow” trench etch as compared to a deep trench etch for isolating optical devices by etching down to the insulator layer in a silicon-on-insulator (SOI) CMOS wafer, for example. In an example scenario, the doping in the p+ region 303, the p-region 305, the n-region 307, and the n+ region 309 may be formed through ion implantation, for example, although other techniques are possible, such as diffusion.

Depletion mode p-n junction modulators are used for high-speed silicon photonics applications because their intrinsic bandwidth may be well beyond 100 GHz. However, their disadvantage is that they generally suffer from smaller phase shifts compared to other means. A typical p-n junction is shown in FIG. 3, where the vertical p-n junction is placed in the middle of the waveguide rib where the optical mode propagates. The phase shift limitation in this type of modulator is due to the poor modal overlap of the vertical depletion region with the propagating optical mode.

FIG. 4 illustrates a horizontal junction optical phase shifter, in accordance with an example embodiment of the disclosure. Referring to FIG. 4, there is shown a horizontal junction optical phase shifter 400 comprising contacts 401A and 401B, a p++region 403, a p+ region 405, a p-region 407, an n-region 409, an n+ region 411, and an n++ region 413. There is also shown a horizontal p-n junction 415, a vertical p-n junction 417, and a junction offset 419, the latter corresponding to the width between the vertical p-n junction 417 and the center of the rib.

The contacts 401A and 401B, p+ region, and n+ region 411 may be similar to the similarly named elements of FIG. 3, and the p++ region 403 and n++region 413 may be p- and n-doped regions, respectively, with higher doping levels than the p+ and n+ regions for improved contact resistance.

The structure of the p-region 407 and the n-region 409, however, is modified compared to FIG. 3 in that the p-n junction is now “L” shaped with a horizontal junction 415 and a vertical junction 417. The p-layer 407 and a portion of the n-layer 409 may be coplanar while a second portion of the n-layer may be formed above the p-layer 407 and a portion of the n-layer 409. This profile was determined through rigorous process, electrical, and optical simulations and provides a significantly improved modal overlap of the depletion region with the propagating optical mode. As a result, OMA is greatly improved over previous designs.

Depending on the junction offset 419, the length of the horizontal p-n junction 415 may be varied and a mostly horizontal p-n junction can be achieved. This mixed junction geometry can be realized by adjusting the implantation process to implant the upper and lower portions of the waveguide separately. In an example scenario, three implantation steps may be utilized for each section, i.e., the p-layer 407, the lower portion of the n-layer 409, the upper portion of the n-layer 409. The energy and dose of each implantation step, as well as the horizontal and vertical location of the junction, may be optimized to achieve the highest possible improvement in the OMA. Moreover, this choice may be balanced to ensure an un-depleted, low-impedance path to the edge of the depletion regions under all biasing conditions used in the modulator, which may assure that the phase shift of a modulator utilizing the horizontal junction optical phase shifter 400 does not degrade at higher frequencies.

In operation, the optical phase shifter 400 may be reverse biased for increased phase shift per unit length, as the depletion width is increased with reverse bias. For example, devices with the structure illustrated in FIG. 4 have exhibited over 22 degrees/mm at 1.8V bias. A modulating signal may also be applied across the contacts 401A and 401B to modulate an optical signal traveling through the phase shifter 400, which may travel into or out of the plane of the structure in FIG. 4.

FIG. 5 illustrates modeling results for a horizontal junction optical phase shifter, in accordance with an example embodiment of the disclosure. Referring to FIG. 5, there are shown simulation results for the horizontal p-n junction comprising the p-layer 507 and n-layer 509. The plots below illustrate how the depletion width of an exemplary junction grows as the reverse voltage is varied from 0V to 1.8V.

The horizontal junction allows for the depletion width to grow mostly where the intensity of the optical mode is also highest, as illustrated by the contour lines indicating the optical mode intensity. At the same time, the design is such that at the widest depletion width, there is still some un-depleted, low impedance path to the edge of the depletion region. A modulator with the modeled horizontal junction optical phase shifters may result in a 2 dB improvement in OMA over a modulator with vertical junction optical phase shifters.

In an example embodiment, a method and system are disclosed for a low-voltage integrated silicon high-speed modulator. In this regard, aspects of the disclosure may comprise optical modulator comprising first and second optical waveguides and two optical phase shifters, where each of the two optical phase shifters comprising a p-n junction with a horizontal section and a vertical section, and where optical signal is communicated to the first optical waveguide. A portion of the optical signal may then be coupled to the second optical waveguide.

A phase of at least one optical signal in the first and second waveguides may be modulated utilizing the optical phase shifters. A portion of the phase modulated optical signals may be coupled between the two waveguides, thereby generating two output signals from the modulator. A modulating signal may be applied to the phase shifters for modulating the phase of the at least one optical signal. The p-n junction of the phase shifters may be reverse biased.

The horizontal and vertical sections of the p-n junction may form an “L” shape. The p-n junction may comprise three rectangular sections, a first section being a p-type semiconductor layer, a second section being a portion of an n-type semiconductor layer coplanar with the first section, and a third section being another portion of the n-type semiconductor layer but formed above the first and second sections. The p-n junction may be reverse biased such that a depletion width of the p-n junction extends across most but not all of the third section. The modulator may be integrated in silicon. The horizontal and vertical sections of the p-n junction may be formed in a waveguide rib. The modulator may be integrated in a CMOS chip. The p-n junction may be formed by ion implantation.

As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As utilized herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As utilized herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As utilized herein, a device/module/circuitry/etc. is “operable” to perform a function whenever the device/module/circuitry/etc. comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled, or not enabled, by some user-configurable setting.

While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A waveguide, comprising: a slab portion including a p-doped region and a first n-doped region that abut to define a first PN junction in a first plane and including a first surface in a second plane perpendicular to the first plane; anda rib portion including a second n-doped region that projects perpendicularly from the first plane from the p-doped region and the first n-doped region and defines a second PN junction in the second plane.

2. The waveguide of claim 1, further comprising: a p+ doped region extending from the p-doped region in a first direction perpendicular to the first plane and including a first portion that projects from the first surface to a third plane parallel to the second plane; andan n+ doped region extending from the first n-doped region in a second direction opposite to the first direction and including a second portion that projects from the first surface to the third plane.

3. The waveguide of claim 2, further comprising: a p++ doped region extending from the first portion of the p+ doped region; andan n++ doped region extending from the second portion of the n+ doped region.

4. The waveguide of claim 3, further comprising: a first electrical contact connected to the p++ doped region; anda second electrical contact connected to the n++ doped region.

5. The waveguide of claim 3, wherein: the first n-doped region and the second n-doped region are doped at an equal concentration;the n+ doped region is doped at a higher concentration than the first n-doped region;the n++ doped region is doped at a higher concentration than the n+ doped region;the p+ doped region is doped at a higher concentration than the p-doped region; andthe p++ doped region is doped at a higher concentration than the p+ doped region.

6. The waveguide of claim 1, wherein the second plane is separated from a third plane that is parallel to the second plane by a junction offset, wherein the third plane bisects the rib portion.

7. The waveguide of claim 6, wherein the p-doped region contacts the rib portion on both sides of the third plane.

8. A waveguide, comprising: a first doped portion having a first side, a second side, and a third side;a second doped portion, having a fourth side;a third doped portion, having a fifth side, and sixth side, and a seventh side;wherein the fourth side of the second doped portion abuts the third side of the first doped portion and the seventh side of the third doped portion and forms a first PN junction with a region of the seventh side of the third doped portion that the fourth side of the second doped portion abuts to;wherein the second side of the first doped portion abuts the sixth side of the third doped portion and forms a second PN junction; andwherein the first side of the first doped portion and the fifth side of the third doped portion are coplanar; andwherein the third side of the first doped portion, the fourth side of the second doped portion, and the seventh side of the third doped portion are coplanar.

9. The waveguide of claim 8, wherein the first doped portion and the second doped portion are n doped, and wherein the third doped portion is p doped.

10. The waveguide of claim 8, wherein the first doped portion and the second doped portion are p doped, and wherein the third doped portion is n doped.

11. The waveguide of claim 8, wherein the second doped portion is bisected by a first plane parallel to the second PN junction, wherein the second PN junction is located in a second plane offset from the first plane by a junction offset.

12. The waveguide of claim 11, wherein the third doped portion extends past the first plane to contact more of the fourth side of the second doped portion than the first doped portion contacts.

13. The waveguide of claim 8, further comprising: a fourth doped portion, doped at a higher concentration than the first doped portion, connected to the first doped portion opposite to the second PN junction; anda fifth doped portion, doped at a higher concentration than the third doped portion, connected to the second doped portion opposite to the second PN junction.

14. A waveguide, comprising: a slab portion including an n-doped region and a first p-doped region that abut to define a first PN junction in a first plane and including a first surface in a second plane perpendicular to the first plane; anda rib portion including a second p-doped region that projects perpendicularly from the first plane from the n-doped region and the first p-doped region and defines a second PN junction in the second plane.

15. The waveguide of claim 14, further comprising: a p+ doped region extending from the first p-doped region in a first direction perpendicular to the first plane and including a first portion that projects from the first surface to a third plane parallel to the second plane; andan n+ doped region extending from the n-doped region in a second direction opposite to the first direction and including a second portion that projects from the first surface to the third plane.

16. The waveguide of claim 15, further comprising: a p++ doped region extending from the first portion of the p+ doped region; andan n++ doped region extending from the second portion of the n+ doped region.

17. The waveguide of claim 16, further comprising: a first electrical contact connected to the p++ doped region; anda second electrical contact connected to the n++ doped region.

18. The waveguide of claim 16, wherein: the first p-doped region and the second p-doped region are doped at an equal concentration;the n+ doped region is doped at a higher concentration than the n-doped region;the n++ doped region is doped at a higher concentration than the n+ doped region;the p+ doped region is doped at a higher concentration than the first p-doped region; andthe p++ doped region is doped at a higher concentration than the p+ doped region.

19. The waveguide of claim 14, wherein the second plane is separated from a third plane that is parallel to the second plane by a junction offset, wherein the third plane bisects the rib portion.

20. The waveguide of claim 19, wherein the n-doped region contacts the rib portion on both sides of the third plane.