Patent Application
20170148525
The disclosed embodiments relate generally to memory systems, and in particular, to adaptive verify voltage adjustment in a non-volatile memory system (e.g., comprising one or more flash memory devices).
Semiconductor memory devices, including flash memory, typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A flash memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Flash memory is a non-volatile data storage device that can be electrically erased and reprogrammed. More generally, non-volatile memory (e.g., flash memory, as well as other types of non-volatile memory implemented using any of a variety of technologies) retains stored information even when not powered, as opposed to volatile memory, which requires power to maintain the stored information.
Writing data to some types of non-volatile memory, including flash memory, may require verifying that the data was properly written. Verify voltages corresponding to the data values are used to perform the verification. However, errors in the data can occur between the time that the data is written to the memory and the time a read operation is performed to read the data in the memory cell. Therefore, it would be desirable to adaptively adjust the verify voltage for one or more portions of the memory to reduce the incidence of error.
Various embodiments of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and particularly after considering the section entitled “Detailed Description,” one will understand how the aspects of various embodiments are used to enable adaptive verify voltage adjustment in memory devices.
The disclosed device and method improve the endurance of non-volatile memory, such as flash memory, by adaptively adjusting a verify voltage to reduce storage raw bit error rate. In conjunction with decoding data read from non-volatile memory, a plurality of error parameters are determined, in accordance with which a verify adjustment signal is determined. Further, in accordance with a determination that a verify trigger event has occurred, and in accordance with the verify adjustment signal, a verify voltage is adjusted. Thereafter, data write operations are performed using the adjusted verify voltage.
So that the present disclosure can be understood in greater detail, a more particular description may be had by reference to the features of various embodiments, some of which are illustrated in the appended drawings. The appended drawings, however, merely illustrate the more pertinent features of the present disclosure and are therefore not to be considered limiting, for the description may admit to other effective features.
In accordance with common practice the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures.
The various implementations described herein include systems, methods and/or devices used to enable adaptive verify voltage adjustment in memory devices. Some implementations include systems, methods and/or devices to adaptively adjust a verify voltage to reduce storage raw bit error rate.
(A1) More specifically, some embodiments include a method of operation in a non-volatile memory system. The method includes: (1) in conjunction with decoding data read from non-volatile memory in the non-volatile memory system, determining a plurality of error parameters, (2) determining, in accordance with the plurality of error parameters, a verify adjustment signal, (3) determining whether a verify trigger event has occurred, (4) in accordance with a determination that a verify trigger event has occurred, adjusting a verify voltage in accordance with the verify adjustment signal, and (5) performing data write operations to write data to non-volatile memory in the non-volatile memory system using the adjusted verify voltage to verify the data written using the data write operations.
(A2) In some embodiments of the method of A1, the plurality of error parameters are determined in accordance with data read operations performed at predefined usage milestones with respect to portions of the non-volatile memory in the non-volatile memory system.
(A3) In some embodiments of the method of any of A1-A2, determining the plurality of error parameters includes: (1) determining a first set of error counts for data read using a first set of voltage thresholds, (2) determining a second set of error counts for data read using a second set of voltage thresholds, and (3) computing a first set of one or more error parameters and a second set of one or more error parameters from the first and second sets of error counts.
(A4) In some embodiments of the method of A3, the first and second sets of error counts each include a plurality of error sum values.
(A5) In some embodiments of the method of A4, the first and second sets of error counts further include a plurality of error difference values.
(A6) In some embodiments of the method of any of A3-A5, determining, in accordance with the plurality of error parameters, the verify adjustment signal includes: (1) applying a first scaling factor to the second set of error parameters, (2) determining whether one or more parameters of the first set of error parameters exceeds one or more corresponding parameters of the scaled second set of error parameters, and (3) in accordance with a determination that the one or more parameters of the first set of error parameters exceeds the one or more corresponding parameters of the scaled second set of error parameters, setting the verify adjustment signal to a first adjustment value.
(A7) In some embodiments of the method of A6, determining, in accordance with the plurality of error parameters, the verify adjustment signal further includes: (1) applying a second scaling factor to the second set of error parameters, (2) determining whether one or more parameters of the scaled second set of error parameters exceeds one or more corresponding parameters of the first set of error parameters, and (3) in accordance with a determination that the one or more parameters of the scaled second set of error parameters exceeds the one or more corresponding parameters of the first set of error parameters, setting the verify adjustment signal to a second adjustment value.
(A8) In some embodiments of the method of any of A1-A7, determining whether the verify trigger event has occurred includes: (1) updating a status counter according to the verify adjustment signal, and (2) determining whether the status counter satisfies any respective range limit of a set of one or more range limits. In these embodiments, the method further includes, in accordance with a determination that the status counter satisfies a respective range limit of the set of one or more range limits, resetting the status counter to an initial value.
(A9) In some embodiments, the method of any of A1-A8 further includes repeating the method for each of a plurality of non-volatile memory portions to generate a separate adjusted verify voltage for each of the plurality of non-volatile memory portions.
(A10) In another aspect, a non-volatile memory system includes non-volatile memory, one or more processors, and memory storing one or more programs, which when executed by the one or more processors cause the non-volatile memory system to: (1) in conjunction with decoding data read from non-volatile memory in the non-volatile memory system, determine a plurality of error parameters, (2) determine, in accordance with the plurality of error parameters, a verify adjustment signal, (3) determine whether a verify trigger event has occurred, (4) in accordance with a determination that a verify trigger event has occurred, adjust a verify voltage in accordance with the verify adjustment signal, and (5) perform data write operations to write data to non-volatile memory in the non-volatile memory system using the adjusted verify voltage to verify the data written using the data write operations.
(A11) In some embodiments of the non-volatile memory system of A10, the one or more processors comprise one or more processors of a storage controller and the one or more programs include a verify voltage adjust module that determines the plurality of error parameters, determines the verify adjustment signal, determines whether the verify trigger event has occurred, and in accordance with a determination that a verify trigger event has occurred, adjusts the verify voltage in accordance with the verify adjustment signal.
(A12) In some embodiments of the non-volatile memory system of A10 or A11, the one or more programs include instructions that when executed by the one or more processors cause the non-volatile memory system to perform the method of any of A1-A9, described above.
(A13) In yet another aspect, a non-volatile memory system includes non-volatile memory, one or more processors, and memory storing one or more programs, which when executed by the one or more processors cause the non-volatile memory system to perform the method of any of A1-A9, described above.
(A14) In yet another aspect, a non-transitory computer readable storage medium stores one or more programs configured for execution by one or more processors of a non-volatile memory system, the one or more programs including instructions that when executed by the one or more processors cause the non-volatile memory system to perform the method of any of A1-A9, described above.
(A15) In yet another aspect, a non-volatile memory system includes: (1) means for determining, in conjunction with decoding data read from non-volatile memory in the non-volatile memory system, a plurality of error parameters, (2) means for determining, in accordance with the plurality of error parameters, a verify adjustment signal, (3) means for determining whether a verify trigger event has occurred, (4) means for adjusting, in accordance with a determination that a verify trigger event has occurred, a verify voltage in accordance with the verify adjustment signal, and (5) means for performing data write operations to write data to non-volatile memory in the non-volatile memory system using the adjusted verify voltage to verify the data written using the data write operations.
(A16) In yet another aspect, the non-volatile memory system of A15 is further configured to perform the method of any of A1-A9, described above.
Numerous details are described herein to provide a thorough understanding of the example implementations illustrated in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the scope of the claims is only limited by those features and aspects specifically recited in the claims. Furthermore, well-known methods, components, and circuits have not been described in exhaustive detail so as not to unnecessarily obscure more pertinent aspects of the implementations described herein.
Computer system 110 is coupled to storage controller 124 through data connections 101. However, in some embodiments computer system 110 includes storage controller 124, or a portion of storage controller 124, as a component and/or as a subsystem. For example, in some embodiments, some or all of the functionality of storage controller 124 is implemented by software executed on computer system 110. Computer system 110 may be any suitable computer device, such as a computer, a laptop computer, a tablet device, a netbook, an internet kiosk, a personal digital assistant, a mobile phone, a smart phone, a gaming device, a computer server, or any other computing device. Computer system 110 is sometimes called a host, host system, client, or client system. In some embodiments, computer system 110 is a server system, such as a server system in a data center. In some embodiments, computer system 110 includes one or more processors, one or more types of memory, a display and/or other user interface components such as a keyboard, a touch-screen display, a mouse, a track-pad, a digital camera, and/or any number of supplemental I/O devices to add functionality to computer system 110. In some embodiments, computer system 110 does not have a display and other user interface components.
Storage medium 130 is coupled to storage controller 124 through connections 103. Connections 103 are sometimes called data connections, but typically convey commands in addition to data, and optionally convey metadata, error correction information and/or other information in addition to data values to be stored in storage medium 130 and data values read from storage medium 130. In some embodiments, however, storage controller 124 and storage medium 130 are included in the same device (i.e., an integrated device) as components thereof. Furthermore, in some embodiments, storage controller 124 and storage medium 130 are embedded in a host device (e.g., computer system 110), such as a mobile device, tablet, other computer or computer controlled device, and the methods described herein are performed, at least in part, by the embedded storage controller. Storage medium 130 may include any number (i.e., one or more) of memory devices (e.g., NVM 134-1, NVM 134-2 through NVM 134-n) including, without limitation, persistent memory or non-volatile semiconductor memory devices, such as flash memory device(s). For example, flash memory device(s) can be configured for enterprise storage suitable for applications such as cloud computing, for database applications, primary and/or secondary storage, or for caching data stored (or to be stored) in secondary storage, such as hard disk drives. Additionally and/or alternatively, flash memory device(s) can also be configured for relatively smaller-scale applications such as personal flash drives or hard-disk replacements for personal, laptop, and tablet computers.
Memory devices (e.g., NVM 134-1, NVM 134-2, etc.) of storage medium 130 include addressable and individually selectable blocks, such as selectable portion of storage medium 131 (also referred to herein as selected portion 131). In some embodiments, the individually selectable blocks (sometimes called erase blocks) are the minimum size erasable units in a flash memory device. In other words, each block contains the minimum number of memory cells that can be erased simultaneously. Each block is usually further divided into a plurality of pages and/or word lines, where each page or word line is typically an instance of the smallest individually accessible (readable) portion in a block. In some embodiments (e.g., using some types of flash memory), the smallest individually accessible unit of a data set, however, is a sector, which is a subunit of a page. That is, a block includes a plurality of pages, each page contains a plurality of sectors, and each sector is the minimum unit of data for writing data to or reading data from the flash memory device.
In some embodiments, storage controller 124 includes a management module 121-1, a host interface 129, an input buffer 123-1, an output buffer 123-2, an error control module 125 and a storage medium I/O interface 128. Storage controller 124 may include various additional features that have not been illustrated for the sake of brevity and so as not to obscure pertinent features of the example embodiments disclosed herein, and a different arrangement of features may be possible. Host interface 129 provides an interface to computer system 110 through data connections 101. Similarly, storage medium I/O 128 provides an interface to storage medium 130 though connections 103. In some embodiments, storage medium I/O 128 includes read and write circuitry, including circuitry capable of providing reading signals to storage medium 130 (e.g., reading threshold voltages for NAND-type flash memory).
In some embodiments, management module 121-1 includes one or more processing units 122-1 (sometimes herein called CPUs, processors, or hardware processors, and sometimes implemented using microprocessors, microcontrollers, or the like) configured to execute instructions in one or more programs (e.g., in management module 121-1). In some embodiments, the one or more CPUs 122-1 are shared by one or more components within, and in some cases, beyond the function of storage controller 124. Management module 121-1 is coupled to host interface 129, error control module 125 and storage medium I/O 128 in order to coordinate the operation of these components. In some embodiments, one or more modules of management module 121-1 are implemented in management module 121-2 of computer system 110. In some embodiments, one or more processors of computer system 110 (not shown) are configured to execute instructions in one or more programs (e.g., in management module 121-2). Management module 121-2 is coupled to storage device 120 in order to manage the operation of storage device 120.
Error control module 125 is coupled to storage medium I/O 128, input buffer 123-1, output buffer 123-2, and management module 121-1. Error control module 125 is provided to limit the number of uncorrectable errors inadvertently introduced into data during writes to memory or reads from memory. In some embodiments, error control module 125 is executed in software by the one or more CPUs 122-1 of management module 121-1, and, in other embodiments, error control module 125 is implemented in whole or in part using special purpose circuitry to perform data encoding and decoding functions. To that end, error control module 125 includes an encoder 126 and a decoder 127. Encoder 126 encodes data by applying an error control code to produce a codeword, which is subsequently stored in storage medium 130.
When the encoded data (e.g., one or more codewords) is read from storage medium 130, decoder 127 applies a decoding process to the encoded data to recover the data, and to correct errors in the recovered data within the error correcting capability of the error control code. Those skilled in the art will appreciate that various error control codes have different error detection and correction capacities, and that particular codes are selected for various applications for reasons beyond the scope of this disclosure. As such, an exhaustive review of the various types of error control codes is not provided herein. Moreover, those skilled in the art will appreciate that each type or family of error control codes may have encoding and decoding algorithms that are particular to the type or family of error control codes. On the other hand, some algorithms may be utilized at least to some extent in the decoding of a number of different types or families of error control codes. As such, for the sake of brevity, an exhaustive description of the various types of encoding and decoding algorithms generally available and known to those skilled in the art is not provided herein.
During a write operation, input buffer 123-1 receives data to be stored in storage medium 130 from computer system 110. The data held in input buffer 123-1 is made available to encoder 126, which encodes the data to produce one or more codewords. The one or more codewords are made available to storage medium I/O 128, which transfers the one or more codewords to storage medium 130 in a manner dependent on the type of storage medium being utilized.
A read operation is initiated when computer system (host) 110 sends one or more host read commands (e.g., via data connections 101) to storage controller 124 requesting data from storage medium 130. Storage controller 124 sends one or more read access commands to storage medium 130, via storage medium I/O 128, to obtain raw read data in accordance with memory locations (addresses) specified by the one or more host read commands. Storage medium I/O 128 provides the raw read data (e.g., comprising one or more codewords) to decoder 127. If the decoding is successful, the decoded data is provided to output buffer 123-2, where the decoded data is made available to computer system 110. In some embodiments, if the decoding is not successful, storage controller 124 may resort to a number of remedial actions or provide an indication of an irresolvable error condition.
Each of the above identified elements may be stored in one or more of the previously mentioned memory devices that together form memory 206, and corresponds to a set of instructions for performing a function described above. The above identified modules or programs (i.e., sets of instructions) need not be implemented as separate software programs, procedures or modules, and thus various subsets of these modules may be combined or otherwise re-arranged in various embodiments. In some embodiments, memory 206 may store a subset of the modules and data structures identified above. Furthermore, memory 206 may store additional modules and data structures not described above. In some embodiments, the programs, modules, and data structures stored in memory 206, or the computer readable storage medium of memory 206, provide instructions for implementing respective operations in the methods described below with reference to
Although
As discussed below with reference to
Flash memory devices utilize memory cells to store data as electrical values, such as electrical charges or voltages. Each flash memory cell typically includes a single transistor with a floating gate that is used to store a charge, which modifies the threshold voltage of the transistor (i.e., the voltage needed to turn the transistor on). The magnitude of the charge, and the corresponding threshold voltage, is used to represent one or more data values. In some embodiments, during a read operation, a reading threshold voltage is applied to the control gate of the transistor and the resulting sensed current or voltage is mapped to a data value.
The terms “cell voltage” and “memory cell voltage,” in the context of flash memory cells, typically mean the threshold voltage of the memory cell, which is the minimum voltage that needs to be applied to the gate of the memory cell's transistor in order for the transistor to conduct current. Similarly, reading threshold voltages (sometimes also called reading signals, reading voltages, and/or read thresholds) applied to flash memory cells are gate voltages applied to the gates of the flash memory cells to determine whether the memory cells conduct current at that gate voltage. In some embodiments, when a flash memory cell's transistor conducts current at a given reading threshold voltage, indicating that the cell voltage is less than the reading threshold voltage, the raw data value for that read operation is a “1,” and otherwise the raw data value is a “0.”
Sequential voltage ranges 301 and 302 between voltages VSS and Vmax are used to represent corresponding bit values “1” and “0,” respectively. Each voltage range 301, 302 has a respective center voltage V1 301b, V0 302b. As described below, in many circumstances the memory cell current sensed in response to an applied reading threshold voltages is indicative of a memory cell voltage different from the respective center voltage V1 301b or V0 302b corresponding to the respective bit value written into the memory cell. Errors in cell voltage, and/or the cell voltage sensed when reading the memory cell, can occur during write operations, read operations, or due to “drift” of the cell voltage between the time data is written to the memory cell and the time a read operation is performed to read the data stored in the memory cell. For ease of discussion, these effects are collectively described as “cell voltage drift.” Each voltage range 301, 302 also has a respective voltage distribution 301a, 302a that may occur as a result of any number of a combination of error-inducing factors, examples of which are identified above.
In some implementations, a reading threshold voltage VR is applied between adjacent center voltages (e.g., applied proximate to the halfway region between adjacent center voltages V1 301b and V0 302b). Optionally, in some implementations, the reading threshold voltage is located between voltage ranges 301 and 302. In some implementations, reading threshold voltage VR is applied in the region proximate to where the voltage distributions 301a and 302a overlap, which is not necessarily proximate to the halfway region between adjacent center voltages V1 301b and V0 302b.
In order to increase storage density in flash memory, flash memory has developed from single-level (SLC) cell flash memory to multi-level cell (MLC) flash memory so that two or more bits can be stored by each memory cell. As discussed below with reference to
Sequential voltage ranges 311, 312, 313, 314 between voltages VSS and Vmax are used to represent corresponding bit-tuples “11,” “01,” “00,” “10,” respectively. Each voltage range 311, 312, 313, 314 has a respective center voltage 311b, 312b, 313b, 314b. Each voltage range 311, 312, 313, 314 also has a respective voltage distribution 311a, 312a, 313a, 314a that may occur as a result of any number of a combination of factors, such as electrical fluctuations, defects in the storage medium, operating conditions, device history (e.g., number of program-erase (PE) cycles), and/or imperfect performance or design of write-read circuitry.
Ideally, during a write operation, the charge on the floating gate of the MLC would be set such that the resultant cell voltage is at the center of one of the ranges 311, 312, 313, 314 in order to write the corresponding bit-tuple to the MLC. Specifically, the resultant cell voltage would be set to one of V11 311b, V01 312b, V00 313b and V10 314b in order to write a corresponding one of the bit-tuples “11,” “01,” “00” and “10.” In reality, due to the factors mentioned above, the initial cell voltage may differ from the center voltage for the data written to the MLC.
Reading threshold voltages VRA, VRB and VRC are positioned between adjacent center voltages (e.g., positioned at or near the halfway point between adjacent center voltages) and, thus, define threshold voltages between the voltage ranges 311, 312, 313, 314. Optionally, in some implementations, the reading threshold voltages are located between adjacent voltage ranges 311, 312, 313, 314. In some implementations, reading threshold voltages VRA, VRB, and VRC are applied in the regions proximate to where adjacent voltage distributions 311a, 312a, 313a, 314a overlap, which are not necessarily proximate to the halfway regions between adjacent center voltages V11 311b, V01 312b, V00 313b and V10 314b. In some implementations, the reading threshold voltages are selected or adjusted to minimize error. During a read operation, one of the reading threshold voltages VRA, VRB and VRC is applied to determine the cell voltage using a comparison process. However, due to the various factors discussed above, the actual cell voltage, and/or the cell voltage received when reading the MLC, may be different from the respective center voltage V11 311b, V01 312b, V00 313b or V10 314b corresponding to the data value written into the cell. For example, the actual cell voltage may be in an altogether different voltage range, strongly indicating that the MLC is storing a different bit-tuple than was written to the MLC. More commonly, the actual cell voltage may be close to one of the read comparison voltages, making it difficult to determine with certainty which of two adjacent bit-tuples is stored by the MLC.
Errors in cell voltage, and/or the cell voltage received when reading the MLC, can occur during write operations, read operations, or due to “drift” of the cell voltage between the time data is written to the MLC and the time a read operation is performed to read the data stored in the MLC. For ease of discussion, sometimes errors in cell voltage, and/or the cell voltage received when reading the MLC, are collectively called “cell voltage drift.”
One way to reduce the impact of a cell voltage drifting from one voltage range to an adjacent voltage range is to gray-code the bit-tuples. Gray-coding the bit-tuples includes constraining the assignment of bit-tuples such that a respective bit-tuple of a particular voltage range is different from a respective bit-tuple of an adjacent voltage range by only one bit. For example, as shown in
Although the description of
Similarly, the tail portion of voltage distribution 413a to the right of a corresponding read threshold voltage (e.g., read threshold voltage VRC,
The voltage distributions 400b corresponding to bit-tuples “11,” “01,” “00,” “10,” respectively, are sometimes referred to as “E,” “A,” “B,” “C” levels or states, respectively. For example, in
In some embodiments, the voltage distributions E, A, B, C are related to verify voltages E-verify, A-verify, B-verify, C-verify, respectively. Adjusting a verify voltage shifts the corresponding voltage distribution accordingly. For example, as shown in
In some embodiments, the error control module (e.g., error control module 125,
In some embodiments, some of the operations (or alternatively, steps) of method 500 are performed at a host system (e.g., computer system 110) that is operatively coupled with the storage device, and other operations of method 500 are performed at the storage device. In some of these embodiments, method 500 is governed, at least in part, by instructions that are stored in a non-transitory computer readable storage medium and that are executed by one or more processors (e.g., hardware processors) of the host system (the one or more processors of the host system are not shown in
With reference to
The method begins, in some embodiments, in accordance with a predefined usage milestone occurring (502) in the storage device (e.g., storage device 120,
After a predefined usage milestone occurs, the storage device (e.g., storage device 120,
For example, in one embodiment, the first set of error counts includes both errorsum and errordiff values using a first set of voltage thresholds (e.g., with VA and VA+2dac,
Subset 1a:
errorsum=(F10A+F01A)+(F10C+F01C) {eq1a-1}
errordiff=(F10A−F01A)+(F10C−F01C) {eq1a-2}
where the error rates are determined using read voltage thresholds VA, VB, and VC.
Subset 1b:
errorsum′=(F10A′+F01A′)+(F10C+F01C) {eq1b-1}
errordiff′=(F10A′−F01A′)+(F10C−F01C) {eq1b-2}
where the error rates are determined using read threshold voltages VA+2dac, VB (or VB+2dac), and VC.
Further, in this example, the second set of error counts similarly includes errorsum and errordiff values using a second set of voltage thresholds (e.g., with VC and VC+2dac,
Subset 2b:
errorsum″=(F10A+F01A)+(F10C′+F01C′) {eq2b-1}
errordiff″=(F10A−F01A)+(F10C′−F01C′) {eq2b-2}
In some embodiments, the optimal read threshold voltages VA, VB, VC are the voltages at which the total error is at a local minimum. In some embodiments, the optimal read threshold voltages are at the crossover points (e.g., crossover points 420 and 422,
Next, the storage device (e.g., storage device 120,
where F10, F10′, F01, F01′ are intermediate values used as follows:
ΔF10A=F10′−F10=F10′−F10A, obtained by subtracting equation 3a from equation 3b; and {eq4a}
ΔF01A=F01′−F01=F01A′−F01A, obtained by subtracting equation 3c from equation 3d. {eq4b}
Thus, ΔF10A is the difference between the “1 to 0” error at VA and at VA+2dac, and ΔF01A is the difference between the “0 to 1” error at VA and at VA+2dac, as described above with respect to
Similarly, the error parameters ΔF01C and ΔF10C of the second set of error parameters can, in some embodiments, be computed as follows:
where F10″ and F01″, in addition to F10 and F01 as determined in equations 3a and 3c, are intermediate values used as follows:
ΔF01C=F01″−F01=F01C′−F01C, obtained by subtracting equation 3c from equation 5b; and {eq6a}
ΔF10C=F10″−F10=F10C′−F10C, obtained by subtracting equation 3a from equation 5a. {eq6b}
Thus, ΔF01C is the difference between the “0 to 1” error at VC and at VC+2dac, and ΔF10C is the difference between the “1 to 0” error at VC and at VC+2dac, as described above with respect to
Next, the storage device (e.g., storage device 120,
If one or more parameters of the first set of error parameters exceed the one or more corresponding parameters of the R1-scaled second set of error parameters (or equivalently, the ratio of the one or more parameters of the first set of error parameters to the one or more corresponding parameters of the second set of error parameters exceeds the first scaling factor) (508-Yes), the storage device (e.g., storage device 120,
If abs(ΔF10A)>R1*abs(ΔF01C) and abs(ΔF01A)>R1*abs(ΔF10C), then AVsignal=+1.
where abs(x) represents the absolute value of x.
If one or more parameters of the first set of error parameters do not exceed one or more corresponding parameters of the R1-scaled second set of error parameters (or equivalently, the aforementioned ratio does not exceed the first scaling factor) (508-No), the storage device (e.g., storage device 120,
If one or more parameters of the R2-scaled second set of error parameters exceed one or more corresponding parameters of the first set of error parameters (or equivalently, the ratio of the one or more parameters of the first set of error parameters to the one or more corresponding parameters of the second set of error parameters is less than the second scaling factor) (512-Yes), the storage device (e.g., storage device 120,
If abs(ΔF10A)<R2*abs(ΔF01C) and abs(ΔF01A)<R2*abs(ΔF10C), then AVsignal=−1.
If one or more parameters of the R2-scaled second set of error parameters do not exceed one or more corresponding parameters of the first set of error parameters (or equivalently, the aforementioned ratio is not less than the second scaling factor) (512-No), the method may repeat (502) in accordance with a subsequent predefined usage milestone.
In some embodiments, if the storage device (e.g., storage device 120,
AV
status
=AV
status
+AV
signal, or equivalently:
If AVsignal=+1, then AVstatus=AVstatus+1;
if AVsignal=−1, then AVstatus=AVstatus−1. {eq7}
While not shown in
Next, the storage device (e.g., storage device 120,
If the status counter (e.g., a status counter in verify status table 220,
If the status counter does not satisfy a respective limit of the set of one or more range limits (518-No), the method may repeat (502) in accordance with a subsequent predefined usage milestone.
In other embodiments, the storage device (e.g., storage device 120,
errorsum=(F10A+F01A)+(F10C+F01C), as determined using read voltage thresholds VA, VB, and VC; and {eq8a}
errorsum′=(F10A′+F01A′)+(F10C+F01C), as determined using read threshold voltages VA+2dac, VB (or VB+2dac), and VC. {eq8b}
Further, in this example, the second set of error counts similarly includes errorsum values using a second set of voltage thresholds (e.g., with VC and VC+2dac,
errorsum″=(F10A+F01A)+(F10C′+F01C′), as determined using read threshold voltages VA, VB (or VB+2dac), and VC+2dac. {eq9b}
Next, the storage device (e.g., storage device 120,
(ΔF10A+ΔF01A)=errorsum′−errorsum=(F10A′−F10A)+(F01A′−F01A)
(ΔF01C+ΔF10C)=errorsum″−errorsum=(F01C′−F01C)+(F10C′−F10C).
Next, the storage device (e.g., storage device 120,
If abs(ΔF10A+ΔF01A)>R1*abs(ΔF01C+ΔF10C), then AVsignal=+1.
If not (508-No), the storage device (e.g., storage device 120,
If abs(ΔF10A+ΔF01A)<R2*abs(ΔF01C+ΔF10C), then AVsignal=−1.
If not (512-No), the method may repeat (502) in accordance with a subsequent predefined usage milestone.
If the storage device (e.g., storage device 120,
Additional details concerning each of the processing steps for method 500, as well as details concerning additional processing steps, are presented below with reference to
With reference to
With reference to
In some embodiments, the plurality of error parameters are determined (604) in accordance with data read operations performed at predefined usage milestones with respect to portions of the non-volatile memory (e.g., selectable portion 131 of storage device 120,
The storage device (e.g., storage device 120,
The storage device (e.g., storage device 120,
In some embodiments, determining whether the verify trigger event has occurred includes: (1) updating (610) a status counter (e.g., a status counter in verify status table 220,
The storage device (e.g., storage device 120,
After the verify voltage has been adjusted (612), the storage device (e.g., storage device 120,
In some embodiments, the storage device (e.g., storage device 120,
In some embodiments, determining the plurality of error parameters includes: (1) determining (618) a first set of error counts for data read using a first set of voltage thresholds, (2) determining a second set of error counts for data read using a second set of voltage thresholds, and (3) computing a first set of one or more error parameters and a second set of one or more error parameters from the first and second sets of error counts, as explained above with reference to operations 504 and 506 of
In some embodiments, the first and second sets of error counts each include (620) a plurality of error sum values, as explained above with reference to operation 504 of
In some embodiments, the first and second sets of error counts further include (622) a plurality of error difference values, as explained above with reference to operation 504 of
In some embodiments, determining, in accordance with the plurality of error parameters, the verify adjustment signal includes: (1) applying (624) a first scaling factor to the second set of error parameters, (2) determining whether one or more parameters of the first set of error parameters exceeds one or more corresponding parameters of the scaled second set of error parameters, and (3) in accordance with a determination that the one or more parameters of the first set of error parameters exceeds the one or more corresponding parameters of the scaled second set of error parameters, setting the verify adjustment signal to a first adjustment value, as explained above with reference to operations 508 and 510 of
In some embodiments, determining, in accordance with the plurality of error parameters, the verify adjustment signal further includes: (1) applying (626) a second scaling factor to the second set of error parameters, (2) determining whether one or more parameters of the scaled second set of error parameters exceeds one or more corresponding parameters of the first set of error parameters, and (3) in accordance with a determination that the one or more parameters of the scaled second set of error parameters exceeds the one or more corresponding parameters of the first set of error parameters, setting the verify adjustment signal to a second adjustment value, as explained above with reference to operations 512 and 514 of
It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, which changing the meaning of the description, so long as all occurrences of the “first contact” are renamed consistently and all occurrences of the “second contact” are renamed consistently. The first contact and the second contact are both contacts, but they are not the same contact.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in accordance with a determination” or “in response to detecting,” that a stated condition precedent is true, depending on the context. Similarly, the phrase “if it is determined [that a stated condition precedent is true]” or “if [a stated condition precedent is true]” or “when [a stated condition precedent is true]” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.
The foregoing description, for purpose of explanation, has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The implementations were chosen and described in order to best explain principles of operation and practical applications, to thereby enable others skilled in the art.
This application claims priority to U.S. Provisional Patent Application No. 62/260,210, filed Nov. 25, 2015, which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62260210 | Nov 2015 | US |
