Method and system for controlling and monitoring an array of point-of-load regulators

Abstract
A power control system comprises a plurality of POL regulators, at least one serial data bus operatively connecting the plurality of POL regulators, and a system controller connected to the serial data bus and adapted to send and receive digital data to and from the plurality of POL regulators. The serial data bus further comprises a first data bus carrying programming and control information between the system controller and the plurality of POL regulators. The serial data bus may also include a second data bus carrying fault management information between the system controller and the plurality of POL regulators. The power control may also include a front-end regulator providing an intermediate voltage to the plurality of POL regulators on an intermediate voltage bus.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention


The present invention relates to power control systems, or more particularly, to a method and system to control and monitor an array of point-of-load regulators.


2. Description of Related Art


With the increasing complexity of electronic systems, it is common for an electronic system to require power provided at several different discrete voltage and current levels. For example, electronic systems may include discrete circuits that require voltages such as 3v, 5v, 9v, etc. Further, many of these circuits require a relatively low voltage (e.g., 1v), but with relatively high current (e.g., 100 A). It is undesirable to deliver relatively high current at low voltages over a relatively long distance through an electronic device for a number of reasons. First, the relatively long physical run of low voltage, high current lines consumes significant circuit board area and congests the routing of signal lines on the circuit board. Second, the impedance of the lines carrying the high current tends to dissipate a lot of power and complicate load regulation. Third, it is difficult to tailor the voltage/current characteristics to accommodate changes in load requirements.


In order to satisfy these power requirements, it is known to distribute an intermediate bus voltage throughout the electronic system, and include an individual point-of-load (“POL”) regulator, i.e., DC/DC converter, at the point of power consumption within the electronic system. Particularly, a POL regulator would be included with each respective electronic circuit to convert the intermediate bus voltage to the level required by the electronic circuit. An electronic system may include multiple POL regulators to convert the intermediate bus voltage into each of the multiple voltage levels. Ideally, the POL regulator would be physically located adjacent to the corresponding electronic circuit so as to minimize the length of the low voltage, high current lines through the electronic system. The intermediate bus voltage can be delivered to the multiple POL regulators using low current lines that minimize loss.


With this distributed approach, there is a need to coordinate the control and monitoring of the POL regulators of the power system. The POL regulators generally operate in conjunction with a power supply controller that activates, programs, and monitors the individual POL regulators. It is known in the art for the controller to use a multi-connection parallel bus to activate and program each POL regulator. For example, the parallel bus may communicate an enable/disable bit for turning each POL regulator on and off, and voltage identification (VID) code bits for programming the output voltage set-point of the POL regulators. The controller may further use additional connections to monitor the voltage/current that is delivered by each POL regulator so as to detect fault conditions of the POL regulators. A drawback with such a control system is that it adds complexity and size to the overall electronic system.


Thus, it would be advantageous to have a system and method for controlling and monitoring POL regulators within a distributed power system.


SUMMARY OF THE INVENTION

The present invention provides a system and method for controlling and monitoring POL regulators within a distributed power system.


In an embodiment of the invention, the power control system comprises a plurality of POL regulators, at least one serial data bus operatively connecting the plurality of POL regulators, and a system controller connected to the serial data bus and adapted to send and receive digital data to and from the plurality of POL regulators. The serial data bus further comprises a first data bus carrying programming, control and monitoring information between the system controller and the plurality of POL regulators. The serial data bus may also include a second data bus carrying fault management information between the system controller and the plurality of POL regulators. The power control may also include a front-end regulator providing an intermediate voltage to the plurality of POL regulators on an intermediate voltage bus.


The POL control system enables four different modes of operation. In the first operational mode, the POL regulators function independently in the absence of a system controller and without interaction with other POL regulators. In the second operational mode, the POL regulators interoperate for the purpose of current sharing or interleaving in the absence of a system controller. In the third operational mode, the POL regulators operate as an array in which the behavior of each POL regulator and the array as a whole are coordinated by a system controller. Lastly, the fourth operational mode includes both central control using the system controller and local control over certain functionality. This way, the POL regulators operate as an array coordinated by a system controller and also interoperate with each other to perform functions such as current sharing.


A more complete understanding of the method and system for controlling and monitoring a plurality of POL regulators will be afforded to those skilled in the art, as well as a realization of additional advantages and objects thereof, by a consideration of the following detailed description of the preferred embodiment. Reference will be made to the appended sheets of drawings, which will first be described briefly.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 depicts a prior art distributed power delivery system;



FIG. 2 depicts a prior art POL control system using a parallel control bus;



FIG. 3 depicts an exemplary POL control system constructed in accordance with an embodiment of the present invention;



FIG. 4 depicts an exemplary POL regulator of the POL control system; and



FIG. 5 depicts an exemplary system controller of the POL control system.





DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention provides a system and method for controlling and monitoring POL regulators within a distributed power system. In the detailed description that follows, like element numerals are used to describe like elements illustrated in one or more figures.


Referring first to FIG. 1, a prior art distributed power delivery system is shown. The prior art distributed power deliver system includes an AC/DC converter 12 that converts the available AC power into a primary DC power source, e.g., 48 volts. The primary DC power source is connected to a primary power bus that distributes DC power to plural electronic systems, such as printed circuit board 14. The bus may be further coupled to a battery 18 providing a back-up power source for the electronic systems connected to the primary power bus. When the AC/DC converter 12 is delivering DC power into the primary power bus, the battery 18 is maintained in a fully charged state. In the event of loss of AC power or fault with the AC/DC converter 12, the battery 18 will continue to deliver DC power to the primary power bus for a limited period of time defined by the capacity of the battery 18.


The printed circuit board 14 may further include a DC/DC converter that reduces the primary bus voltage to an intermediate voltage level, such as 5 or 12 volts. The intermediate voltage is then distributed over an intermediate power bus provided to plural circuits on the printed circuit board 14. Each circuit has an associated point-of-load (“POL”) regulator located closely thereby, such as POLs 22, 24, and 26. Each POL regulator converts the intermediate bus voltage to a low voltage, high current level demanded by the electronic circuit, such as 1.8 volts, 2.5 volts, and 3.3 volts provided by POLs 22, 24, and 26, respectively. It should be appreciated that the voltage levels described herein are entirely exemplary, and that other voltage levels could be selected to suit the particular needs of electronic circuits on the printed circuit board 14. By locating the POLs 22, 24, 26 close to their corresponding electronic circuits, the length of the low voltage, high current lines on the printed circuit board 14 are minimized. Moreover, the intermediate power bus can be adapted to carry relatively low current, thereby minimizing power loss due to the line impedance. But, this distributed power delivery system does not provide a way to monitor and control the performance of the POLs 22, 24, 26.



FIG. 2 illustrates a prior art DC/DC converter control system having a power supply controller 32 and a plurality of DC/DC converters 34, 36, 38, and 42. The DC/DC converters 34, 36, 38, and 42 are each connected to a power bus (as described above with respect to FIG. 1), which provides an input voltage. The DC/DC converters 34, 36, 38, and 42 each provide a low voltage, high current output that passes through respective sensing resistors 46, 52, 56, and 62 and respective switches 48, 54, 58, and 64. The controller 32 provides control signals to the DC/DC converters 34, 36, 38, and 42 via a plurality of six-bit parallel buses that each carry an enable/disable bit and five VID code bits. The VID code bits program the DC/DC converters for a desired output voltage/current level. The controller 32 also monitors the performance of the DC/DC converters 34, 36, 38, and 42 using the sensing resistors 46, 52, 56, and 62. Particularly, the controller 32 monitors the output voltage of each DC/DC converter by detecting the voltage at the output side of the sensing resistor, and monitors the output current through the sensing resistor by detecting the voltage across the sensing resistor. The voltage and current sensing for each DC/DC converter requires two separate lines, so eight separate lines are needed to sense the voltage and current condition of the exemplary four-converter system. Moreover, the controller 32 has a switch enable line connected to the gate terminals of switches 48, 54, 58, and 64, by which the controller 32 can shut off the output from any of the DC/DC controllers 34, 36, 38, and 42.


In an exemplary operation, the controller 32 provides control parameters (e.g., output voltage set-point) to the DC/DC converter 34 via the VID code portion of the six-bit parallel bus. The controller 32 then activates the DC/DC converter 34 via the enable/disable portion of the six-bit parallel bus. Once activated, the DC/DC converter 34 converts the power bus voltage (e.g., 48 volts) into a selected output voltage. The controller 32 then verifies that the output voltage is the desired voltage by measuring the voltage via the voltage monitoring line. If the output voltage is within an acceptable range, it is provided to the load (not shown) by activating the switch 48 via the switch enable line. The controller 32 can then continuously monitor the output voltage and the output current produced by the DC/DC converter 34 by measuring the output voltage via the voltage monitoring line and measuring the voltage drop across the sensing resistor (i.e., the voltage differential between the current monitoring line and the voltage monitoring line). If the controller 32 detects a fault condition of the DC/DC converter 34 (e.g., output voltage drops below a specific threshold), the controller 32 can disable and reset the DC/DC converter. The controller 32 communicates with the other DC/DC converters 36, 38, and 42 in the same manner.


A disadvantage with the control system of FIG. 2 is that it adds complexity and size to the overall electronic system by using a six-bit parallel bus to control each DC/DC converter and a separate three-line output connection to monitor the performance of each DC/DC converter. In other words, the controller 32 utilizes thirty-six separate connections in order to communicate with four DC/DC converters 34, 36, 38, and 42. As the complexity and power requirements of electronic systems increase, the number of connections to the controller will also increase in a linear manner.


Referring now to FIG. 3, a POL control system 100 is shown in accordance with an embodiment of the present invention. Specifically, the POL control system 100 includes a system controller 102, a front-end regulator 104, and a plurality of POL regulators 106, 108, 110, 112, and 114 arranged in an array. The POL regulators depicted herein include, but are not limited to, point-of-load regulators, power-on-load regulators, DC/DC converters, voltage regulators, and all other programmable voltage or current regulating devices generally known to those skilled in the art. An intra-device interface is provided between individual ones of the POL regulators to control specific interactions, such as current share or paralleling, e.g., current share interface (CS1) provided between POL0106 and POL1108, and CS2 provided between POL4112 and POLn 114. In the exemplary configuration shown in FIG. 3, POL0106 and POL1108 operate in parallel mode to produce output voltage VO1 with increased current capability, POL2110 produces output voltage VO2, and POL4112 and POLn 114 operate in parallel mode to produce output voltage VO3, though it should be appreciate that other combinations and other numbers of POL regulators could be advantageously utilized.


The front-end regulator 104 provides an intermediate voltage to the plurality of POL regulators over an intermediate voltage bus, and may simply comprise another POL regulator. The system controller 102 and front-end regulator 104 may be integrated together in a single unit, or may be provided as separate devices. Alternatively, the front-end regulator 104 may provide a plurality of intermediate voltages to the POL regulators over a plurality of intermediate voltage buses. The system controller 102 may draw its power from the intermediate voltage bus.


The system controller 102 communicates with the plurality of POL regulators by writing and/or reading digital data (either synchronously or asynchronous) via a uni-directional or bi-directional serial bus, illustrated in FIG. 3 as the synch/data bus. The synch/data bus may comprise a two-wire serial bus (e.g., I2C) that allows data to be transmitted asynchronously or a single-wire serial bus that allows data to be transmitted synchronously (i.e., synchronized to a clock signal). In order to address any specific POL in the array, each POL is identified with a unique address, which may be hardwired into the POL or set by other methods. The system controller 102 also communicates with the plurality of POL regulators for fault management over a second unidirectional or bi-directional serial bus, illustrated in FIG. 3 as the OK/fault bus. By grouping plural POL regulators together by connecting them to a common OK/fault bus allows the POL regulators have the same behavior in the case of a fault condition. Also, the system controller 102 communicates with a user system via a user interface bus for programming, setting, and monitoring of the POL control system 10. Lastly, the system controller 102 communicates with the front-end regulator 104 over a separate line to disable operation of the front-end regulator.


An exemplary POL regulator 106 of the POL control system 10 is illustrated in greater detail in FIG. 4. The other POL regulators of FIG. 3 have substantially identical configuration. The POL regulator 106 includes a power conversion circuit 142, a serial interface 144, a POL controller 146, default configuration memory 148, and hardwired settings interface 150. The power conversion circuit 142 transforms an input voltage (Vi) to the desired output voltage (VO) according to settings received through the serial interface 144, the hardwired settings 150 or default settings. The power conversion circuit 142 may also include monitoring sensors for output voltage, current, temperature and other parameters that are used for local control and also communicated back to the system controller through the serial interface 144. The power conversion circuit 142 may also generate a Power Good (PG) output signal for stand-alone applications in order to provide a simplified monitoring function. The serial interface 144 receives and sends commands and messages to the system controller 102 via the synch/data and OK/fault serial buses. The default configuration memory 148 stores the default configuration for the POL regulator 106 in cases where no programming signals are received through the serial interface 144 or hardwired settings interface 150. The default configuration is selected such that the POL regulator 106 will operate in a “safe” condition in the absence of programming signals.


The hardwired settings interface 150 communicates with external connections to program the POL regulator without using the serial interface 144. The hardwired settings interface 150 may include as inputs the address setting (Addr) of the POL to alter or set some of the settings as a function of the address (i.e., the identifier or the POL), e.g., phase displacement, enable/disable bit (En), trim, and VID code bits. Further, the address identifies the POL regulator during communication operations through the serial interface 144. The trim input allows the connection of one or more external resistors to define an output voltage level for the POL regulator. Similarly, the VID code bits can be used to program the POL regulator for a desired output voltage/current level. The enable/disable bit allows the POL regulator to be turned on/off by toggling a digital high/low signal.


The POL controller 146 receives and prioritizes the settings of the POL regulator. If no settings information is received via either the hardwired settings interface 150 or the serial interface 144, the POL controller 146 accesses the parameters stored in the default configuration memory 148. Alternatively, if settings information is received via the hardwired settings interface 150, then the POL controller 146 will apply those parameters. Thus, the default settings apply to all of the parameters that cannot be or are not set through hard wiring. The settings received by the hardwired settings interface 150 can be overwritten by information received via the serial interface 144. The POL regulator can therefore operate in a stand-alone mode, a fully programmable mode, or a combination thereof. This programming flexibility enables a plurality of different power applications to be satisfied with a single generic POL regulator, thereby reducing the cost and simplifying the manufacture of POL regulators.


An exemplary system controller 102 of the POL control system 100 is illustrated in FIG. 5. The system controller 102 includes a user interface 122, a POL interface 124, a controller 126, and a memory 128. The user interface 122 sends and receives messages to/from the user via the user interface bus. The user interface bus may be provided by a serial or parallel bi-directional interface using standard interface protocols, e.g., an I2C interface. User information such as monitoring values or new system settings would be transmitted through the user interface 122. The POL interface 124 transforms data to/from the POL regulators via the synch/data and OK/fault serial buses. The POL interface 124 communicates over the synch/data serial bus to transmit setting data and receive monitoring data, and communicates over the OK/fault serial bus to receive interrupt signals indicating a fault condition in at least one of the connected POL regulators. The memory 128 comprises a non-volatile memory storage device used to store the system set-up parameters (e.g., output voltage, current limitation set-point, timing data, etc.) for the POL regulators connected to the system controller 102. Optionally, a secondary, external memory 132 may also be connected to the user interface 122 to provide increased memory capacity for monitoring data or setting data.


The controller 126 is operably connected to the user interface 122, the POL interface 124, and the memory 128. The controller 126 has an external port for communication a disable signal (FE DIS) to the front-end regulator 104. At start-up of the POL control system 100, the controller 126 reads from the internal memory 128 (and/or the external memory 132) the system settings and programs the POL regulators accordingly via the POL interface 124. Each of the POL regulators is then set up and started in a prescribed manner based on the system programming. During normal operation, the controller 126 decodes and executes any command or message coming from the user or the POL regulators. The controller 126 monitors the performance of the POL regulators and reports this information back to the user through the user interface 122. The POL regulators may also be programmed by the user through the controller 126 to execute specific, autonomous reactions to faults, such as over current or over voltage conditions. Alternatively, the POL regulators may be programmed to only report fault conditions to the system controller 102, which will then determine the appropriate corrective action in accordance with predefined settings, e.g., shut down the front-end regulator via the FE DIS control line.


A monitoring block 130 may optionally be provided to monitor the state of one or more voltage or current levels of other power systems not operably connected to the controller 102 via the synch/data or OK/fault buses. The monitoring block 130 may provide this information to the controller 126 for reporting to the user through the user interface in the same manner as other information concerning the POL control system 100. This way, the POL control system 100 can provide some backward compatibility with power systems that are already present in an electronic system.


The POL control system 100 enables four different modes of operation. In the first operational mode, the POL regulators function independently in the absence of a system controller and without interaction with other POL regulators. The POL regulators each include local feedback and control systems to regulate their own performance as well as control interfaces to enable local programming. The POL regulators further include default settings in which they can revert to in the absence of local programming or data from the system controller. In other words, each of the POL regulators can operate as a standalone device without the need for a system controller or interactions with another POL regulator.


In the second operational mode, the POL regulators interoperate for the purpose of current sharing or interleaving in the absence of a system controller. The POL regulators communicate with each other over the current share interface. The synch/data line may be used to communicate synchronization information to permit phase interleaving of the POL regulators, in which the phase is programmed locally by entering an address through hardwired connections.


In the third operational mode, the POL regulators operate as an array in which the behavior of each POL regulator and the array as a whole are coordinated by a system controller. The system controller programs the operation of each of the POL regulators over the synch/data serial bus, and thereby overrides the predetermined settings of the POL regulators. The synch/data serial bus is further used to communicate synchronization information to permit synchronization and interleaving of the POL regulators. This operational mode would not include interdevice communications over the current share interface.


Lastly, the fourth operational mode includes both central control using the system controller and local control over certain functionality. This way, the POL regulators operate as an array coordinated by a system controller and also interoperate with each other to perform functions such as current sharing.


Having thus described a preferred embodiment of a method and system to control and monitor an array of DC/DC power converters, it should be apparent to those skilled in the art that certain advantages of the system have been achieved. It should also be appreciated that various modifications, adaptations, and alternative embodiments thereof may be made within the scope and spirit of the present invention. The invention is further defined by the following claims.

Claims
  • 1. A power delivery management system, the system comprising: a plurality of digital power regulating devices, wherein each of the plurality of digital power regulating devices provides a plurality of functions, wherein each of the plurality of digital power regulating devices is operable to provide power to one or more loads; anda control and communication bus, wherein each one of the plurality of digital power regulating devices is coupled to the control and communication bus;wherein each one of the plurality of digital power regulating devices includes a controller operable to control the functions of a corresponding one of the plurality of digital power regulating devices; andwherein the plurality of digital power regulating devices are operable to communicate with each other over the control and communication bus to exchange information to coordinate their functions.
  • 2. The system of claim 1, wherein at least one of the plurality of digital power regulating devices is also adapted to coordinate and/or control the functions of one or more other ones of the plurality of digital power regulating devices.
  • 3. The system of claim 2, wherein the other ones of the plurality of digital power regulating devices are adapted to provide status information over the control and communication bus to the at least one of the plurality of digital power regulating devices.
  • 4. The system of claim 1, wherein the plurality of functions comprise one or more power delivery functions; wherein each controller is operable to control the one or more power delivery functions of a corresponding one of the digital power regulating devices.
  • 5. The system of claim 1, wherein at least a subset of the plurality of digital power regulating devices each comprise the same functions.
  • 6. The system of claim 1, wherein one or more of the plurality of digital power regulating devices comprises a voltage converter unit.
  • 7. The system of claim 6, wherein the voltage converter unit comprises a DC (direct current) to DC voltage converter.
  • 8. The system of claim 1, wherein the control and communication bus is a digital bus.
  • 9. The system of claim 8, wherein the control and communication bus comprises one or more digital communication paths, wherein each one of the one or more digital communication paths comprises one or more dedicated signals.
  • 10. The system of claim 1, wherein each individual one of the plurality of digital power regulating devices is operable to be programmed and/or configured across the control and communication bus.
  • 11. The system of claim 1, wherein two or more of the plurality of digital power regulating devices are operable to be grouped together in a current sharing configuration.
  • 12. The system of claim 1, wherein each one of the plurality of digital power regulating devices is operable to provide feedback data to all other ones of the plurality of digital power regulating devices.
  • 13. The system of claim 12, wherein the feedback data comprises real-time data.
  • 14. The system of claim 1, wherein the functions of the plurality of digital power regulating devices comprise at least one of: phase displacement;current sharing; andvoltage programming and voltage tracking.
  • 15. The system of claim 1 further comprising at least one master control device coupled to the control and communication bus, wherein the at least one master control device is operable to centrally control the plurality of digital power regulating devices to implement advanced features.
  • 16. The system of claim 15, wherein the advanced features comprise reconfiguring and/or reprogramming one or more of the plurality of digital power regulating devices.
  • 17. The system of claim 1, wherein the control and communication bus is a serial bus.
  • 18. The system of claim 15, wherein the master control device is adapted to control the plurality of digital power regulating devices over the control and communication bus.
  • 19. The system of claim 18, wherein the control and communication bus is a serial digital control and communication bus.
  • 20. The system of claim 18, wherein said communicating with the plurality of digital power regulating devices comprises each one of the plurality of digital power regulating devices providing feedback data to the master control device.
  • 21. The system of claim 18, wherein the master control device comprises a controller operable to execute functions corresponding to each of the plurality of digital power regulating devices to control the plurality of digital power regulating devices.
  • 22. The system of claim 18, wherein the plurality of digital power regulating devices provide status information over the control and communication bus to the master control device.
  • 23. A digital power regulating device for use in a power delivery management system, the digital power regulating device including a power delivery circuit adapted to deliver regulated power to one or more loads, the digital power regulating device further comprising a controller operable to provide a plurality of functions pertaining to control over the power delivery circuit, the controller being further operable to communicate with other like digital power regulating devices over a control and communication bus to exchange information and to coordinate their functions.
  • 24. The digital power regulating device of claim 23, wherein the controller is also adapted to coordinate and/or control the functions of one or more of the other like digital power regulating devices.
  • 25. The digital power regulating device of claim 23, wherein the controller is also adapted to receive status information from one or more of the other like digital power regulating devices over the control and communication bus.
  • 26. The digital power regulating device of claim 23, wherein the controller is also adapted to send status information to one or more of the other like digital power regulating devices over the control and communication bus.
  • 27. The digital power regulating device of claim 23, wherein the plurality of functions comprise at least one power delivery function.
  • 28. The digital power regulating device of claim 23, wherein the power delivery circuit comprises a voltage converter unit.
  • 29. The digital power regulating device of claim 28, wherein the voltage converter unit comprises a DC (direct current) to DC voltage converter.
  • 30. The digital power regulating device of claim 23, wherein the controller is operable to be programmed and/or configured across the control and communication bus.
  • 31. The digital power regulating device of claim 23, wherein the controller is operable to couple the digital power regulating device with at least one other like digital power regulating device in a current sharing configuration.
  • 32. The digital power regulating device of claim 23, wherein the controller is operable to provide feedback data to at least one other like digital power regulating device.
  • 33. The digital power regulating device of claim 32, wherein the feedback data comprises real-time data.
  • 34. The digital power regulating device of claim 23, wherein the plurality of functions comprise at least one of: phase displacement;current sharing; andvoltage programming and voltage tracking.
  • 35. The digital power regulating device of claim 23, wherein the controller is operable to serve as a master controller to centrally control the other like digital power regulating devices over the control and communication bus.
  • 36. The digital power regulating device of claim 35, wherein the controller is operable to control reconfiguring and/or reprogramming of at least one of the other like digital power regulating devices.
  • 37. The digital power regulating device of claim 35, wherein the controller is further operable to receive feedback data from at least one of the other like digital power regulating devices.
  • 38. A method for operating a digital power regulating device within a power delivery management system, the digital power regulating device being operably coupled together by a control and communication bus, the method comprising: controlling functions of the digital power regulating device to provide power to one or more loads; andcommunicating with at least one other digital power regulating device over the control and communication bus to exchange information to coordinate their respective functions.
  • 39. The method of claim 38, further comprising controlling the functions of the at least one other digital power regulating device.
  • 40. The method of claim 38, further comprising providing status information over the control and communication bus to the at least one other digital power regulating device.
  • 41. The method of claim 38, further comprising receiving status information over the control and communication bus from the at least one other digital power regulating device.
  • 42. The method of claim 38, wherein the controlling functions comprise controlling one or more power delivery functions.
  • 43. The method of claim 38, further comprising programming the digital power regulating device using information received across the control and communication bus.
  • 44. The method of claim 38, further comprising grouping at least two of the digital power regulating devices in a current sharing configuration.
  • 45. The method of claim 38, further comprising providing feedback data to at least one other digital power regulating device.
  • 46. The method of claim 45, wherein the feedback data comprises real-time data.
  • 47. The method of claim 38, wherein the controlling functions further comprises controlling at least one of: phase displacement;current sharing; andvoltage programming and voltage tracking.
  • 48. The method of claim 38, further comprising centrally controlling plural digital power regulating devices.
  • 49. The method of claim 48, further comprising reconfiguring and/or reprogramming at least one of the plural digital power regulating devices.
RELATED APPLICATION DATA

This application claims priority as a continuation-in-part pursuant to 35 U.S.C. §120 of patent application Ser. No. 11/354,550, filed Feb. 14, 2006 now U.S. Pat. No. 7,266,709, which was in turn a continuation-in-part of patent application Ser. No. 10/326,222, filed Dec. 21, 2002, now issued as U.S. Pat. No. 7,000,125.

US Referenced Citations (233)
Number Name Date Kind
3660672 Berger et al. May 1972 A
4021729 Hudson May 1977 A
4147171 Greene et al. Apr 1979 A
4194147 Payne et al. Mar 1980 A
4204249 Dye et al. May 1980 A
4328429 Kublick et al. May 1982 A
4335445 Nercessian Jun 1982 A
4350943 Pritchard Sep 1982 A
4451773 Papathomas et al. May 1984 A
4538073 Freige et al. Aug 1985 A
4538101 Shimpo et al. Aug 1985 A
4607330 McMurray et al. Aug 1986 A
4616142 Upadhyay et al. Oct 1986 A
4622627 Rodriguez et al. Nov 1986 A
4630187 Henze Dec 1986 A
4654769 Middlebrook Mar 1987 A
4677566 Whittaker et al. Jun 1987 A
4761725 Henze Aug 1988 A
4940930 Detweiler Jul 1990 A
4988942 Ekstrand Jan 1991 A
5004972 Roth Apr 1991 A
5053920 Staffiere et al. Oct 1991 A
5073848 Steigerwald et al. Dec 1991 A
5079498 Cleasby et al. Jan 1992 A
5117430 Berglund May 1992 A
5168208 Schultz et al. Dec 1992 A
5229699 Chu et al. Jul 1993 A
5270904 Gulczynski Dec 1993 A
5272614 Brunk et al. Dec 1993 A
5287055 Cini et al. Feb 1994 A
5325062 Bachand et al. Jun 1994 A
5349523 Inou et al. Sep 1994 A
5377090 Steigerwald Dec 1994 A
5398029 Toyama et al. Mar 1995 A
5426425 Conrad et al. Jun 1995 A
5440520 Schutz et al. Aug 1995 A
5481140 Maruyama et al. Jan 1996 A
5489904 Hadidi Feb 1996 A
5508606 Ryczek Apr 1996 A
5532577 Doluca Jul 1996 A
5610826 Whetsel Mar 1997 A
5627460 Bazinet et al. May 1997 A
5631550 Castro et al. May 1997 A
5646509 Berglund et al. Jul 1997 A
5675480 Stanford Oct 1997 A
5684686 Reddy Nov 1997 A
5727208 Brown Mar 1998 A
5752047 Darty et al. May 1998 A
5815018 Soborski Sep 1998 A
5847950 Bhagwat Dec 1998 A
5870296 Schaffer Feb 1999 A
5872984 Berglund et al. Feb 1999 A
5874912 Hasegawn Feb 1999 A
5883797 Amaro et al. Mar 1999 A
5889392 Moore et al. Mar 1999 A
5892933 Voltz Apr 1999 A
5905370 Bryson May 1999 A
5917719 Hoffman et al. Jun 1999 A
5929618 Boylan et al. Jul 1999 A
5929620 Dobkin et al. Jul 1999 A
5935252 Berglund et al. Aug 1999 A
5943227 Bryson et al. Aug 1999 A
5946495 Scholhamer et al. Aug 1999 A
5990669 Brown Nov 1999 A
5994885 Wilcox et al. Nov 1999 A
6005377 Chen et al. Dec 1999 A
6021059 Kennedy Feb 2000 A
6055163 Wagner et al. Apr 2000 A
6057607 Rader, III et al. May 2000 A
6079026 Berglund et al. Jun 2000 A
6100676 Burstein et al. Aug 2000 A
6111396 Line et al. Aug 2000 A
6115441 Douglass et al. Sep 2000 A
6121760 Marshall et al. Sep 2000 A
6136143 Winter et al. Oct 2000 A
6137280 Ackermann Oct 2000 A
6150803 Varga Nov 2000 A
6157093 Giannopoulos et al. Dec 2000 A
6157182 Tanaka et al. Dec 2000 A
6160697 Edel Dec 2000 A
6163143 Shimamori Dec 2000 A
6163178 Stark et al. Dec 2000 A
6170062 Henrie Jan 2001 B1
6177787 Hobrecht Jan 2001 B1
6181029 Berglund et al. Jan 2001 B1
6191566 Petricek et al. Feb 2001 B1
6194856 Kobayashi et al. Feb 2001 B1
6194883 Shimamori Feb 2001 B1
6198261 Schultz et al. Mar 2001 B1
6199130 Berglund et al. Mar 2001 B1
6208127 Doluca Mar 2001 B1
6211579 Blair Apr 2001 B1
6246219 Lynch et al. Jun 2001 B1
6249111 Nguyen Jun 2001 B1
6262900 Suntio Jul 2001 B1
6288595 Hirakata et al. Sep 2001 B1
6291975 Snodgrass Sep 2001 B1
6294954 Melanson Sep 2001 B1
6304066 Wilcox et al. Oct 2001 B1
6304823 Smit et al. Oct 2001 B1
6320768 Pham et al. Nov 2001 B1
6351108 Burnstein et al. Feb 2002 B1
6355990 Mitchell Mar 2002 B1
6366069 Nguyen et al. Apr 2002 B1
6370047 Mallory Apr 2002 B1
6373334 Melanson Apr 2002 B1
6385024 Olson May 2002 B1
6392577 Swanson et al. May 2002 B1
6396169 Voegli et al. May 2002 B1
6396250 Bridge May 2002 B1
6400127 Giannopoulos Jun 2002 B1
6411071 Schultz Jun 2002 B1
6411072 Feldman Jun 2002 B1
6414864 Hoshi Jul 2002 B1
6421259 Brooks et al. Jul 2002 B1
6429630 Pohlman et al. Aug 2002 B2
6448745 Killat Sep 2002 B1
6448746 Carlson Sep 2002 B1
6456044 Darmawaskita Sep 2002 B1
6465909 Soo et al. Oct 2002 B1
6465993 Clarkin et al. Oct 2002 B1
6469478 Curtin Oct 2002 B1
6469484 L'Hermite et al. Oct 2002 B2
6476589 Umminger et al. Nov 2002 B2
6556158 Steensgaard-Madsen Apr 2003 B2
6559684 Goodfellow May 2003 B2
6563294 Duffy et al. May 2003 B2
6583608 Zafarana et al. Jun 2003 B2
6590369 Burstein et al. Jul 2003 B2
6608402 Soo et al. Aug 2003 B2
6614612 Menegoli et al. Sep 2003 B1
6621259 Jones et al. Sep 2003 B2
6665525 Dent et al. Dec 2003 B2
6683494 Stanley Jan 2004 B2
6686831 Cook Feb 2004 B2
6693811 Bowman et al. Feb 2004 B1
6717389 Johnson Apr 2004 B1
6731023 Rothleitner et al. May 2004 B2
6744243 Daniels et al. Jun 2004 B2
6771052 Ostojic Aug 2004 B2
6778414 Chang et al. Aug 2004 B2
6788033 Vinciarelli Sep 2004 B2
6788035 Bassett et al. Sep 2004 B2
6791298 Shenai et al. Sep 2004 B2
6791302 Tang et al. Sep 2004 B2
6791368 Tzeng et al. Sep 2004 B2
6795009 Duffy et al. Sep 2004 B2
6801027 Hann et al. Oct 2004 B2
6807070 Ribarich Oct 2004 B2
6816758 Maxwell, Jr. et al. Nov 2004 B2
6819537 Pohlman et al. Nov 2004 B2
6825644 Kernahan et al. Nov 2004 B2
6828765 Schultz et al. Dec 2004 B1
6829547 Law et al. Dec 2004 B2
6833691 Chapuis Dec 2004 B2
6850046 Chapuis Feb 2005 B2
6850049 Kono Feb 2005 B2
6850426 Kojori et al. Feb 2005 B2
6853169 Burstein et al. Feb 2005 B2
6853174 Inn Feb 2005 B1
6888339 Travaglini et al. May 2005 B1
6903949 Ribarich Jun 2005 B2
6911808 Shimamori Jun 2005 B1
6915440 Berglund et al. Jul 2005 B2
6917186 Klippel et al. Jul 2005 B2
6928560 Fell, III et al. Aug 2005 B1
6933709 Chapuis Aug 2005 B2
6933711 Sutardja et al. Aug 2005 B2
6936999 Chapuis Aug 2005 B2
6947273 Bassett et al. Sep 2005 B2
6949916 Chapuis Sep 2005 B2
6963190 Asanuma et al. Nov 2005 B2
6965220 Kernahan et al. Nov 2005 B2
6965502 Duffy et al. Nov 2005 B2
6975494 Tang et al. Dec 2005 B2
6975785 Ghandi Dec 2005 B2
6977492 Sutardja et al. Dec 2005 B2
7000125 Chapuis et al. Feb 2006 B2
7000315 Chua et al. Feb 2006 B2
7002265 Potega Feb 2006 B2
7007176 Goodfellow et al. Feb 2006 B2
7023192 Sutardja et al. Apr 2006 B2
7023672 Goodfellow et al. Apr 2006 B2
7047110 Lenz et al. May 2006 B2
7049798 Chapuis et al. May 2006 B2
7068021 Chapuis Jun 2006 B2
7080265 Thaker et al. Jul 2006 B2
7141956 Chapuis Nov 2006 B2
7190754 Chang et al. Mar 2007 B1
7266709 Chapuis et al. Sep 2007 B2
7315157 Chapuis Jan 2008 B2
7315160 Fosler Jan 2008 B2
7359643 Aronson et al. Apr 2008 B2
7394445 Chapuis et al. Jul 2008 B2
7584371 Zhang Sep 2009 B2
20010052862 Roelofs Dec 2001 A1
20020070718 Rose Jun 2002 A1
20020073347 Zafarana et al. Jun 2002 A1
20020075710 Lin Jun 2002 A1
20020104031 Tomlinson et al. Aug 2002 A1
20020105227 Nerone et al. Aug 2002 A1
20020144163 Goodfellow et al. Oct 2002 A1
20030006650 Tang et al. Jan 2003 A1
20030067404 Ruha et al. Apr 2003 A1
20030122429 Zhang Jul 2003 A1
20030137912 Ogura Jul 2003 A1
20030142513 Vinciarelli Jul 2003 A1
20030201761 Harris Oct 2003 A1
20040080044 Moriyama et al. Apr 2004 A1
20040093533 Chapuis et al. May 2004 A1
20040123164 Chapuis et al. Jun 2004 A1
20040123167 Chapuis Jun 2004 A1
20040174147 Vinciarelli Sep 2004 A1
20040178780 Chapuis Sep 2004 A1
20040189271 Hanson et al. Sep 2004 A1
20040201279 Templeton Oct 2004 A1
20040225811 Fosler Nov 2004 A1
20040246754 Chapuis Dec 2004 A1
20050093594 Kim et al. May 2005 A1
20050117376 Wilson Jun 2005 A1
20050146312 Kenny et al. Jul 2005 A1
20050200344 Chapuis Sep 2005 A1
20050289373 Chapuis et al. Dec 2005 A1
20060022656 Leung et al. Feb 2006 A1
20060085656 Betts-LaCroix Apr 2006 A1
20060149396 Templeton Jul 2006 A1
20060174145 Chapuis et al. Aug 2006 A1
20060244570 Leung et al. Nov 2006 A1
20060250120 King Nov 2006 A1
20060276914 Templeton Dec 2006 A9
20070114985 Latham et al. May 2007 A1
20080074373 Chapuis et al. Mar 2008 A1
20080238208 Potter et al. Oct 2008 A1
Foreign Referenced Citations (22)
Number Date Country
2521825 Nov 2002 CN
0255258 Feb 1988 EP
0315366 May 1989 EP
0401562 Dec 1990 EP
0660487 Jun 1995 EP
0875994 Nov 1998 EP
0877468 Nov 1998 EP
0997825 May 2000 EP
2377094 Dec 2002 GB
60-244111 Dec 1985 JP
1185329 Mar 1999 JP
11-289754 Oct 1999 JP
200284495 Aug 2002 KR
1359874 Dec 1985 RU
1814177 May 1993 RU
WO9319415 Sep 1993 WO
WO0122585 Mar 2001 WO
WO0231943 Apr 2002 WO
WO0231951 Apr 2002 WO
WO0250690 Jun 2002 WO
WO02063688 Aug 2002 WO
WO 03030369 Apr 2003 WO
Related Publications (1)
Number Date Country
20070240000 A1 Oct 2007 US
Continuation in Parts (2)
Number Date Country
Parent 11354550 Feb 2006 US
Child 11696422 US
Parent 10326222 Dec 2002 US
Child 11354550 US