Patent Application
20100225243
In general, the present invention relates to image devices, and more specifically to methods and systems for controlling the power supplied to the pixels of an image device.
In a digital imager, pixel power is required to perform operations, such as resetting a floating diffusion and translating charge on the floating diffusion to an output pixel voltage. The pixel power, however, may induce unwanted behavior within the digital imager. Specifically, the digital imager may suffer from effects of hot pixels and dark current.
Hot pixels are generally caused by pixels with higher than normal rates of charge leakage. Hot pixels show up as bright points in an image. Dark currents, on the other hand, are charges accumulated by a pixel even though the pixel is not exposed to light. Thus, dark currents may be seen as off-set noise.
Two contributing causes of hot pixels and dark currents are high floating diffusion voltages and fringing field effects in a drain terminal of a reset transistor. A high floating diffusion voltage is maintained by global anti-blooming functions, since the reset signal is high for unselected rows. A fringing field effect of the drain terminal in the reset transistor is caused by a voltage potential being supplied to the power node of a pixel. The voltage potential on the power node lowers the p-n potential barrier, thus causing charge leakage.
Another unwanted result caused by voltage being supplied to the power node is standby leakage current. Specifically, standby leakage current is dominated by the p-n junction leakage current between the N-epitaxial layer and the P-substrate underneath it, as well as the buried P-layer above it. In addition, leakage current is present between the N+ diffusion areas within the pixel array and the P-epitaxial layer. Such leakage current is particularly undesirable in low-power applications, such as portable devices utilizing image sensors.
It would be an advantage to have a system and method for switching the pixel power. It would also be advantageous if the system and method could provide a high impedance mode.
In one embodiment, the present invention includes a switch for coupling a power supply to a power node of a pixel. In general, the switch controls the pixel power by applying an operating potential to the power node, applying a ground potential to the power node or applying a low potential to the power node. The switch also controls the pixel power by isolating the power node in a high impedance state.
Referring first to
When conducting, the RST transistor couples vaapix_int to FD. As the FD voltage increases, the depletion region surrounding the n-minus layer of the PD expands and may contact the shallow trench isolation (STI). The STI which includes impurities and crystalline lattice defects, may inject undesired non-photo-generated carriers into the PD causing hot pixels and dark current. One solution to reduce this effect, is switching off or reducing the FD voltage.
The N-type diffusion areas within the pixel array are either directly or indirectly connected to vaapix_int and the P-epitaxial layer. One example of an N-type diffusion area that is indirectly connected to vaapix_int is the n-minus layer of the photodiode. This occurs during the anti-bloom mode, when the RST and TX transistors are turned on. One method to reduce this leakage charge is by isolating vaapix int along with the n+ guard ring in a high impedance state. This method and others are described below.
Transistors 200-208 are controlled by various signals. The vaapix_switch signal controls the inverter structure of transistors 202 and 204 to couple vaapix_int to the external vaapix power supply, thereby providing a pull-up network (PUN). The vaapix_switch signal may also control switch module 250 to couple vaapix_int to the vaapix_lo_vref or AGND node, thereby providing a pull-down network (PDN).
The vaapix_int node may be pulled down by the PDN. During pull-down, transistor 204 couples vaapix_int to vaapix_lo_int. The voltage potential of the PDN is controlled by vaapix_lo_to_ground_bar and its complement vaapix_lo_to_gnd. These two signals enable transistors 206 and 208 to perform as a multiplexer. Specifically, transistors 206 and 208 couple vaapix_lo_vref or AGND to vaapix_lo_int. At the same time, transistor 202 de-couples vaapix_int from vaapix ensuring that the PUN is disabled during the PDN operation.
The vaapix_int node may also be pulled up to vaapix by the PUN. During pull-up, transistors 200 and 202 couple vaapix_int to vaapix. At the same time, transistor 204 de-couples vaapix_int from vaapix_lo_int ensuring that the PDN is disabled during the PUN operation.
In one embodiment, an optional high impedance mode is also provided by switching module 250. Specifically, transistor 200 and node vaapix_ring_int are included as optional high impedance circuit 210. In circuit 210, vaapix_ring_int is coupled to the n+ guard ring of the pixel and transistor 200 couples vaapix_ring_int to vaapix. When vaapix_switch is in a low state and vaapix_ring_switch_bar is in a high state, transistor 200 is turned off and transistor 202 is turned on. Thus, both vaapix_ring_int and vaapix_int are isolated from vaapix (PUN) and vaapix_lo_int (PDN).
In one embodiment, the signals that control the column module shown in
In the PUN operation, vaapix_switch and vaapix_ring_switch_bar are generated by circuits 336 and 338 in
In the PDN operation, vaapix switch and vaapix_lo_to_gnd are generated by circuits 336 and 340 in
Furthermore, the voltage potential of the PDN operation is selected by vaapix_lo_to_gnd. In one example, if vaapix_lo_to_gnd is in a high state, then vaapix_int is coupled to ground potential AGND. In another example, if vaapix_lo_to_gnd is in a low state, then vaapix_int is coupled to low reference potential vaapix_lo_vref. In general, transistors 206 and 208 are controlled as a multiplexer for the dual PDN operation which couples vaapix_int to either a low reference potential or a ground potential.
In the high impedance mode of switch 250, vaapix_switch and vaapix_ring_int are generated by circuits 336 and 338 in
In another embodiment, controlling the power applied to the pixels is performed by switching circuit 650 as shown in
The analog/digital switching module as shown in
In this embodiment, switch 650 comprises current sources 630 and 632, PMOS level shifters 600 and 602, switches S1 and S2, capacitor C, op-amp 604, NMOS transistor 634 and variable resistor R. Switch 650 further comprises a current mirror 660 which includes transistors 606 and 608 that are controlled between analog and digital mode by transistor S3, and a current mirror 670 which includes transistors 620 and 622 that are controlled between analog and digital mode by transistor S5.
Switch 650 has a PDN comprising an enable transistor 610 for enabling transistors 616(1)-616(N). Specifically, transistors 616(1)-616(N) are coupled to the vaapix_int node for each pixel column in the imager. The PDN further comprises transistor 612 which is the input leg to a PDN current mirror, and transistors 614(1)-614(N) which are the output legs of the PDN current mirror. Transistors 614(1)-614(N) are coupled to ground potential AGND or a low potential vaapix_lo_vref. In general, the ratio between the sizing of transistors 612 and 614(1)-614(N) may be substantially larger than 1 to ensure fast settling of their shared gate terminal which is a global net across the column module horizontally.
Switch circuit 650 in
In analog mode, the switching circuit is able to perform both the PUN and PDN operations with or without rising and falling ramp currents. In the analog mode, digital switches S3, S4, S5 and S6 are turned off. Thus, current mirrors 660, 670, PUN and PDN to operate normally.
In the PDN operation shown in the timing diagram of
The timing diagram of
In general, the PUN operation works similarly to the above described PDN operation. Thus, during the PUN operation, transistor 606 mirrors the current flowing through resistor R to transistors 618 and 620. Then, transistor 620 mirrors the current to transistors 622, 636 and 624. The current flowing through transistor 624 is then mirrored to the PUN current mirror output leg transistors 628(1)-628(N). Therefore, the pull-up current Ioutup in the timing diagram of
In general, the PDN and PUN are complimentary networks so that only one of them is operating at a given time. Thus, vaapix_int is either coupled to vaapix during the PUN operation or AGND/vaapix_lo_vref during the PDN operation.
If rising and falling ramps are not desired during the PDN and PUN operation, the upper plate of capacitor C may be shorted to vaapix or some other adjustable reference voltage. This configuration maintains a constant voltage on the input terminal of op-amp 604 therefore disabling the rising and falling ramps.
If a digital mode of operation is desired, switches S3, S4, S5 and S6 are turned on so that the PUN and PDN are driven by power rails (i.e., AGND and vaapix). Specifically, the PDN current mirror is driven by vaapix via switch S4, while the PUN current mirror is driven by AGND via switch S6. Also, in the digital mode, the analog circuitry comprising Ibias sources 630 and 632, transistors 600 and 602, switches S1 and S2, capacitor C, resistor R, op-amp 604, and transistors 606 and 634 are all disabled.
Thus, during PDN operation, PDN enable transistor 610 is turned on and PUN enable transistor 636 is turned off allowing Ioutdown to flow from power nodes vaapix_int(1-N) of each column through transistors 614(1)-614(N). Similarly, during the PUN operation, PUN transistor 636 is turned on while the PDN transistor 610 is turned off, allowing vaapix to flow to vaapix_int(1-N) through transistors 626(1)-626(N).
As described previously with reference to
When high impedance mode is desired, enable transistors 626(1)-626(N) as well as ring transistors 640(1)-640(N) in
Both embodiments of the switching modules in
Although this invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of the equivalents of the claims and without departing from the invention.
