Number | Name | Date | Kind |
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5373457 | George et al. | Dec 1994 | |
5774382 | Tyler et al. | Jun 1998 |
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Croix et al, “A Fast and Accurate Technique to Optimize Characterization Tables for Logic Synthesis”, IEEE Proceedings of the 34th Design Automation Conference, pp. 337-340, Jun. 1997.* |
Menezes et al, “Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization”, Proceedings of the 32nd ACM/IEEE Design Automation Conference, pp. 690-695, Jun. 1995.* |
John F. Croix, D.F. Wong, “A Fast and Accurate Technique to Optimize Characterization Tables for Logic Synthesis”, Jun. 9, 1997. |