BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows schematically serializer 100 and deserializer 150, according to one embodiment of the present invention.
FIG. 2 is a block diagram showing the major components of phase-locked loop circuit 200, which may be used to implement a phase-locked loop of deserializer 150.
FIG. 3 shows a circuit 300 suitable for use in a DVI application, according to a second embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
According to one embodiment of the present invention, digital video signals may be transmitted over long distance by (1) converting the digital video signals into a serial data stream (“serializing”) before transmission from a source component, (2) transmitting the serial signal over the distance in a cable with fewer conductors than would be required by the digital video signals, and (3) converting the serial signal back to the digital video signals (“deserializing”) upon receipt by the destination component. In this manner, the present invention avoids both the problem of parallel data bit synchronization and the high material cost of the connecting cable.
FIG. 1 shows schematically serializer 100 and deserializer 150, according to one embodiment of the present invention. Serializer 100 and deserializer 150 may be used, for example, to implement data communication between two video components under a suitable data standard (e.g., the DVI standard or the high definition multimedia interface or HDMI standard), or under a proprietary data format. In FIG. 1, for example, a single differential pair transmits data under a proprietary data format. As shown in FIG. 1, serializer 100 includes input latch 101 which receives twenty-four (24) single-ended digital signals from data bus 106, each signal implementing a bit in the 8-bit representations of the colors (e.g., red, green and blue; collectively, “color data”) in a 3-color component video system. In this embodiment, each signal may operate at a data rate of 30-50 Megabits per second (Mbps). In addition, input latch 101 also receives control signals h_sync, v_sync and CLK_R-F. The control signals h_sync and v_sync are control signals familiar to those skilled in video signals. Signal CLK_R-F specifies for input latch 101 whether the parallel data signal should be latched at a rising edge or a falling edge of the reference clock signal. The control signals may also be used to provide synchronization patterns for deserializer 150. For example, when the control signal h_sync is asserted, serializer 100 provides the corresponding predetermined bit pattern for h_sync in the output signal to assist in synchronizing word and pixel boundaries at deserializer 150. Further, a synchronization bit pattern may be inserted prior to transmitting a block of color data.
Based on input reference signal P_CLK and a predetermined serializing ratio, phase-locked loop 105 generates a reference clock signal which is used to latch input signals into latch 101 and to output its contents, and another reference clock signal to clock multiplexer/serializer 102. Multiplexer/serializer 102 selects one of the parallel signals of latch 101 to be driven by encoder/transmitter 103 as output differential signal (SERIAL+, SERIAL−) onto the conductors of a connecting cable 180. Output differential signal (SERIAL+, SERIAL−) may be coded, for example, according to the 8b/10b coding scheme familiar to those skilled in the 10GBASE Ethernet technology. In this embodiment, as both the coding scheme and the electrical characteristics of differential signal (SERIAL+, SERIAL−) conform to the 10GBASE Ethernet technology standard, a convention category 5 (CAT5) or category 6 (CAT6) twisted pairs cable or automotive data transmission cables (e.g., LEONI Dacar products) may be used as connection cable 180. Such a connection cable is known to provide signal integrity up to a distance of a hundred or more meters. Techniques such as transmitter pre-amphasis and receiver equalization allow the signal to be successfully transmitted over an even greater distance. In this embodiment, the data rate achieved on differential output signal (SERIAL+, SERIAL−) may be, for example, 1.5 gigabits per second (Gbps).
In FIG. 1, control circuit 104 controls the operation of serializer 100. As shown in FIG. 1, control circuit 104 may be itself controlled over an I2C bus (I2CADDR, I2CDATA, I2CCLK). Signal DE_IN informs serializer 100 whether color data or control signals should be output. Control signal PWRDN allows power management.
As shown in FIG. 1, the differential signal (SERIAL+, SERIAL−) is received into and decoded by decoding/receiver circuit 151. Phase-locked loop 152, which provides a recovery clock reference by multiplying the frequency of an input reference clock signal RECLK, recovers a clock signal from the output decoded data signal of decoder/receiver circuit 151. This recovered clock signal is used to clock deserializer/demultiplexer 158 to recover the 27 signals transmitted in differential signal (SERIAL+, SERIAL−). Because of the high data rate required in this application, a suitable scheme for robust data and clock recovery is used to implement phase-locked loop 152. One suitable circuit for clock and data recovery is disclosed by one of the present inventors in U.S. Pat. No. 6,931,089, entitled “Phase-locked Loop with Analog Phase Rotator,” filed on Aug. 21, 2001. The disclosure of the '089 patent is hereby incorporated by reference in its entirety to inform the clock and data recovery technique.
FIG. 2 is a block diagram showing the major components of phase-locked loop circuit 200 in accordance with the teachings of the '089 patent. As shown in FIG. 2, phase-locked loop circuit 200 includes phase-detector 201 receiving decoded differential data signal 202. Phase-detector 201 provides a phase-difference signal which indicates in the data signal a phase difference between the input data and the recovered differential clock signal at terminals 203. The recovered differential clock signal is generated by multiplier 206 based on an input reference clock signal. The phase-difference signal is optionally low-pass filtered by low-pass filter 204, which provides the phase-difference signal to analog rotator circuit 205. Analog rotator circuit 205 adjusts the phase of the data signal through multiplier circuit 206. A control signal from analog rotator circuit 205 adjusts the phase difference by changing the multiplier in multiplier circuit 206, thereby increasing or decreasing the frequency of recovered differential clock signal at terminals 203.
Returning to FIG. 1, latch 154 latches the deserialized signal at the output terminals of deserializer 153 and recovers the parallel data and control signals at the input data rate of serializer 100.
The present invention is applicable also to receiving high-speed digital data from multiple asynchronous sources. FIG. 3 shows a circuit 300 suitable for use in this application, according to a second embodiment of the present invention. As shown in FIG. 3, color data is received from 4 sources, with each source providing a clock signal and a differential data signal in each of the component colors (e.g., red green or blue) at corresponding input terminals of 4:1 multiplexers 301a, 301b, 301c and 301d. Multiplexers 401a, which receives the clock signals from the four sources, provides the clock signal from the selected source to phase-locked loop 302, which recover the clock signal using a clock multiplier phase-locked loop. The recovered clock can then be used to recover the differential component color signal from each of the signals selected by multiplexers 301b, 301c and 301d using, for example, the technique disclosed in the '089 patent incorporated by reference above. Note that, under this scheme, the clock signal of multiplexer 301 a is used in the receiver only as a frequency reference, the actual clocking of the recovered data signal (i.e., the color data signals) is extracted from each of the data signal itself. Consequently, the phase relationship between the transmitted clock signal and a data signal, or the phase relationships among transmitted data signals are irrelevant, thereby increasing the system's tolerance to transmission noise. Because the clock signal for clocking each data stream is recovered from the data stream itself, any phase relationship required of the transmitted clock and its associated data signals is significantly reduced, thus relaxing the signal integrity requirements on the connecting cables. Further, in addition to multiplexing multiple DVI signals, the present scheme also extends the distance over which signals can be transmitted using DVI cables, because the transmitted signals are re-clocked. FIG. 3 also represents multiplexing the signals from multiple DVI channels. Each DVI channel may arrive at the circuit of FIG. 3 through the same or different DVI cables, for example. Due to signal degradation in the multiplexing process, the clock and data recovery process shown in FIG. 3 is used to allow reliable data recovery. The analog rotator circuit disclosed in the '089 patent is suitable for this application. FIG. 3 therefore shows data recovery circuits 303a, 303b and 303c recovering the RGB data from 4 DVI channels.
The multiplexing circuit of FIG. 3 includes display data channel (DDC) data, which may be used in a KVM application, for example, to allow bi-directional identification between a video source and a display device receiving the output signals of circuit 300. In that application, a hot-plug detect (HPD) signal can be provided to alert the video sources when the display device comes on-line. In an automobile application, only a single differential pair is required for video data transmission.
The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the following claims.
Patent Application
20070279408
