Patent Application
20060294179
1. Field of the Invention
The present invention relates to thermal management, specifically, deterministic throttling for serial interconnect technology.
2. Description of the Related Art
As mobile PC platforms increase performance and become feature-rich, thermal cooling of the platforms becomes increasingly challenging while sustaining or reducing its form factors and cost. Present thermal management solutions fail to offer a predictable and deterministic scheme. Therefore, the components suffer a performance loss because of over-conservativeness or risking reliability and quality issues because of under-estimation.
Subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. The claimed subject matter, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:
In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention.
An area of current technological development relates to thermal management. As previously described, the existing solutions result in performance loss for the relevant components because of over-conservativeness or risking reliability and quality issues because of under-estimation.
In contrast, a method and a system are proposed that facilitates deterministic thermal management by having either device connected via a link to generate a thermal management request based on the device's thermal capability and the present conditions. The request is transmitted over the link to the other device with a specific sleep period. Consequently, the receiving device responds with an acknowledgement within a pre-configured or pre-agreed response time. An example of the preceding thermal management request and response is depicted in
The claimed subject matter facilitates exchanging latency information via a link initialization process. In another embodiment, latency information may be exchanged in a variety of methods, such as, via an operating system, BIOS, a power management module values hardwired into silicon by design, or latencies set by pin straps (each agent supports a small # of values and we choose value/value pair based on some encoding on a few pinouts)
In one embodiment, the point-to-point (pTp) architecture is defined by Intel's Common System Interface (CSI) and supports a layered protocol scheme,
In this embodiment, the CPU has reached a thermal threshold and requires a thermal management response. A thermal threshold may be an upper bound temperature that the integrated device would malfunction, predetermined operating frequency, thermal operating point, a measurement from an on die thermal sensor, etc. Thus, the CPU sends a thermal management request with a specific sleep period to the chipset via the communication link. The chipset may or may not be thermally stressed, nonetheless, it responds with an acknowledgment within an agreed response time. In response to receiving the acknowledgement, both components provide link inactivity by putting their respective transmitters into high impedance state which that enables the components to enter low power states upon noticing this link condition by their respective receivers.
In order to define the entry and exit latencies for the low power state for the components, in one embodiment, the sleep period, response time, entry and exit latencies are configured and exchanged during a link initialization process. One approach is to use a field in the request and ack/nak protocol. Another approach is to use BIOS to pre-program the extry and exit latencies. In another approach, a mechanism allows for a sideband pin to be used to define the latencies.
In one embodiment, the exit latency from the low power state is a function of resume time required for the power managed circuitry as well as the power delivery capability. In one embodiment, power delivery capability. is the ability to deliver an amount of current (I) on a voltage rail almost instantly to energize the proper functioning of required circuitry (and component). Thus, one aspect of power delivery is to deliver the voltage and current while minimizing and meeting the noise characteristic of that particular voltage rail.
Therefore, the timing parameters for the sleep period, the response time, the entry and exit latencies as well as transmitting the thermal management request and acknowledgement messages are accountable and deterministic.
A typical problem arises for power state selection since a natural conflict arises between the need to balance the level of power management in shutting down more circuitry versus the penalty of longer exit latency. The following flowcharts,
In this embodiment, the initiating agent has active link traffic but detects a thermal threshold (referred to as “thermal stress detection.). As previously discussed, a thermal threshold may be an upper bound temperature that the integrated device would malfunction a predetermined operating frequency, thermal operating point, a measurement from an on die thermal sensor, etc. In one embodiment, a bandwidth throttling algorithm controls the bandwidth by reducing the number of lanes available for data traffic. In another embodiment, the throttling algorithm manages the amount of request and completion packets to process. In yet another embodiment, the entry and exit of low power states. In still another embodiment, a bandwidth utilization counter is used to determine the target's choice of acknowledgement response.
Consequently, the initiating agent generates a thermal management request to the target agent over the link and waits for the acknowledgement from the target agent. The generation of the acknowledgment from the target agent is discussed in the next paragraph. Upon receiving the acknowledgment, the target agent enters a low power state for a predetermined time until a sleep timer expires.
For the target agent's acknowledgement, it eventually receives the thermal management request from the initiating agent over the link. Based on a response timer value, the target agent has a degree of freedom in determining the appropriate time of responding with an acknowledgement. For example, a power optimized approach would require the target agent to respond immediately whereas a performance oriented approach would look at the current or pending transactions for opportunity to complete one or more transactions within the agreed response time before submitting the acknowledgement to enter into low power state.
For embodiment 406, the uni-processor P is coupled to graphics and memory control, depicted as IO+M+F, via a network fabric link that corresponds to a layered protocol scheme. The graphics and memory control is coupled to memory and is capable of receiving and transmitting via PCI Express Links. Likewise, the graphics and memory control is coupled to the ICH. Furthermore, the ICH is coupled to a firmware hub (FWH) via a LPC bus. Also, for a different uni-processor embodiment, the processor would have external network fabric links. The processor may have multiple cores with split or shared caches with each core coupled to a Xbar router and a non-routing global links interface. Thus, the external network fabric links are coupled to the Xbar router and a non-routing global links interface.
Also, the claimed subject matter depicted in the previous Figures and Tables may be implemented in software. For example, the software may be stored in an electronically-accessible medium that includes any mechanism that provides (i.e., stores and/or transmits) content (e.g., computer executable instructions) in a form readable by an electronic device (e.g., a computer, a personal digital assistant, a cellular telephone). For example, a machine-accessible medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals).
Although the claimed subject matter has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiment, as well as alternative embodiments of the claimed subject matter, will become apparent to persons skilled in the art upon reference to the description of the claimed subject matter. It is contemplated, therefore, that such modifications can be made without departing from the spirit or scope of the claimed subject matter as defined in the appended claims.
The description and claims talk about exchanging latency information via link initialization process. This is one example, and we may want to provide other possible mechanisms too.
Examples include, OS, BIOS, a power management module in h/w or s/w, values hardwired into silicon by design (e.g., for a given series of products) or latencies set by pin straps (each agent supports a small # of values and we choose value/value pair based on some encoding on a few pinouts)
