Patent Application
20190165887
The present application relates generally to error correction and, more specifically, to providing a low complexity systematic encoder for error correction in transmitting data using polar codes.
In modern digital data transmission (wireless telephony, wireless data transmission, optical disk transmission to a player, music players receiving music data, and so on), a source encoder can compress the data to be transmitted for efficiency and then a channel encoder can receive the compressed data and add redundancy to it to protect the data against noise in the transmission channel. The receiver (sometimes referred to as the “sink”) at the other end of the channel receives the encoded data and uses a channel decoder to perform the inverse of channel encoding, followed by a source decoder which performs the inverse of source encoding. The decoded information is then played by the sink, e.g., by an optical disk player or music player or receiving telephone as audio, or is otherwise used and/or stored by the receiver.
Present principles focus on channel encoding for transmission of data that possibly contain redundancies introduced purposefully to improve the chances of recovery from error at the receiver. Channel encoding typically works by sending a piece of data sought to be communicated, referred to as a “data word,” through a transformation to produce a “codeword” that is better protected against errors than the data word from which it is derived, and thus is more suitable for transmission than the data word. For present purposes suffice it to say that linear block encoders, which multiply a data word using a matrix, have been used for this purpose because they are able to achieve an acceptable tradeoff of offering significant (albeit not absolute) protection against noise, commonly expressed in terms of the error rates such as bit error rates (BER) that result from noise, while being of sufficiently “low complexity” in terms of the amount of computation they require. Higher complexity encoding schemes that reduce the BER of a received signal but require too much computation for expected data transmission rates are of little practical use.
A newer type of linear block code is the polar code, which improves on older codes by being able to achieve channel capacity, i.e., by being able to encode data such that the full capacity of the transmission channel can be exploited. Channel polarization refers to the fact that given a binary-input discrete memoryless channel W with symmetric capacity I(W), it is possible to synthesize, out of N independent copies of W, a second set of N binary-input channels WN(i), 1≤i≤N such that as N becomes large, a fraction I(W) of the synthesized channels become near perfect while the remaining fraction of channels become near useless. Codes constructed on the basis of this idea are called polar codes. Non-systematic polar encoders effect polar coding by collecting an input data word d and a fixed word b into a transform input word u and by multiplying it with a transform matrix G to render a codeword x, i.e., x=uG.
The transform matrix G used in polar codes is based on Kronecker products, and its dimension is established as appropriate for the desired channel rate or capacity. Polar coding essentially amounts to selecting some of the elements of the transform input word u to carry the data word d while “freezing’ (not using for encoding) the remainder of the elements of the transform input word. The elements of the transform input word that are selected to carry the data word d are those that in effect “see” the relatively good channels created by channel polarization, while the elements of b that are frozen “see” the relatively bad channels. The paper E. Arikan [Arik1], “Channel Polarization: A Method for Constructing Capacity-Achieving Code for Symmetric Binary-Input Memoryless Channels,” IEEE Trans. Inf. Theory, volume 55, pages 3051-3073 (July 2009), incorporated herein by reference and included in the file history of this application, introduced polar codes and describes how to carry out channel polarization and transmit data reliably in the presence of noise using only the “good” channels. Polar codes have attracted interest for practical applications and several methods have been proposed for improving their performance.
One method that was proposed for enhancing polar coding performance is systematic encoding [Arik2]. Systematic encoding of polar codes has several benefits. First, it improves the Bit Error Rate (BER) performance of polar codes as shown in [Arik2, Li]. Second, it allows construction of “turbo-like” polar codes as pointed out in [Arik2] and studied in detail in [Wu]. Third, systematic encoding of polar codes has also been beneficially applied to develop methods for Hybrid Automatic Repeat request (HARQ) schemes, as in [Feng, Moha]. Recursive methods for carrying out systematic encoding of polar codes in a low-complexity manner have been disclosed in [Arik3]. Specific methods that utilize the recursive principles in [Arik3] for systematic polar encoding appeared in [Chen, Sark1, Sark2, Vang].
Recent work on polar coding within standardization bodies, such as [Huaw1], [Huaw2], [Huaw3], and [Intel], propose certain modifications to polar coding that are not compatible with existing methods of systematic encoding of polar codes. In these works, two major modifications are proposed that are of significance for present purposes. First, a certain amount of redundancy, usually in the form of a cyclic redundancy check (CRC), is inserted into the data so as to improve the performance of a list decoder at the receiver [Tal, Huaw1, Huaw2, Intel]. Second, “puncturing” is applied, as a method adjusting the length and rate of the polar code to desired values [Huaw3, Wang]. These above-described methods of “data-checks” and “puncturing” have been proposed within the framework of non-systematic encoding of polar codes.
As recognized herein, however, data-checks and puncturing as proposed in the cited works distort the structure of polar codes and render existing methods of systematic encoding of polar codes inapplicable.
Present principles critically recognize that a systematic encoder for polar codes that allows insertion of data-checks into the transmitted signal in such a way that there is no concomitant performance penalty relative to the case of non-systematic encoding is desirable in order to maximize channel capacity exploitation, maximize immunity from noise, while exhibiting a low computation complexity to enable it to feasibly operate in expected data transmission environments.
A systematic polar encoder with data checks includes a data mapper receiving an input data d containing information to be polar coded for transmission and generating a modified data d′, together with a nonsystematic polar encoder implementing a transform matrix G that encodes the modified data d′ to produce the codeword x such that, for some sub-sequence of coordinates S, xS=d. The non-systematic encoding operation is characterized by a transform input u that includes a part uF satisfying uF=b for a fixed word b that is independent of the data word d, a part uT=t for an inverse puncture word t that is a fixed word independent of the data word d, a part uI carrying the modified data, uI=d′, and a part uC carrying a check word derived from the modified data, uC=f(d′), by a check generator function f, the part uC being strictly non-null. Corresponding to the transform input u is a transform output z given by z=uG that includes a punctured part zP satisfying zP=p for a puncture word p that is a fixed word independent of the data word d, a part zJ carrying the data d, zJ=d, and a part zR serving as redundant symbols, wherein the codeword x is related to the transform output by x=zQ where Q=(J,R) is the complement of the punctured part P. The transform matrix G, the input partition (F,C,I,T) and the output partition (P,J,R) are selected such that GI,P=0, GC,P=0, GF,P=0, and GT,P is invertible and preferably selected such that the check generator function f is an affine function, GI,J is invertible, GC,J=0, and GF,J=0.
Before undertaking the DETAILED DESCRIPTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The term “couple” and its derivatives refer to any direct or indirect communication between two or more elements, whether or not those elements are in physical contact with one another. The terms “transmit,” “receive,” and “communicate,” as well as derivatives thereof, encompass both direct and indirect communication. The terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The term “or” is inclusive, meaning and/or. The phrase “associated with,” as well as derivatives thereof, means to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, have a relationship to or with, or the like. The term “controller” means any device, system or part thereof that controls at least one operation. Such a controller may be implemented in hardware or a combination of hardware together with either or both of software and/or firmware. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. The phrase “at least one of,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be needed. For example, “at least one of: A, B, and C” includes any of the following combinations: A; B; C; A and B; A and C; B and C; and A, B and C.
Moreover, various functions described below can be implemented or supported by one or more computer programs, each of which is formed from computer readable program code and embodied in a computer readable medium. The terms “application” and “program” refer to one or more computer programs, software components, sets of instructions, procedures, functions, objects, classes, instances, related data, or a portion thereof adapted for implementation in a suitable computer readable program code. The phrase “computer readable program code” includes any type of computer code, including source code, object code, and executable code. The phrase “computer readable medium” includes any type of medium capable of being accessed by a computer, such as read only memory (ROM), random access memory (RAM), a hard disk drive, a compact disc (CD), a digital video disc (DVD), or any other type of memory. A “non-transitory”computer readable medium excludes wired, wireless, optical, or other communication links that transport transitory electrical or other signals. A non-transitory computer readable medium includes media where data can be permanently stored and media where data can be stored and later overwritten, such as a rewritable optical disc or an erasable memory device.
Definitions for other certain words and phrases are provided throughout this disclosure. Those of ordinary skill in the art should understand that in many if not most instances such definitions apply to prior as well as future uses of such defined words and phrases.
For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:
In accordance with established conventions in coding theory, data words, parity words, and codewords in the system are represented herein as vectors over a finite field Fq where q denotes the number of elements in the field. Field elements (scalars) are denoted by plain lower case letters, such as a∈Fq. Vectors over a field are denoted by lower-case boldface letters, such as a∈FqN, where N denotes the length of the vector. The notation ai denotes the ith coordinate of a vector a. The convention that the elements of a vector of length N are indexed with integers 0, 1, . . . , N−1 is used. Thus, a vector a∈FqN is denoted in terms of its elements as (a0, . . . , aN−1) or alternatively as (ai: 0≤i≤N−1). Matrices over a field are denoted by upper-case boldface letters, such as A∈FqM×N, where M denotes the number of rows and N denotes the number of columns of A. The notation ai,j denotes the element in the ith row and jth column of A. The elements of a matrix with M rows and N columns are indexed with a pair of integers (i,j), 0≤i≤M−1, 0≤j≤N−1. Accordingly, a matrix A∈FqM×N is denoted in terms of its elements as (ai,j: 0≤i≤M−1, 0≤j≤N−1). The size of a matrix A is defined as the number of elements in A; thus, the size of a matrix with M rows and N columns is MN. All-zero vectors and all-zero matrices are denoted by 0.
Often sub-vectors of a given vector or sub-matrices of a given matrix are considered. To specify such sub-vectors or sub-matrices, tuples (ordered lists of distinct indices over a given index set) are used, and denoted by italic upper-case letters such as I, J. The number of elements in a tuple I is denoted by |I|.
For example, if a=(a0, a1, a2, a3) and I=(1,3), then aI=(a1,a3); whereas, if I=(3,1), then aI=(a3,a1). A similar notation applies to matrices and their sub-matrices. For example, if
I=(1,3), and J=(2,0,3), then
In general, for a vector a=(a0, a1, a2, . . . , aN−1) and a k-tuple I=i1, i2, . . . ik) of indices over {0, 1, . . . , N−1}, aI denotes the sub-vector (ai
with M rows and N columns, an m-tuple I=(i1, i2, . . . , im) over {0, 1, . . . , M−1}, and an n-tuple J=(j1, j2, . . . , jn) over {0, 1, . . . , N−1}, the notation AI,J denotes the sub-matrix
A tuple of tuples (I1, I2, . . . , In) is called a partition of the index set {0, 1, . . . , N−1} if each index 0≤i≤N−1 belongs to one and only one of the tuples Ij, and each element of each tuple Ij belongs to the index set {0, 1, . . . , N−1}. Every partition (I1, I2, . . . , In) of {0, 1, . . . , N−1} partitions each vector a=(a0, a1, a2, . . . , aN−1) into n (disjoint) sub-vectors aI
The product of a row vector a∈FqM and a matrix A∈FqM×N is denoted as aA. The Kronecker product of two matrices A∈Fqm×r and BϵFqk×l is defined as:
which is an mk-by-rl matrix. A matrix C is said to factorize into a Kronecker product of a matrix A and B if C=A⊗B. The nth Kronecker power of a matrix A is defined recursively as A⊗n=A⊗A⊗(n−1) for n≥2, with A⊗1=A.
Encoding operations comprise various transformations of vector representations of data words, parity words, and codewords. The term “transform” is used below to refer to linear vector space transformations. Transforms are represented by matrices. Transforms are usually cited below together with a specific matrix representation; for example, “transform G” refers to a transform that is represented by the matrix G in a specific basis.
For an integer i in the range 0≤i≤2n−1, bn−1bn−2 . . . b0 is the binary expansion of i if bm is 0 or 1 for each 0≤m≤n−1 and
For any two integers i,j in the range 0≤i, j≤2n−1, the notation ij is used to indicate that the binary expansion bn−1bn−2 . . . b0 of i dominates the binary expansion b′n−1b′n−2 . . . b′0 of j in the sense that bm≥b′m for all 0≤m≤n−1. The notation “i
j” and the phrase “i dominates j” are used synonymously. The relation “
” on the set of integers in the range 0 to 2n−1 defines a “partial order.” It is reflexive: i
i for every i; antisymmetric: if i
j for distinct i and j, then the converse j
i cannot be true; and transitive: if i
j and j
k, then i
k. The relation “
” is a “partial order” (as opposed to a “total order”) in the sense that there are integers i and j for which neither i
j nor j
i is true. For example, neither 14 (which is 1110 in binary) nor 7 (which is 0111 in binary) dominates the other.
A special type of transform that is important for polar coding is the transform F⊗n where
and F⊗n is the nth Kronecker power of F. A well-known [Arik1] property links F⊗n with the domination relation between binary expansions: we have (F⊗n)i,j=1 if and only if ij, where the rows and columns are indexed starting with 0 and the indices take values in the range 0≤i, j≤2n−1. For example, with n=3, we have
and (F⊗3)6,5=0 since 65 is false, while (F⊗3)7,j=1 since 7
j for all 0≤j≤7.
A key property of the transform F⊗n that is important for present principles is that for any tuple of k (distinct) coordinates, such as A=(a1, a2, . . . , ak), the submatrix (F⊗n)A,A is invertible. This can be seen by observing that if the elements of A are in ascending order, a1<a2< . . . <ak, then A is lower triangular with 1s on the diagonal. If A is not in ascending order, one may consider the tuple à that has the coordinates in A in the ascending order. Since (F⊗n)A,A and (F⊗n)Ã,à differ only by a permutation of rows and columns, one is invertible if and only if the other is invertible.
A second key property of the transform F⊗n is that, for any two tuples A=(a1, a2, . . . , ak) and B=(b1, b2, . . . , bm) the submatrix (F⊗n)A,B equals the all-zero matrix if and only if no element ai of A dominates any element bj of B; that is, (F⊗n)A,B=0 if and only if ai⊗bj is false for every 1≤i≤k and 1≤j≤m.
With the above in mind, initially referring to
It is to be understood that present principles apply to various transmission systems and media. For example, in a wireless communication system, the transmission medium 30 typically is space or the atmosphere, in which case the communication system 10 is a wireless communication system. In such embodiments, the transmission system 20 and reception system 40 each include antenna(s) coupled respectively to the transmitter 150 and receiver 160. However, other embodiments of the present disclosure may be implemented in wired communications systems, in which case the transmission medium 30 may be a cable or a wire that connects the transmission system 20 to the reception system 40. Embodiments of the present disclosure may also be implemented for storage systems, in which case the transmission medium 30 may be a magnetic tape, a hard disk drive, an optical disk drive, a solid state memory, or another storage medium.
As will be apparent to those of skill in the art, input data 110 is ordinarily input into the transmission system 20 for eventual transmission to the reception system 40. A source encoder 120 compresses input data 110 so that the amount of data that must be transmitted is reduced. Data output from the source encoder 120 is then encoded by a channel encoder 130, which is configured as described in further detail below. Such encoding renders the data to be transmitted more robust against errors that may be introduced during transmission across the transmission medium 30. In accordance with present principles, the channel encoder 130 implements a systematic encoder. After such encoding, the data is modulated by a modulator 140 and provided to a transmitter 150 for transmission through the transmission medium 30 to the reception system 40. The transmitter 150 has the task of converting information into signals capable of being transmitted across the transmission medium 30. For example, the transmitter 150 may be a radio frequency (RF) radio transmitter with an antenna when the transmission medium 30 is airwaves or the transmitter 150 may be a laser device sending light into a fiber-optic cable.
The reception system 40 generally receives signals from the transmission medium 30 and demodulates and decodes them to extract the output data 195. With more specificity, a receiver 160 of the reception system 40 receives signals from the transmission system 20 and passes the signals to a demodulator 170, which demodulates the received signals. The demodulated signals are then sent to a channel decoder 180, which produces a decoded data as an estimate of the transmitted data, and then the decoded data is sent to a source decoder 190 to decompress (and optionally verify) the data. It will readily be appreciated that the demodulator 170, channel decoder 180, and source decoder 190 perform the inverse of the operations performed by the modulator 140, channel encoder 130, and source encoder 120, respectively, subject to limitations imposed by noise effects and other non-idealities in the system. In any case, if the communication system 10 is properly designed and operated within its design parameters, extracted output data 195 should match the input data 110 with high reliability.
According to present principles, each component 120, 130, 140, and 150 of the transmission system 20 and each component 160, 170, 180, and 190 of the reception system 40 comprises electrical circuits and may be implemented on its own respective semiconductor chip, with the various chips communicating with each other according to the system of
Turning to
Turning to
One problem addressed by the present disclosure is the construction of a data mapper that turns a non-systematic encoder with data checks into a systematic encoder with data checks. It is to be noted that a direct implementation of such a data mapper may be prohibitively complex due to the inclusion of redundancy as part of the encoding process. Present principles described herein address the development of a low-complexity method for implementing such a data mapper for the case of polar codes, which is the primary application domain for subject matter of the present disclosure.
The non-systematic polar encoder 400 includes as processing blocks a check generator 410, a transform input assembler 420, a polar transform G 430, and a puncturer 440. Those processing blocks operate on a number of sequences of symbols (signals), including a data d 401, a codeword x 402, a fixed word b 403, a check word c 404, and an inverse puncture word t 405.
The non-systematic polar encoder 400 receives, as input, a data d 401 and produces, as output, a codeword x 402.
The fixed word b 403 is a fixed pattern of symbols independent of the data d 401.
The check generator 410 computes a check word c 404 from the data d 401 by computing c=f(d), where f is a function independent of the data d 401.
The inverse puncture word t 405 is a fixed pattern of symbols independent of the data d 401.
The transform input assembler 420 receives the data d 401, the fixed word b 403, the check word c 404, and the inverse puncture word t 405, and produces the transform input u 406. The multiplexing operation by the transform input assembler 420 is characterized by an input partition (F,C,I,T), which is a partition of the index set {0, 1, . . . , N−1} of the input vectors of the polar transform G 430. The transform input assembler 420 assembles the transform input u 406 in accordance with the partition (F,C,I,T) so that uF=b, uC=c, uI=d, and uT=t.
The polar transform G 430 implements a transform operation represented by a “polar transform matrix G,” where in the most general form of the present principles G is an arbitrary invertible matrix with N rows and N columns, for some positive integer N. However, present principles are applicable at low complexity only if G has a special structure, as described below.
It is to be noted that the present disclosure uses the convention of labeling the rows and columns of the transform matrix G by the integers {0, 1, . . . , N−1} solely for convenience of notation in the presentation of present principles. It will be clear that alternative labeling conventions may be used in actual embodiments of present principles.
In preferred embodiments of present disclosure, the polar transform matrix G 430 is given by the Kronecker product of a plurality of matrices, each of which has a size smaller than a size of G, so as to render computation of the transform at low-complexity possible by using recursive computational methods.
Preferred embodiments are applicable with advantage whenever the transform matrix has the form G=A(F1⊗G1)BT, wherein A is a permutation matrix, F1 is a first kernel transform, G1 is a first-tier transform, B is a permutation matrix, the first kernel transform F1 has a size greater than one, and the first-tier transform G1 has a size smaller than a size of the transform G. A common choice for the preferred embodiments of present principles is to take A and B as the identity permutation.
In a first type of a most preferred embodiment of present principles, the transform matrix has the form G=F⊗n, where
and all transform operations are carried out in the binary field F2. In this case, the number of rows and columns is constrained to be a power of two, N=2n. (The need for puncturing arises in order to set the length of the codewords to integer values other than powers of two. The present disclosure describes how to carry out specific methods of puncturing in combination with systematic encoding of data.)
In a second type of most preferred embodiment of present principles, the transform matrix has the form G=AF⊗nBT, where A or B is a “bit reversal” permutation, as defined in [Arik1].
The polar transform G 430 takes as input the transform input u 406 and produces a transform output z 407, the transform output z 407 being related to the transform input u 406 by the functional relationship z=uG. The transform output z 407 is processed by a puncturer 440, the puncturer 440 being characterized by an output partition (P,Q), the output partition (P,Q) being a partition of the index set {0, 1, . . . , N−1} of vectors in the range space of the polar transform G 430.
The codeword x 402 is obtained from the transform output z 407 by setting x=zQ, which corresponds to puncturing the part zP.
In some forms of puncturing, such as in [Wang, Huaw3], and in preferred embodiments of present principles, the puncturing operation includes a constraint of the form zP=p, where p is a fixed word independent of the data d 401. The non-systematic encoder 400 accommodates such a constraint by computing the inverse puncture word t 405 as a function of p and substituting the constraint uT=t in place of zP=p.
Turning to
The systematic polar encoder 500 includes a data mapper 510 and a non-systematic polar encoder with data checks and puncturing 520. The non-systematic polar encoder 520 is a non-systematic polar encoder such as the non-systematic polar encoder with data checks and puncturing 400 in
The data mapper 510 receives a data d 501 and converts it into a modified data d′ 503, which in turn is received as input by the non-systematic polar encoder 520 and encoded into a codeword x 502. The systematic polar encoder 500 is systematic in the sense that there is a fixed tuple S such that xS=d.
Embodiments of present principles described below aim to turn a given non-systematic polar encoder 520 into a systematic polar encoder as in
Before presenting specific embodiments of present rules, the underlying principles will be explained by carrying out a mathematical analysis of the relationship between the data mapper 510 and the non-systematic encoder 520. This analysis will reveal sufficient conditions to render practical implementations of the systematic polar encoder 500 possible.
In the analysis of the systematic polar encoder 500 that follows, it will be assumed that the non-systematic polar encoder 520 is a non-systematic polar encoder 400 of the type shown in
Turning to the analysis, note that the encoding operation is carried out under the following constraints. First, there is the transform relationship:
z=uG (1)
Second, the transform input is assembled from its various parts as
u
T
=t (2)
u
I
=d′ (3)
u
C
=c=f(d) (4)
u
F
=b (5)
Third, there is the systematic encoding constraint that the data appear as part of the transform output:
z
J
=d (6)
Finally, preferred embodiments of present principles impose a constraint of the form
z
P
=p (7)
on the puncturing operation, where p is a fixed pattern independent of the data d. The system of Eq. (1) through (7) constitute an overdetermined system in the sense that there are more equations than the number of degrees of freedom, which is equal to N. However, in preferred embodiments of present principles, Eq. (2) and (7) actually stand for the same constraint by allowing t to be a function of p. Hence, it is possible to satisfy Eq. (1) through (7) simultaneously, provided that the partitions (F,C,I,T) and (P,J,R) are selected properly. The present disclosure describes methods of selecting the partitions that render systematic encoding under the constraints of Eq. (1) through (7) feasible.
To discuss present principles more thoroughly, it is useful to rewrite the transform relation Eq. (1) in the following form:
z
P
=u
T
G
T,P
+u
I
G
I,P
+u
C
G
C,P
+u
F
G
F,P (8)
z
J
=u
T
G
T,J
+u
I
G
I,J
+u
C
G
C,J
+u
F
G
F,J (9)
z
R
=u
T
G
T,R
+u
I
G
I,R
+u
C
G
C,R
+u
F
G
F,R (10)
Eq (8)-(10) reveal the effect of each part of the transform input on each part of the transform output under the input and output partitions (F,C,I,T) and (P,J,R). A number of design rules emerge by inspecting Eq. (2) through (10), as stated below. These design rules form the mathematical basis of present principles.
Design Rule 0:
Choose the transform matrix G and the input partition (F,C,I,T) and the output partition (P,J,R) so that GI,P=0, GC,P=0, GF,P=0, and GT,P is invertible.
Remark:
Design Rule 0 ensures that p and t stand in one-to-one relationship to each other by the relations p=tGT,P and t=p(GT,P)−1, as can be seen readily from Eq. (2), (7), and (8).
Design Rule 1:
Choose the transform matrix G, the input partition (F,C,I,T), and the output partition (P,J,R) so that, in addition to Design Rule 0 being satisfied, the check generator Eq. (4) is an affine function of the form
u
C
=u
I
E+e, (11)
and (GI,J+EGC,J) is an invertible matrix.
Remark:
Under Design Rule 1, it follows from Eq. (2) through (7) and Eq. (9) that
d′=(d−tGT,J−eGC,J−bGF,J)(GI,J+EGC,J)−1 (12)
Eq. (12) defines a data mapper that can be used in the role of the data mapper 510 in
The first embodiment assumes that Design Rule 1 is satisfied. The data mapper 510 in this embodiment is based on Eq. (12), which can be written in a simpler form as
d′=dD+a (13)
where D=(GI,J+EGC,J)−1 and a=(−tGT,J−eGC,J−bGF,J)(GI,J+EGC,J)−1. The matrix D and the vector a are independent of the data d, so they can be precomputed and the data mapping operation Eq. (13) consists of computing an affine transform of the data d.
In this embodiment, after obtaining the modified data d′ 503 by Eq. (13), systematic polar encoding can be completed by employing any available non-systematic encoder in place of the non-systematic encoder 520. If a non-systematic encoder is not available, or as an alternative to an existing non-systematic encoder, the non-systematic encoder 520 can be realized by assembling the transform input u 406 in accordance with Eq. (2) through (5), and computing the transform output z 407 in accordance with Eq. (1). Once the transform output z 407 is available, the codeword x 402 is obtained by setting x=zQ where Q=(J,R) is the complement of the punctured indices P.
The first embodiment mainly serves a proof-of-concept purpose by showing that a data mapper can be implemented by computing Eq. (13). For practical applications, the first embodiment may be too complex since the matrix D that appears in Eq. (13) may not have any structure that can be exploited for reducing complexity of computations. A direct computation of dD has a computational complexity on the order of the size of matrices involved, which for a code of length N may run into order N2. In refinements of the first embodiment, further structure is imposed on the transform matrix G to bring down computational complexity to practical levels.
Design Rule 2:
The transform matrix G, the input partition (F,C,I,T), and the output partition (P,J,R) are chosen so that, in addition to Design Rule 0 being satisfied, GI,J is invertible, GC,J=0, and GF,J=0.
Remark:
Under Design Rule 2, Eq. (13) simplifies to
d′=d(GI,J)−1−tGT,J(GI,J)−1. (14)
Eq. (14) defines an alternative data mapper that will be explored in a second embodiment of present principles.
The second embodiment assumes that the system under discussion conforms to Design Rule 2. This embodiment uses a data mapper based on Eq. (14). The rest of the systematic encoding operation can be completed in the same manner as in the first embodiment.
A direct computation of Eq. (14) may still be too complex for practical purposes. A third embodiment of present principles below organizes the computations in the second embodiment in a different manner with the goal of taking advantage of a structure that may exist in the transform G, which proves useful when working directly with the matrix (GI,J)−1 as in Eq. (14) does not allow taking advantage of such structure readily.
The third embodiment refines the computational method of the second embodiment and constitutes a most preferred embodiment of present principles.
Consider the matrix
The matrix {tilde over (G)} is obtained by permuting the rows and columns of G:
{tilde over (G)}=AGB
T (16)
where A and B are permutation matrices. Assuming that G is invertible, {tilde over (G)} is also invertible and
({tilde over (G)})−1=BG−1AT, (17)
as can be verified by direct computation and noting that the inverse of a permutation matrix equals its transpose.
Under Design Rule 2, the matrix {tilde over (G)} has an upper triangular form
It is well known that an invertible upper-triangular matrix has an inverse which is also upper-triangular. Thus, the inverse of {tilde over (G)} has the form
where “*” denotes a generic submatrix whose particular form does not have any significance for present purposes. Note that Eq. (19) assumes that the inverses of GT,P and GI,J exist, which is guaranteed to be true by Design Rule 2.
A third embodiment comprises the following data mapper.
A preferred embodiment of the data mapper 510 will:
1) Receive as input the data d 501;
2) Prepare a transform word w such that wP=p, wJ=d, and wR=0;
3) Compute v=wG−1; and
4) Output vI as the modified data d′ 503.
Proposition.
The data mapper in the preceding paragraph implements the data mapping operation as specified by Eq. (14); in other words, the output at step 4) satisfies vI=dD+a with D=(GI,J)−1 and a=−tGT,J(GI,J)−1.
Proof.
The equation v=wG−1 can be written as
This shows that
v
I
=−w
P(GT,P)−1GT,J(GI,J)−1+wJ(GI,J)−1 (21)
Recalling that wP=p, wJ=d, and tGT,P=p, Eq. (21) is equivalent to
v
I
=−p(GT,P)−1GT,J(GI,J)−1+d(GI,J)−1=tGT,J(GI,J)−1+d(GI,J)−1. (22)
The proof is complete.
Remark:
The above proof makes it evident that the submatrices in Eq. (19) denoted by “*” play no role in this context.
The question that arises is whether there is any advantage to computing d′ as part of a larger transform operation as in Eq. (20) instead of directly as in Eq. (14). It may appear that the calculation by Eq. (20) is more involved than Eq. (14) since it involves operations on larger matrices. However, if G−1 has a structure that can be exploited to simplify the calculations, then Eq. (20) can readily take advantage of this, while in Eq. (14) the derived matrix D may have no structure left that can readily be exploited. Present principles recognize that embedding the data mapping operation into a larger matrix operation may simplify the calculations significantly.
In this third embodiment, once the modified data d′ 503 is computed by a data mapper, it is provided as input to the non-systematic polar encoder 520, which may be any given encoder or implemented directly as discussed in connection with the first embodiment above. The exact nature of how the non-systematic polar encoder 520 is implemented is a side issue for present purposes. Present principles are directed primarily at providing an implementation of the data mapper 510 at low-complexity.
A class of codes that can benefit readily from present principles is the class of polar codes [Arik1]. In the case of polar codes, the transform matrix is of the form G=F⊗n where
is called the “kernel” of the construction. The following properties of the polar transform are well known [Arik1]. The transform matrix has elements Gi,j such that Gi,j=1 if ij and Gi,j=0 otherwise. The inverse transform G−1 equals G, and for any given u, the forward transform uG and its inverse uG−1 can be computed using order N log N logic operations.
Turning to
The polar transform 600 receives a transform input u 601 and outputs a transform output z 602. The transform input u 601 and the transform output z 602 are signals consisting of 16 Boolean variables which may be implemented using standard logic gates. The polar transform 600 operates using standard digital logic circuitry and comprises exclusive-or gates as the main data processing elements. The computation carried out by the polar transform is equivalent to the matrix operation z=uG in the binary field F2.
While still looking at
Consider a systematic polar encoder as in
Suppose that the input partition (F,C,I,T) and the output partition (P,J,R) are specified as follows:
T=P=(7,11,15)=(0111,1011,1111)
I=J=(3,12,13,14)=(0011,1100,1101,1110)
C=(6,9,10)=(0110,1001,1010)
F=(0,1,2,4,5,8)=(0000,0001,0010,0100,0101,1000)
R=(F,C)=(0,1,2,4,5,8,6,9,10)=(0000,0001,0010,0100,0101,1000,0110,1001,1010)
In writing the partition elements, the binary representations of the indices have also been given in order to facilitate checking if Gi,j=1. (Recall that Gi,j=1 if and only if ij holds.)
Some submatrices of G that are of interest for the present example are
Note that GT,P and GI,J are invertible, as required by Design Rule 2.
Note also that GI,P=0, GC,P=0, GF,P=0, GC,J=0, and GF,J=0.
Thus, the design choices in this example satisfy all requirements of Design Rule 2.
Conformance to Design Rule 2 is facilitated by some general properties of the transform G=F⊗n. Specifically, the invertibility of the submatrices GT,P=T and GI,J=I is due to the general property that GA,A is invertible for any non-empty A. The fact that GI,P=0 is due to the fact that no element in I dominates any element in P. The same explanation holds for GC,P=0, GF,P=0, GC,J=0, and GF,J=0.
It should be clear from the preceding discussion how to select the input partition (F,C,I,T) and the output partition (P,J,R) so that Design Rule 2 will be valid in general with G=F⊗n for any integer n≥1.
Continuing with the example, let b=(0,1,1,0,1,0), p=(1,1,0), and uC be given by the linear function
The inverse puncture word t is computed as
In the second embodiment, the data mapper takes the form
For example, if d=(1,0,1,1), then d′=(1,0,1,1).
In the third embodiment, the data mapper first assembles a w such that wP=p, wJ=d, wR=0, then computes v=wG−1, and finally outputs v1 as d′. For example, if d=(1,0,1,1), then
w=(0,0,0,1,0,0,0,1,0,0,0,1,0,1,1,0),
v=wG
−1=(1,0,0,1,1,0,0,1,1,0,0,1,0,1,1,0), and
d′=v
I=(1,0,1,1).
Turning to
The third embodiment above can utilize the recursive divide-and-conquer strategy of
Depending on the network type, other well-known terms may be used instead of “eNodeB” or “eNB,” such as “base station” or “access point.” For the sake of convenience, the terms “eNodeB” and “eNB” are used in this patent document to refer to network infrastructure components that provide wireless access to remote terminals. Also, depending on the network type, other well-known terms may be used instead of “user equipment” or “UE,” such as “mobile station” (or “MS”), “subscriber station” (or “SS”), “remote terminal,” “wireless terminal,” or “user device.” For the sake of convenience, the terms “user equipment” and “UE” are used in this patent document to refer to remote wireless equipment that wirelessly accesses an eNB, whether the UE is a mobile device (such as a mobile telephone or smartphone) or is normally considered a stationary device (such as a desktop computer or vending machine).
The eNB 802 provides wireless broadband access to the network 830 for a first plurality of user equipments (UEs) within a coverage area 820 of the eNB 802. The first plurality of UEs includes a UE 811, which may be located in a small business (SB); a UE 812, which may be located in an enterprise (E); a UE 813, which may be located in a WiFi hotspot (HS); a UE 814, which may be located in a first residence (R); a UE 815, which may be located in a second residence (R); and a UE 816, which may be a mobile device (M) like a cell phone, a wireless laptop, a wireless personal digital assistant (PDA), or the like. The eNB 803 provides wireless broadband access to the network 830 for a second plurality of UEs within a coverage area 825 of the eNB 803. The second plurality of UEs includes the UE 815 and the UE 816. In some embodiments, one or more of the eNBs 801-803 may communicate with each other and with the UEs 811-816 using 3G, 4G or 5G, long-term evolution (LTE), LTE-A, WiMAX, or other advanced wireless communication techniques.
Dotted lines show the approximate extents of the coverage areas 820 and 825, which are shown as approximately circular for the purposes of illustration and explanation only. It should be clearly understood that the coverage areas associated with eNBs, such as the coverage areas 820 and 825, may have other shapes, including irregular shapes, depending upon the configuration of the eNBs and variations in the radio environment associated with natural and man-made obstructions.
As described in more detail below, one or more of BS 801, BS 802 and BS 803 include 2D antenna arrays as described in embodiments of the present disclosure. In some embodiments, one or more of BS 801, BS 802 and BS 803 support the codebook design and structure for systems having 2D antenna arrays.
Although
The example wireless transmit path 20 and receive path 40 depicted in
The UE 816 includes an antenna 905, a radio frequency (RF) transceiver 910, transmit (TX) processing circuitry 915 (which may be the transmit system 20 in
The RF transceiver 910 receives, from the antenna 905, an incoming RF signal transmitted by an eNB of the network 800. The RF transceiver 910 may down-convert (e.g., within or in connection with demodulator 170) the incoming RF signal to generate an intermediate frequency (IF) or baseband signal which would be sent to the receive (Rx) processing circuitry 925 implementing channel decoder 180 and source decoder 190, which generates a processed signal by filtering, decoding, and/or digitizing the baseband or IF signal. The Rx processing circuitry 925 transmits the processed signal (including output data 195) to the speaker 930 (such as for voice data) or to the main processor 940 for further processing (such as for web browsing data).
The transmit (Tx) processing circuitry 915 receives, as at least some input data 110, analog or digital voice data from the microphone 920 or other outgoing baseband data (such as web data, e-mail, or interactive video game data) from the main processor 940. The Tx processing circuitry 915 implements source encoder 120 and channel encoder 130 to encode, multiplex, and/or digitize the outgoing data to generate a processed baseband or IF signal. The RF transceiver 910 receives the outgoing processed baseband or IF signal from the Tx processing circuitry 915 and up-converts (e.g., within or in connection with modulator 140) the baseband or IF signal to an RF signal that is transmitted via the antenna 905.
The main processor 940 can include one or more processors or other processing devices and execute the basic OS program 961 stored in the memory 960 in order to control the overall operation of the UE 816. For example, the main processor 940 could control the reception of forward channel signals and the transmission of reverse channel signals by the RF transceiver 910, the Rx processing circuitry 925, and the Tx processing circuitry 915 in accordance with well-known principles. In some embodiments, the main processor 940 includes at least one programmable microprocessor or microcontroller, while in other embodiments the main processor includes dedicated circuitry (e.g., for systemic and/or non-systematic encoding or decoding processes, puncturing processes, data mapping, etc.) as well as (optionally) programmable logic or processing circuits.
The main processor 940 is also capable of executing other processes and programs resident in the memory 960, such as operations for channel quality measurement and reporting for systems having 2D antenna arrays as described in embodiments of the present disclosure. The main processor 940 can move data and/or instructions into or out of the memory 960 as required by an executing process. In some embodiments, the main processor 940 is configured to execute the applications 962 based on the OS program 961 or in response to signals received from eNBs or an operator. The main processor 940 is also coupled to the I/O interface 945, which provides the UE 816 with the ability to connect to other devices such as laptop computers and handheld computers. The I/O interface 945 is the communication path between these accessories and the main controller 940.
The main processor 940 is also coupled to the keypad 950 (which may simply be a single button or may be an array or other set of buttons) and the display unit 955. The operator of the UE 816 can use the keypad 950 to enter data into the UE 816. The display 955 may be a touch screen display or other display capable of rendering text and/or at least limited graphics, such as from web sites, and receiving touch inputs by a user in accordance with known practices. The memory 960 is coupled to the main processor 940, and at least a part of the memory 960 could include a random access memory (RAM), and another part of the memory 960 could include a Flash memory or other read-only memory (ROM).
Although
As shown in
The RF transceivers 972a-972n receive, from the antennas 970a-970n, incoming RF signals, such as signals transmitted by UEs or other eNBs. The RF transceivers 972a-972n down-convert (e.g., within or in connection with demodulator 170) the incoming RF signals to generate IF or baseband signals. The IF or baseband signals are sent to the Rx processing circuitry 976 implementing channel decoder 180 and source decoder 190, which generates processed signals by filtering, decoding, and/or digitizing the baseband or IF signals. The Rx processing circuitry 976 transmits the processed signals (including output data 195) to the controller/processor 978 for further processing.
The Tx processing circuitry 974 receives, as at least some input data 110, analog or digital data (such as voice data, web data, e-mail, or interactive video game data) from the controller/processor 978. The Tx processing circuitry 974 implements source encoder 120 and channel encoder 130 to encode, multiplex, and/or digitize the outgoing baseband data to generate processed signals. The RF transceivers 972a-972n receive the outgoing processed signals from the Tx processing circuitry 974 and up-converts (e.g., within or in connection with modulator 140) the baseband or IF signals to RF signals that are transmitted via the antennas 970a-970n.
The controller/processor 978 can include one or more processors or other processing devices that control the overall operation of the eNB 802. For example, the controller/processor 978 could control the reception of forward channel signals and the transmission of reverse channel signals by the RF transceivers 972a-972n, the Rx processing circuitry 976, and the Tx processing circuitry 974 in accordance with well-known principles. The controller/processor 978 could support additional functions as well, such as more advanced wireless communication functions. Any of a wide variety of other functions could be supported in the eNB 802 by the controller/processor 978. In some embodiments, the controller/processor 378 includes at least one microprocessor or microcontroller, while in other embodiments the main processor includes dedicated circuitry (e.g., for systemic and/or non-systematic encoding processes, puncturing processes, data mapping, etc.) as well as (optionally) programmable logic or processing circuits.
The controller/processor 978 is also capable of executing programs and other processes resident in the memory 980, such as a basic OS. The controller/processor 978 is also capable of supporting channel quality measurement and reporting for systems having 2D antenna arrays as described in embodiments of the present disclosure. In some embodiments, the controller/processor 978 supports communications between entities. The controller/processor 878 can move data and/or instructions into or out of the memory 980 as required by an executing process.
The controller/processor 978 is also coupled to the backhaul or network interface 982. The backhaul or network interface 982 allows the eNB 802 to communicate with other devices or systems over a backhaul connection or over a network. The interface 982 could support communications over any suitable wired or wireless connection(s). For example, when the eNB 802 is implemented as part of a cellular communication system (such as one supporting 3G, 4G, 5G, LTE, or LTE-A), the interface 982 could allow the eNB 802 to communicate with other eNBs over a wired or wireless backhaul connection. When the eNB 802 is implemented as an access point, the interface 982 could allow the eNB 802 to communicate over a wired or wireless local area network or over a wired or wireless connection to a larger network (such as the Internet). The interface 982 includes any suitable structure supporting communications over a wired or wireless connection, such as an Ethernet or RF transceiver.
The memory 980 is coupled to the controller/processor 978. Part of the memory 980 could include a RAM, and another part of the memory 980 could include a Flash memory or other ROM. In certain embodiments, a plurality of instructions is stored in memory. The plurality of instructions are configured to cause the controller/processor 978 to perform the systemic and/or non-systematic encoding or decoding processes, puncturing processes, data mapping, etc.
Although
While the particular METHOD AND SYSTEM FOR ERROR CORRECTION IN TRANSMITTING DATA USING LOW COMPLEXITY SYSTEMATIC ENCODER is herein described in detail and is depicted in the drawings, it is to be understood that the subject matter which is encompassed by the present disclosure is limited only by the claims. Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications that fall within the scope of the appended claims. The description in the present application should not be read as implying that any particular element, step, or function is an essential or critical element which must be included in the claim scope: the scope of patented subject matter is defined only by the allowed claims. Moreover, none of these claims are intended to invoke 35 USC § 112(f) with respect to any of the appended claims or claim elements unless the exact words “means for” or “step for” are explicitly used in the particular claim, followed by a participle phrase identifying a function. Use of terms such as (but not limited to) “mechanism,” “module,” “device,” “unit,” “component,” “element,” “member,” “apparatus,” “machine,” “system,” “processor,” or “controller” within a claim is understood and intended to refer to structures known to those skilled in the relevant art, as further modified or enhanced by the features of the claims themselves, and is not intended to invoke 35 U.S.C. § 112(f).
