Claims
- 1. A method for analyzing parasitic impedance in a circuit, comprising:
receiving a description of a layout of the circuit; receiving an identification of a conductor to be analyzed in the circuit; tracing the conductor to be analyzed using the description of the layout of the circuit; determining parasitic impedance values including an inductance value for the conductor using a parameterized inductance function with pre-computed coefficients; and creating a circuit description for the conductor using the parasitic impedance values.
- 2. The method of claim 1, wherein determining the inductance value for the conductor comprises:
analyzing structures within a selected distance of the conductor within the circuit; determining a distance from the conductor to a current return path for the conductor; and using the distance to the current return path and the parameterized inductance function to determine the inductance value for the conductor.
- 3. The method of claim 1, wherein determining the parasitic impedance values comprises determining a parasitic capacitance value for the conductor.
- 4. The method of claim 3, wherein determining the parasitic impedance values further comprises determining a resistance value for the conductor.
- 5. The method of claim 4, wherein creating the circuit description for the conductor using the parasitic impedance values comprises:
changing at least one of the parasitic capacitance value and the resistance value for the conductor in response to the inductance value; and creating the circuit description for the conductor using the parasitic capacitance value and the resistance value.
- 6. The method of claim 1, further comprising:
receiving a technology profile including values of physical parameters characterizing a plurality of conducting and dielectric layers of the circuit; and creating impedance functions including the parameterized inductance function in an interconnect primitive library in response to the technology profile.
- 7. The method of claim 6, wherein creating the parameterized inductance function in the interconnect primitive library in response to the technology profile comprises:
performing a plurality of inductance calculations for one of the conducting layers of the integrated circuit including the conductor using the physical parameters characterizing the plurality of conducting and dielectric layers from the technology profile, the inductance calculations being performed using a set of difference distances to return path; and storing a set of inductance values resulting from the plurality of inductance calculations in the interconnect primitive library together with the distances to return path corresponding to each inductance value.
- 8. The method of claim 7, wherein determining the inductance value for the conductor using the parameterized inductance function comprises:
dividing the conductor into a plurality of segments; for each conductor segment, determining a distance from the conductor segment to a current return path for the conductor segment; for each conductor segment, deriving an inductance value for the conductor segment using the inductance values stored in the interconnect primitive library; and adding together the inductance values for the conductor segments to determine the inductance value for the conductor.
- 9. The method of claim 8, wherein deriving the inductance value for each conductor segment comprises interpolating between the inductance values stored in the interconnect primitive library using the distance from the conductor segment to the current return path for the conductor segment.
- 10. The method of claim 1, further comprising receiving an identification of an operating frequency of the circuit, wherein determining the inductance value for the conductor comprises comparing the operating frequency of the circuit to a frequency associated with the parameterized inductance function of the interconnect primitive library.
- 11. The method of claim 1, further comprising performing a circuit timing simulation using the circuit description for the conductor.
- 12. A method for determining a parasitic impedance value for a conductor from an integrated circuit description, comprising:
determining from the integrated circuit description a distance to a current return path for the conductor; and calculating an inductance value for the conductor using the distance to the current return path and a parameterized inductance function with a set of pre-computed coefficients.
- 13. The method of claim 12, further comprising calculating a parasitic resistance value for the conductor.
- 14. The method of claim 13, further comprising calculating a parasitic capacitance value for the conductor.
- 15. The method of claim 12, further comprising:
calculating an effective dielectric constant for an environment of the conductor; calculating a second inductance value for the conductor using the parasitic capacitance value for the conductor, the effective dielectric constant for the environment of the conductor and the speed of light; comparing the inductance value to the second inductance value; and in response to a determination that the inductance value differs from the second inductance value by more than a preselected difference factor, correcting the inductance value to correspond to the second inductance value.
- 16. The method of claim 12, wherein determining the distance to the current return path for the conductor comprises receiving an identification of the current return path from a user.
- 17. The method of claim 12, further comprising:
accessing a technology profile by an interconnect library builder, the technology profile including values of physical parameters characterizing a plurality of conducting and dielectric layers of the integrated circuit; and formulating by the interconnect library builder an inductance function for at least one of the conducting layers including the conductor using the physical parameter values from the technology profile; wherein calculating the inductance value for the conductor using the current return path comprises using the inductance function for the at least one conducting layer including the conductor to calculate the inductance value for the conductor.
- 18. The method of claim 17, wherein formulating the inductance function by the interconnect library builder comprises:
determining a plurality of inductance values for at least one of the conducting layers including the conductor using a plurality of different values for at least one conductor parameter; and storing the plurality of inductance values and the plurality of different values for the at least one conductor parameter in an inductance table.
- 19. The method of claim 17, wherein formulating the inductance function by the interconnect library builder comprises:
determining a plurality of inductance values for at least one of the conducting layers including the conductor using a corresponding plurality of different values for a circuit operating frequency; and storing the plurality of inductance values and the corresponding plurality of different values for the circuit operating frequency in an inductance table.
- 20. The method of claim 19, wherein calculating the inductance value for the conductor further comprises
receiving an actual circuit operating frequency; comparing the actual circuit operating frequency to the plurality of different values for the circuit operating frequency stored in the inductance table; calculating the inductance value for the conductor using the plurality of inductance values corresponding to the plurality of different values for the circuit operating frequency stored in the inductance table.
- 21. The method of claim 14, further comprising creating a circuit description for the conductor using the inductance value, the parasitic capacitance value and the parasitic resistance value.
- 22. The method of claim 21, wherein creating the circuit description for the conductor comprises creating an RLC circuit description as a model for the conductor.
- 23. The method of claim 21, wherein creating the circuit description for the conductor comprises:
changing at least one of the parasitic capacitance value and the parasitic resistance value for the conductor in response to the inductance value; and creating an equivalent RC circuit description as a model for the conductor.
- 24. A parasitic extraction system for extracting parasitic impedances from an integrated circuit layout description, comprising:
an interconnect primitive library including a parameterized inductance function for at least one conducting layer of the integrated circuit; and a parasitic extractor operable to analyze structures within a selected distance of a selected conductor within the integrated circuit, and operable to determine parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library.
- 25. The parasitic extraction system of claim 24, further comprising:
a technology profile including values of physical parameters characterizing a plurality of conducting and dielectric layers of the integrated circuit; and an interconnect library builder operable to create the parameterized inductance function of the interconnect primitive library using the technology profile.
CROSS-REFERENCE TO RELATED PATENT
[0001] This application is related to U.S. Pat. No. 5,901,063.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09350966 |
Jul 1999 |
US |
Child |
10057165 |
Jan 2002 |
US |