The present invention relates to improved techniques for encrypting and decrypting data.
The need for effective and efficient data encryption/decryption is widespread throughout today's world. Whether it be data maintained by a governmental agency that pertains to national security or data maintained by a private company that pertains to the company's trade secrets and/or confidential information, the importance of effective and efficient encryption/decryption cannot be understated.
Effective encryption/decryption is needed to preserve the integrity of the subject data. Efficient encryption/decryption is needed to prevent the act of encrypting/decrypting the subject data from becoming an overwhelming burden on the party that maintains the subject data. These needs exist in connection with both “data at rest” (e.g., data stored in nonvolatile memory) and “data in flight” (e.g., data in transit from one point to another such as packet data transmitted over the Internet).
A number of data encryption/decryption techniques are known in the art. Many of these encryption techniques utilize a block cipher (see, e.g., block cipher 100 in
As an example of one such known mode of encryption/decryption, the electronic codebook (ECB) mode of encryption/decryption is commonly used due to its simplicity and high data throughput. Examples of the ECB mode of encryption/decryption are shown in
With ECB, the lack of sequential blockwise dependency in the encryption/decryption (i.e., feedback loops where the encryption of a given plaintext block depends on the result of encryption of a previous plaintext data block) allows implementations of the ECB mode to achieve high data throughput via pipelining and parallel processing techniques. While ECB exhibits these favorable performance characteristics, the security of ECB's encryption is susceptible to penetration because of the propagation of inter-segment and intra-segment uniformity in the plaintext to the ciphertext blocks.
For example, a 256 bit segment of plaintext containing all zeros that is to be encrypted with a 64 bit block cipher using ECB will be broken down into 4 64-bit blocks of plaintext, each 64-bit plaintext block containing all zeros. When operating on these plaintext blocks, ECB will produce a segment of ciphertext containing four identical blocks. This is an example of intra-segment uniformity. Furthermore, if another such 256-bit all zero segment is encrypted by ECB using the same key, then both of the resulting ciphertext segments will be identical. This is an example of inter-segment uniformity. In instances where intra-segment and/or inter-segment uniformity is propagated through to ciphertext, the security of the ciphertext can be compromised because the ciphertext will still preserve some aspects of the plaintext's structure. This can be a particularly acute problem for applications such as image encryption.
To address intra-segment and inter-segment uniformity issues, there are two commonly-used approaches. One approach is known as cipher block chaining (CBC). An example of the CBC mode of encryption/decryption is shown in
As shown in
Preferably, the reversible combinatorial operation 210 is an XOR operation performed between the bits of the vector 200 and the block 102. The truth table for an XOR operation between bits X and Y to produce output Z is as follows:
As is well known, the XOR operation is reversible in that either of the inputs X or Y can be reconstructed by performing an XOR operation between Z and the other of the inputs X or Y. That is, if one XORs X with Y, the result will be Z. If one thereafter XORs Z with Y, then X will be reconstructed. Similarly, if one thereafter XORs Z with X, then Y will be reconstructed.
Thus, on the decryption side, the CBC mode operates to decrypt ciphertext block 202 with the cipher block 100 using key 114 to thereby reconstruct the XOR combination of plaintext data block 102 and the initialization vector 200. Thereafter, this reconstructed combination can be XORed with the initialization vector 200 to reconstruct plaintext block 102. Next, at time t=t1, the process is repeated for the next ciphertext block 204, although this time the XOR operation will be performed using ciphertext block 202 (rather than initialization vector 200) to reconstruct plaintext data block 104. Ciphertext block 202 is used in this XOR operation because it was ciphertext block 202 that was used in the XOR operation when plaintext block 104 was encrypted. Then, once again this process is repeated at time t=t2, albeit with ciphertext block 204 being used for the XOR combination operation with the output from cipher block 100.
While the use of feedback by the CBC mode addresses the issue of inter-segment and intra-segment uniformity, such feedback imposes a sequential processing flow on the encryption that significantly limits the achievable throughput of the encryption engine. As such, the CBC mode cannot make ready use of pipelining because one of the inputs for the reversible combinatorial operation stage 210 of the encryption for a given data block depends upon the output of the cipher block stage 100 of the encryption performed on the previous data block. That is, because of the feedback, the reversible combinatorial operation stage in a CBC encryption engine must wait for the block cipher to complete its encryption of a given data block-bit vector combination before it can begin to process the next data block.
Furthermore, on the decryption side, the CBC mode's dependence on the sequential order of data block encryption can raise problems when one wants to retrieve only a portion of the encrypted data segment. For example, for a data segment that comprises data blocks DB1 through DB20, when that data segment is encrypted and stored for subsequent retrieval in its encrypted form, an instance may arise where there is a need to retrieve data blocks DB6 through DB10, wherein the other data blocks of the data segment are not needed. However, to be able to successfully decrypt data blocks DB6 through DB10, the retrieval operation and decryption operation will nevertheless need to operate on data blocks DB1 through DB5 so that decryption can be performed for data blocks DB6 through DB10.
Furthermore, when used for disk encryption, the CBC mode may be vulnerable to a “watermark attack” if the initialization vector 200 is not kept secret (such as may be the case when the initialization vector is derived from a quantity such as a disk volume number). With such an attack, an adversary can determine from the output ciphertext whether or not a specially crafted file is stored. While there are solutions to such an attack (such as using hashing to derive the initialization vector from the data blocks in the sector), these solutions add to the computational complexity of the encryption operation and thus further degrade the throughput and/or increase the computational resources required for the encryption.
A second approach is known as the Segmented Integer Counter (SIC) mode, or more succinctly the counter (CTR) mode.
As shown in
On the decryption side, this process can then be reversed where the combination blocks 302, 304 and 306 are decrypted by block cipher 100 using key 114, with the respective outputs therefrom being XORed with the ciphertext blocks 322, 324 and 326 respectively to reconstruct plaintext blocks 102, 104 and 106.
The SIC/CTR mode of encryption/decryption also suffers from a security issue if data segments are always encrypted with the same random value 300. If an adversary is able to gather several versions of the encrypted data segment, it would be possible to derive information about the plaintext because the cipher text (C) is simply the XOR of the variable (V) based on the random number and the plaintext (P), e.g., C=P⊕V, thus C⊕C′=P⊕P′.
Therefore, the inventors herein believe that a need exists in the art for a robust encryption/decryption technique that is capable of reducing both inter-segment and intra-segment uniformity while still retaining high throughput and exhibiting blockwise independence. As used herein, an encryption operation for a data segment is said to be “blockwise independent” when the encryption operations for each data block of that data segment do not rely on the encryption operation for any of the other data blocks in that data segment. Likewise, a decryption operation for a data segment is said to be “blockwise independent” when the decryption operations for each encrypted data block of that data segment do not rely on the decryption operation for any of the other data blocks in that data segment.
Toward this end, in one embodiment, the inventors herein disclose a technique for encryption wherein prior to key encryption, the plaintext data block is combined with a blockwise independent bit vector using a reversible combinatorial operation to thereby create a plaintext block-vector combination. This plaintext block-vector combination is then key encrypted to generate a ciphertext block. This process is repeated for all data blocks of a data segment needing encryption. For decryption of the cipher text blocks produced by such encryption, the inventors herein further disclose an embodiment wherein each ciphertext data block is key decrypted to reconstruct each plaintext block-vector combination. These reconstructed plaintext block-vector combinations can then be combined (using the reversible combinatorial operation) with the corresponding randomized bit vectors that were used for encryption to thereby reconstruct the plaintext blocks.
As an improvement relative to the CBC mode of encryption/decryption, each bit vector is blockwise independent. A bit vector is said to be blockwise independent when the value of that bit vector does not depend on any results of an encryption/decryption operation that was performed on a different data block of the data segment. Because of this blockwise independence, this embodiment is amenable to implementations that take advantage of the power of pipelined processing and/or parallel processing.
Moreover, because of the blockwise independent nature of the encryption performed by the present invention, a subset of the encrypted data segment can be decrypted without requiring decryption of the entire data segment (or at least without requiring decryption of the encrypted data blocks of the data segment that were encrypted prior to the encrypted data blocks within the subset). Thus, for a data segment that comprises data blocks DB1 through DB20, when that data segment is encrypted and stored for subsequent retrieval in its encrypted form using the present invention, a need may arise to retrieve plaintext versions of encrypted data blocks DB6 through DB10 and DB15, wherein the other data blocks of the data segment are not needed in their plaintext forms. A preferred embodiment of the present invention supports successful decryption of a subset of data blocks within the encrypted data segment (e.g., data blocks DB6 through DB10 and DB15) without requiring the decryption of the data segment's data blocks that are not members of the subset (e.g., data blocks DB1 through DB5, data blocks DB11 through DB14 and data blocks DB16 through DB20). Accordingly, the present invention supports the decryption of any arbitrary subset of the encrypted data blocks of a data segment without requiring decryption of any data blocks that are non-members of the arbitrary subset even if those non-member data blocks were encrypted prior to the encryption of the data blocks within the arbitrary subset.
Similarly, even if an entire encrypted data segment is to be decrypted, the present invention supports the decryption of the encrypted data blocks in a block order independent manner. Further still, the present invention supports the encryption of data blocks in a block order independent manner as well as supports limiting the encryption to only a defined subset of a data segment's data blocks (wherein such a subset can be any arbitrary subset of the data segment's data blocks).
Furthermore, as an improvement relative to the SIC/CTR mode of encryption/decryption, a greater degree of security is provided by this embodiment because the data that is subjected to key encryption includes the plaintext data (whereas the SIC/CTR mode does not subject the plaintext data to key encryption and instead subjects only its randomized bit vector to key encryption).
Preferably, the blockwise independent bit vector is a blockwise independent randomized (BIR) bit vector. As is understood by those having ordinary skill in the art, randomization in this context refers to reproducible randomization in that the same randomized bit vectors can be reproduced by a bit vector sequence generator given the same inputs. Further still, the blockwise independent randomized bit vector is preferably generated from a data tag that is associated with the data segment needing encryption/decryption. Preferably, this data tag uniquely identifies the data segment. In a disk encryption/decryption embodiment, this data tag is preferably the logical block address (LBA) for the data segment. However, it should be noted that virtually any unique identifier that can be associated with a data segment can be used as the data tag for that data segment. It should also be noted that rather than using a single data tag associated with the data segment, it is also possible to use a plurality of data tags that are associated with the data segment, wherein each data tag uniquely identifies a different one of the data segment's constituent data blocks
A bit vector generation operation preferably operates on a data tag to generate a sequence of blockwise independent bit vectors, each blockwise independent bit vector for reversible combination with a corresponding data block. Disclosed herein are a plurality of embodiments for such a bit vector generation operation. As examples, bit vectors can be derived from the pseudo-random outputs of a pseudo-random number generator that has been seeded with the data tag; including derivations that employ some form of feedback to enhance the randomness of the bit vectors. Also, linear feedback shift registers and adders can be employed to derive the bit vectors from the data tag in a blockwise independent manner.
The inventors also disclose a symmetrical embodiment of the invention wherein the same sequence of operations are performed on data in both encryption and decryption modes.
One exemplary application for the present invention is to secure data at rest in non-volatile storage; including the storage of data placed on tape, magnetic and optical disks, and redundant array of independent disks (RAID) systems. However, it should be noted that the present invention can also be applied to data in flight such as network data traffic.
These and other features and advantages of the present invention will be apparent to those having ordinary skill in the art upon review of the following description and figures.
a) and (b) depict an embodiment of the present invention in both encryption and decryption modes;
a) and (b) depict exemplary encryption and decryption embodiments of the present invention;
a) and (b) depict exemplary encryption and decryption embodiments of the present invention showing their operations over time;
a)-(c) depict three additional exemplary embodiments of a bit vector sequence generator;
a) and (b) depict exemplary encryption and decryption embodiments of the present invention that are hybrids of the embodiments of
c) and (d) depict exemplary embodiments of the bit vector sequence generator for use with the hybrid embodiments of
a) and (b) depict an exemplary embodiment for symmetrical encryption/decryption in accordance with the present invention;
a) and (b) depict an exemplary embodiment for symmetrical encryption/decryption in accordance with the present invention wherein the blockwise independent bit vectors are derived from the data segment's LBA;
a) and (b) depict the embodiment of
c) and (d) depict a symmetrical encryption/decryption counterpart to the embodiments of
a) and (b) depict exemplary hardware environments for the present invention; and
a)-(c) depict exemplary printed circuit boards on which the encryption/decryption embodiments of the present invention can be deployed.
a) illustrates an embodiment of the present invention wherein the encryption operation is segmented into a plurality of stages. At stage 504, the blockwise independent bit vector 506 is generated, preferably from a data tag 502 that is associated with the data segment 400. Preferably, the bit vector 506 has a length that is the same as the data blocks of the data segment, although this need not be the case. Further still, it is preferred that the blockwise independent bit vector 506 have a randomized value to thereby enhance the security of the encryption. Also, it is preferred that a different bit vector 506 be generated for each data block of a data segment that is encrypted, although this need not be the case. The bit vectors that are used in the encryption of a data segment's data blocks should be either stored for subsequent use when it is time to decrypt one or more of the data segment's data blocks or should be reproducible from a known quantity (such as the data tag) when it is time to decrypt one or more of the data segment's data blocks.
At stage 210, a reversible combinatorial operation such as a bitwise XOR operation is performed on the blockwise independent bit vector 506 and plaintext data block. This reversible combinatorial operation preferably produces a data block-bit vector combination 508.
At stage 100, a block cipher performs an encryption operation on the data block-bit vector combination 508 using key 114 as per well-known key encryption techniques (e.g., AES, the Data Encryption Standard (DES), the triple DES (3DES), etc.). The output of the block cipher stage 100 is thus a ciphertext data block that serves as the encrypted counterpart to the plaintext data block that was fed into stage 210. It should be noted that any of several well-known key management techniques can be used in connection with managing the key(s) 114 used by the block cipher(s) 100. As such, the inventors do not consider the key management for the block cipher(s) 100 to be any limitation on the present invention. It should also be noted that “keyless” encryption techniques may also be used in the practice of the present invention (e.g., substitution ciphers that do not require a key).
b) depicts the decryption counterpart to
As can be seen in
The data tag 502 may be any data value(s) that can be associated with the data segment 400. Preferably, the data tag 502 serves as a unique identifier for the data segment 400, although this need not be the case. A preferred data tag 502 is the logical block address (LBA) for the data segment to be encrypted. An LBA for a data segment is the logical memory address for the data segment that is typically assigned by an Operating System (OS) or memory management system. However, other data tags may be used in the practice of the present invention; examples of which include file identifiers, physical memory addresses, and packet sequence numbers. The source of the data tag can be any of a variety of sources, including but not limited to communication protocol, storage subsystem, and file management systems.
a) and (b) illustrate embodiments of the invention where the data segment's LBA is used as the data tag 502 for the encryption/decryption operations. Sequence generator 600 processes the LBA to produce a different blockwise independent randomized bit vector 506 for XOR combination (210) with each plaintext data block. On decryption (shown in
a) illustrates the embodiment of
b) depicts the decryption counterpart to
As can be seen, the sequence of bit vectors 5061, 5062, . . . 506n produced by the sequence generator 600 of
It should also be noted that if the encryption/decryption technique involves using a data tag that is unique to each data block to generate each data block's corresponding blockwise independent bit vector 506, the need to pause operations while cycling through unneeded bit vectors can be eliminated.
a)-(c) depict other examples of sequence generator embodiments.
b) discloses a sequence generator 600 that uses the LBA 502 to seed a linear feedback shift register (LFSR) 1000 whose outputs then serve as the bit vectors 506 for combination with the data segment's data blocks.
c) discloses a sequence generator 600 that uses the LBA 502 to seed a feedback counter 1002, wherein the feedback counter 1002 has a constant increment 1004, and wherein the counter's outputs then serve as the bit vectors 506 for combination with the data segment's data blocks. As with the embodiments of
Data Tag′=Data Tag+k*Constant
wherein Data Tag′ represents the value of the data tag 502 that is fed into the sequence generator 600, wherein Data Tag represents the value of the data tag that is associated with the data segment, wherein k represents the block number within the data segment of the data block to be encrypted/decrypted, and wherein Constant represents the value of the incremental constant 1004 for adder 1002. This computation can be performed either within the sequence generator (in which case it will be the value Data Tag that is fed into the sequence generator 600) or in a module upstream from the sequence generator. Appropriate control logic is preferably used to control whether the multiplexer passes the data tag value 502 or the output of adder 1002 on to the reversible combinatorial stage 210.
It should also be noted that the present invention need not be limited to a single combination of a blockwise independent bit vector randomizer and a block cipher. Pairs of sequence generators 600, reversible combinatorial operations 210, and block ciphers 100 can be sequentially chained as shown in
Further still, the inventors herein disclose an embodiment that hybridizes the present invention and the CBC mode of encryption/decryption.
c) and (d) depict exemplary embodiments of a sequence generator 600′ that could be used to generate bit vectors for the embodiments of
d) depicts another exemplary embodiment for the sequence generator 600′. In the example of
As another embodiment of the present invention, the inventors disclose a symmetrical embodiment for encryption/decryption. With “symmetrical” encryption/decryption, the same order of operations can be performed on data blocks to both encrypt and decrypt those data blocks. Thus, with a symmetrical embodiment, the same module that is used to encrypt data can be used to decrypt encrypted data.
As shown in
For decryption, as shown in
Timing logic (not shown) can be employed to synchronize the outputs of bit vectors 506 from the bit vector generation stage 504 such that the appropriate bit vector 506 is fed to the second reversible combinatorial stage 1302 for each block ciphered data block-bit vector combination 1304 (or reconstructed data block-bit vector combination 508 for the decryption mode) that is processed thereby. Such synchronization could be designed to accommodate the latency within the block cipher 100 to thereby allow the same bit vector 506 to be used for reversible combination with a given data block by first reversible combinatorial operation stage 210 as is used for later reversible combination with the block ciphered data block-bit vector combination 1304 derived from that given data block by the second reversible combinatorial operation stage 1302.
a) (for encryption mode) and
a) (for encryption mode) and
It should also be noted that the symmetrical encryption/decryption embodiments described herein can also be used in a hybrid CBC embodiment like the ones shown in
As a further embodiment of the present invention, the inventors note that a parallel architecture 1600 such as the one shown in
The encryption/decryption techniques of the present invention can be implemented in a variety of ways including but not limited to a software implementation on any programmable processor (such as general purpose processors, embedded processors, network processors, etc.), a hardware implementation on devices such as programmable logic devices (e.g., field programmable gate arrays (FPGAs)), ASICs, and a hardware and/or software implementation on devices such as chip multi-processors (CMPs), etc. For example, some CMPs include built-in hardware for encryption ciphers, in which case software on parallel processors systems for the CMPs could perform the bit vector generation and reversible combinatorial tasks while offloading the block cipher operations to the dedicated hardware.
However, the inventors herein particularly note that the present invention is highly amenable to implementation in reconfigurable logic such as an FPGA. Examples of suitable FPGA platforms for the present invention are those described in the following: U.S. patent application Ser. No. 11/339,892 (filed Jan. 26, 2006, entitled “Firmware Socket Module for FPGA-Based Pipeline Processing” and published as 2007/0174841), published PCT applications WO 05/048134 and WO 05/026925 (both filed May 21, 2004 and entitled “Intelligent Data Storage and Processing Using FPGA Devices”), U.S. patent application Ser. No. 10/153,151 (filed May 21, 2002 entitled “Associative Database Scanning and Information Retrieval using FPGA Devices”, published as 2003/0018630, now U.S. Pat. No. 7,139,743), and U.S. Pat. No. 6,711,558 (entitled “Associative Database Scanning and Information Retrieval”), the entire disclosures of each of which are incorporated by reference herein.
a) depicts an example of an implementation environment for the present invention.
Data flowing to or from data store 1704 can be routed through reconfigurable logic device 1702 (which may be embodied by an FPGA). One or more firmware application modules (FAMs) 1730 are deployed on the reconfigurable logic using the techniques described in the above-incorporated references. The different stages of the encryption/decryption engine of the present invention can be implemented on the reconfigurable logic device 1702 as a processing pipeline deployed on one or more of these FAMs 1730. Firmware socket module 1720 can be implemented as described in the incorporated Ser. No. 11/339,892 patent application to control the flow of data to and from the encryption/decryption engine(s) deployed on the reconfigurable logic device 1702 via communication paths 1732 and 1734. Data to be encrypted and stored in the data store can be routed through the reconfigurable logic device 1702 along with appropriate control instructions for the encryption. Such control information can include the data tag used to generate the blockwise independent bit vectors. Moreover, these control instructions can emanate from any source with access to system bus 1712 including sources that connect to the system bus 1712 over a network. For example, in an embodiment wherein the data segment's LBA is used as the data tag from which the bit vectors are generated, the LBA can be passed to the FAM pipeline 1730 with the data from the data store 1704 or it can be passed to the FAM pipeline 1730 from processor 1708. Moreover, the data segments to be encrypted can emanate from any source with access to the reconfigurable logic device 1702. Encrypted data to be decrypted can also be routed through the reconfigurable logic device 1702 along with appropriate control instructions for the decryption.
Thus, when encrypting a data segment to be stored at an LBA of the data store 1704, the data blocks of the data segment can be streamed through a FAM 1730 on reconfigurable logic device 1702 that is configured to perform encryption in accordance with the teachings of the present invention (with the encryption FAM 1730 preferably deriving the blockwise independent bit vectors 506 from the LBA). The resultant ciphertext produced by the encryption FAM 1730 can then be stored in data store 1704 starting at the LBA. On decryption, the ciphertext data blocks of the encrypted data segment (or a subset thereof) can be streamed through a decryption FAM 1730 (or a symmetrical encryption/decryption FAM 1730) to reconstruct the plaintext data segment (or subset thereof). Once again, in an embodiment wherein the blockwise independent bit vectors are derived form the data segment's LBA, the LBA can also be used as the source of the bit vectors used during the decryption process.
It should also be noted that for disk or file encryption operations, it may be desirable to include the platform (e.g., FPGA or ASIC) on which the encryption/decryption engine of the present invention is deployed (or the encryption/decryption engine itself) on-board the disk controller 1706. It may also be desirable for the encryption/decryption engine to receive all data streaming to/from the disk(s), in which case control information could be added to the data streams to inform the encryption/decryption engine of which data is to be encrypted/decrypted and which data is to be passed through without modification. For example, such control information can take the form of a flag within a data set's SCSI control block (SCB).
The embodiment of
a) depicts a printed circuit board or card 1800 that can be connected to the PCI-X bus 1712 of a computer system (e.g., a commodity computer system or other) for use in encrypting/decrypting data. In the example of
b) depicts an alternate configuration for a printed circuit board/card 1800. In the example of
c) depicts another alternate configuration for a printed circuit board/card 1800. In the example of
It should be further noted that the printed circuit board/card 1800 may also be configured to support both a disk controller/connector 1810/1812 and a network interface controller/connector 1820/1822 to connect the board 1800 to disk(s) and network(s) via private PCI-X bus 1808, if desired by a practitioner of the invention.
It is worth noting that in either of the configurations of
Exemplary applications for the present invention include but are not limited to general purpose data encryption (e.g., files, images, documents, etc.), disk encryption, streaming message (e.g., packets, cells, etc.) encryption, and streaming image encryption (e.g., streaming reconnaissance imagery, etc.).
While the present invention has been described above in relation to its preferred embodiment, various modifications may be made thereto that still fall within the invention's scope. Such modifications to the invention will be recognizable upon review of the teachings herein. As such, the full scope of the present invention is to be defined solely by the appended claims and their legal equivalents.
This application is a continuation of U.S. patent application Ser. No. 13/759,227, filed Feb. 5, 2013, and entitled “Method and System for High Throughout Blockwise Independent Encryption/Decryption”, now U.S. Pat. No. 8,737,606, which is a continuation of U.S. patent application Ser. No. 11/690,034, filed Mar. 22, 2007, and entitled “Method and System for High Throughout Blockwise Independent Encryption/Decryption”, now U.S. Pat. No. 8,379,841, which claims priority to provisional patent application 60/785,821, filed Mar. 23, 2006, and entitled “Method and System for High Throughput Blockwise Independent Encryption/Decryption”, the entire disclosures of each of which are incorporated herein by reference.
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Number | Date | Country | |
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60785821 | Mar 2006 | US |
Number | Date | Country | |
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Parent | 13759227 | Feb 2013 | US |
Child | 14279856 | US | |
Parent | 11690034 | Mar 2007 | US |
Child | 13759227 | US |