This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0089031, filed on Jul. 19, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The inventive concepts relate to structure measurement, and more particularly, to a method and system for measuring a structure, based on a spectrum.
Due to advances in semiconductor processes, an integrated circuit may have a high degree of integration and may include a complex structure. For verification of an integrated circuit manufactured by a semiconductor process, measuring a structure included in the integrated circuit may require a lot of time and high costs, and may require destruction of the integrated circuit. Accordingly, a method of effectively measuring a structure included in an integrated circuit without destroying the integrated circuit may be beneficial.
The inventive concepts provide a method and system for effectively measuring a structure, based on a spectrum.
According to an aspect of the inventive concepts, there is provided a method for measuring a structure based on a spectrum of the structure, the method including obtaining a first model trained based on simulation data, the first model including a first sub-model and a second sub-model following the first sub-model, generating a second model such that the second model includes a third sub-model generated from at least a portion of the first sub-model, training the second model based on sample spectrum data generated by measuring spectra of sample structures, and estimating, based on the trained second model, the structure from measured spectrum data generated by measuring the spectrum of the structure.
According to another aspect of the inventive concepts, there is provided a system including at least one processor and a non-transitory storage medium storing instructions which, when executed by the at least one processor, instruct the at least one processor to perform measurement of a structure based on a spectrum of the structure. The measurement of the structure includes obtaining a first model trained based on simulation data, the first model including a first sub-model and a second sub-model following the first sub-model, generating a second model such that the second model includes a third sub-model generated from at least a portion of the first sub-model, and estimating, based on the trained second model, the structure from measured spectrum data generated by measuring the spectrum of the structure.
According to another aspect of the inventive concepts, there is provided a non-transitory storage medium storing instructions which, when executed by at least one processor, instruct the at least one processor to perform measurement of a structure based on a spectrum of the structure, wherein the measurement of the structure includes obtaining a first model trained based on simulation data, the first model including a first sub-model and a second sub-model following the first sub-model, generating a second model such that the second model includes a third sub-model generated from at least of portion of the first sub-model, training the second model based on sample spectrum data generated by measuring spectra of sample structures, and estimating, based on the trained second model, the structure from measured spectrum data generated by measuring the spectrum of the structure.
According to another aspect of the inventive concepts, there is provided a method for measuring a structure based on a spectrum, the method including obtaining a first model trained based on simulation data, the first model including a first sub-model and a second sub-model following the first sub-model, generating a second model based on the first model, training the second model based on sample spectrum data generated by measuring spectra of sample structures, verifying the trained second model based on output data of the first model and output data of the trained second model, and estimating, based on the verified second model, the structure from measured spectrum data generated by measuring the spectrum of the structure.
Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing tolerance (e.g., ±10%) around the stated numerical value. Further, regardless of whether numerical values are modified as “about” or “substantially,” it will be understood that these values should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values.
The wafer W may be manufactured by a semiconductor process and may include a plurality of dies. As a semiconductor process develops, the size of a die may decrease and/or the degree of integration of devices included in the die may increase. Accordingly, the die may include a small-sized structure and/or may include a complex structure. In order to verify the die (e.g., to determine whether the die manufactured by the semiconductor process has a designed structure) the structure included in the die may be measured. For example, the die may include a device, such as a transistor, and the gate (and/or the like) of the transistor may be measured. The die may include patterns respectively formed on a plurality of wiring layers, and, for example, widths of the patterns and spacing between the patterns may be measured. In at least one example, the semiconductor process may be designed such that all of the dies included in the wafer W have the same structures, but variations may occur between the wafers due to various factors and may occur between the dies included in the wafer W.
Directly measuring the structure of a die by using, e.g., a scanning electron microscope (SEM) or transmission electron microscope (TEM) may take a lot of time and accrue high costs, and thus may impair the efficiency of a semiconductor process. Additionally, measuring a structure included within a die may require destruction of the die. The spectrum may be utilized to efficiently measure the structure included in the die and perform non-destructive testing. For example, a light beam may be radiated to the wafer W, and the structure included in the die may be estimated based on the spectrum generated by the radiated light beam. Machine learning may be used to estimate the structure from the spectrum, and the accuracy of the structure measurement 10 based on the spectrum may depend on the accuracy of machine learning.
In at least one embodiment, spectrum acquisition equipment 12 may irradiate the wafer W with a light beam and may obtain the spectrum generated by the light beam. According to at least one embodiment, the spectrum acquisition equipment 12 may acquire a spectrum reflected from the wafer W and/or may acquire a spectrum penetrated by the wafer W. The spectrum acquisition equipment 12 may, for example, include a light source (e.g., a laser, a plurality of lasers, a light emitting diode, an ultraviolet (UV) source, etc.) and a photoreceptor (e.g., a photodiode, a camera, etc.). As shown in
The measurement system 14 may receive the spectrum data SPC from the spectrum acquisition equipment 12 and may generate dimension data DIM representing a structure corresponding to the spectrum of the spectrum data SPC. For example, the dimension data DIM may include a value representing the size of a structure included in the die. According to at least one embodiment, the measurement system 14 may be implemented by a computing system (or referred to as a computer system) that will be described later with reference to
Referring to
The machine learning model ML may be used to generate the dimension data DIM from the spectrum data SPC. For example, the dimension data DIM may be generated by processing (e.g., transforming and/or interpreting) output data of the machine learning model ML. Herein, the machine learning model ML included in the measurement system 14 may be referred to as a second model. As described above, measuring a die may require a lot of time and high costs, and thus, measured data for training the machine learning model ML may be limited.
As will be described later with reference to the drawings, the machine learning model ML may be generated and trained based on a model trained based on simulation data. The machine learning model ML may also be trained so that the output data follows the physics of the structure. Accordingly, the machine learning model ML for accurately estimating the structure of the die from the spectrum may be provided, the structure may be accurately measured without destroying the die, and the reliability of the integrated circuit may be improved. In addition, the semiconductor process may be easily adjusted or redesigned due to the efficiently measured structure, and thus, the productivity of the integrated circuit may be improved. According to at least one embodiment, production and training of the measurement system 14 may be implemented by a computing system that will be described later with reference to
Referring to
In operation S400, the second model may be generated. As described above with reference to
In operation S600, the second model may be trained. For example, as shown in
In operation S800, the structure may be estimated. For example, as shown in
As shown in
The second sub-model ML2 may process the data received from the first sub-model ML1 and may generate the output data D33. For example, the second sub-model ML2 may function as a regressor for estimating a structure from the feature indicated by the data provided by the first sub-model ML1. Accordingly, the output data D33 may include information about a virtual structure, for example, a value indicating the size of the virtual structure. According to at least one embodiment, the output data D33 may be used to train the second model 32, as will be described later with reference to
As shown in
The fourth sub-model ML4 may process the data received from the third sub-model ML3 and may generate the output data D37. For example, the fourth sub-model ML4 may function as a regressor for estimating a structure from the feature indicated by the data provided by the third sub-model ML3. Accordingly, the output data D37 may include information about the structure, for example, a value indicating the size of the structure. According to at least one embodiment, the fourth sub-model ML4 may have the same structure as the second sub-model ML2 of the first model 31. An example of the fourth sub-model ML4 will be described later with reference to
Referring to
According to at least one embodiment, each of the first sub-model ML1 and the third sub-model ML3 of
Referring to
In operation S240, the first model 31 may be trained. For example, the virtual spectrum data generated in operation S220 may be provided to the first model 31, and the first model 31 may be trained based on, e.g., the output data D33 of the first model 31 and the virtual structure data. According to at least one embodiment, the first model 31 may be trained to reduce an error between the output data D33 and the virtual structure data. For example, a loss function proportional to the error between the output data D33 and the virtual structure data may be defined, and the first model 31 may be trained so that a value of the loss function decreases.
In operation S260, the first model 31 may be verified. For example, the first model 31 may be verified based on the error between the output data D33 and the virtual structure data. According to at least one embodiment, the loss function proportional to the error between the output data D33 and the virtual structure data may be defined, and, when the value of the loss function decreases to no more than a predefined (or otherwise determined) threshold, the verification of the first model 31 may succeed.
In operation S280, it may be determined whether the verification of the first model 31 has succeeded or failed. As shown in
Referring to
In operation S440, the fourth sub-model ML4 may be generated. As described above with reference to
Referring to
The first sub-model ML1 for extracting the representation from the virtual spectrum may be used to extract a representation from a measured spectrum. For example, as shown in
Referring to
In operation S640, the fourth sub-model ML4 may be trained. As described above with reference to
In operation S660, the second model 32 may be verified. According to at least one embodiment, the second model 32 may be verified based on the measured data. According to at least one embodiment, the second model 32 may be verified based on the output data D33 of the first model 31. An example of operation S660 will be described later with reference to
In operation S680, it may be determined whether the verification of the second model 32 succeeds or fails. As shown in
Referring to
L
0(g)=MSE(g(xHW),yHW) [Equation 1]
In Equation 1, g indicates the second model 32, xHW indicates measured spectrum data, yHW indicates measured structure data, and MSE indicates a mean squared error.
In operation S664, the second model 32 may be verified based on the output data D33 of the first model 31. When the second model 32 is trained based on a loss function, such as Equation 1, as will be described later with reference to
Referring to
Referring to
In operation S664_2, first output data and second output data may be obtained from the first model 31. For example, the first sample may be provided to the first model 31, and the first model 31 may generate first output data corresponding to the first sample. The second sample may be provided to the first model 31, and the first model 31 may generate second output data corresponding to the second sample.
In operation S664_3, a first relationship between the first output data and the second output data may be identified. When the first sample and the second sample extracted in operation S664_1 have a specific relationship, the first output data and the second output data (corresponding to the first sample and the second sample, respectively) may have the first relationship in order to comply with the physics. For example, the first relationship may mean that the second output data is greater than the first output data as in Equation 2 below.
f(xi)<f(xj) [Equation 2]
In Equation 2, f indicates the first model 31, xi indicates the first sample, and xj indicates the second sample. As will be described later, the second model 32 may be verified based on whether a second relationship identified from the second model 32 corresponds to the first relationship.
In operation S664_4, third output data and fourth output data may be obtained from the second model 32. For example, the first sample may be provided to the second model 32, and the second model 32 may generate third output data corresponding to the first sample. The second sample may be provided to the second model 32, and the second model 32 may generate fourth output data corresponding to the second sample.
In operation S664_5, a second relationship between the third output data and the fourth output data may be identified. For example, the second relationship may be a relationship between the third output data and the fourth output data.
In operation S664_6, the second model 32 may be verified based on the first relationship and the second relationship. For example, when the first relationship and the second relationship have the same (or substantially similar) properties, verification of the second model 32 may be determined to have succeeded, and, when the first relationship and the second relationship do not have the same (or substantially similar) properties, it may be determined that the verification of the second model 32 has failed. For example, when the first relationship is identified as in Equation 2 and the second relationship is defined as Equation 3 below, it may be determined that the verification of the second model 32 succeeds, in operation S664′.
g(xi)<g(xj) [Equation 3]
According to at least one embodiment, the second model 32 may be trained to comply with the physics. For example, the second model 32 may be trained such that a loss proportional to an error (e.g., a degree to which the second relationship deviates from the first relationship) between the first relationship and the second relationship decreases. For example, the loss function may be defined to increase when the output data D37 of the second model 32 does not comply with the physics. According to at least one embodiment, a loss function L for training the second model 32 may be defined as in Equation 4 below, and the second model 32 may be trained to decrease the loss function L.
In Equation 4, λ indicates a weight and is a positive real number less than 1 (0<λ<1), and a value of a rectified Linear Unit (ReLU) function may be 0 when g(xi)-g(xj) is zero or negative and may be g(xi)-g(xj) when g(xi)-g(xj) is positive. Thus, when the second relationship obeys the first relationship, the value of the ReLU function may be zero, whereas, when the second relationship does not obey the first relationship, the ReLU function may have a value proportional to a degree to which the second relationship deviates from the first relationship.
A semiconductor process for manufacturing the wafer W may include a series of sub-processes. For example, a front-end-of-line (FEOL) may include an operation of planarizing and cleaning a wafer, an operation of forming a trench, an operation of forming a well, an operation of forming a gate electrode, and an operation of forming a source and a drain, etc. and individual devices (such as a transistor, a capacitor, a resistor, and/or the like) may be formed on a substrate according to the FEOL. A back-end-of-line (BEOL) may include an operation of silicidating a gate region, a source region, and a drain region, an operation of adding a dielectric, a planarization operation, an operation of forming a hole, an operation of adding a metal layer, an operation of forming a via, and an operation of forming a passivation layer, etc. and individual devices (such as a transistor, a capacitor, a resistor, and/or the like), may be connected to one another according to the BEOL. According to at least one embodiment, a middle-end-of-line (MEOL) may be performed between the FEOL and the BEOL, and contacts may be formed on the individual devices. A plurality of dies may be separated from the wafer W, and each of the plurality of dies may be packaged into a semiconductor package and used as a component of various applications.
Referring to
In operation S940, the integrated circuit may be manufactured through the semiconductor process. For example, the semiconductor process may include the at least one sub-process adjusted in operation S920, and accordingly, the integrated circuit may be manufactured to have the designed structure.
The computer system 130 may refer to a system including a general-purpose and/or special-purpose computing system. For example, the computer system 130 may include a personal computer (PC), a server computer, a laptop computer, an appliance product, and/or the like. Referring to
The at least one processor 131 may execute a program module including an instruction executable by a computer system. The program module may include, for example, routines, programs, objects, components, a logic, a data structure, etc., which perform a certain operation or implement a certain data format based on, inputs, commands, and/or the like. The memory 132 may include a computer system-readable medium of a volatile memory type such as random-access memory (RAM). The at least one processor 131 may access the memory 132 and may execute instructions loaded into the memory 132. The storage system 133 may non-volatilely store information, and according to at least one embodiment, may include at least one program product including a program module configured to perform training of machine learning models for the structure measurement described above with reference to the drawings. Non-limiting examples of a program may include an operating system (OS), at least one application, other program modules, and other program data. The memory 132 and/or the storage system 133 may be (or include), for example, a non-transitory computer readable media. The term “non-transitory,” as used herein, is a description of the medium itself (e.g., as tangible, and not a signal) as opposed to a limitation on data storage persistency (e.g., RAM vs. ROM). For example, the computer-readable recording medium may be any tangible medium that can store or include the program in or connected to an instruction execution system, equipment, or device.
The network adapter 134 may provide access to a network comprising other computer systems. For example, the network adaptor 134 may provide access to a local area network (LAN), a wide area network (WAN), a common network (for example, the Internet), and/or the like. The I/O interface 135 may provide a communication channel for communication with a peripheral device, such as a keyboard, a pointing device, an audio system, and/or the like. The display 136 may output various pieces of information for a user to check.
According to at least one embodiment, training of machine learning models for the structure measurement described above with reference to the drawings may be implemented as a computer program product. The computer program product may include a non-transitory computer-readable medium (or a storage medium) including computer-readable program instructions for allowing the at least one processor 131 to perform image processing and/or training of models. The computer-readable instruction may include, for example, an assembler instruction, an instruction set architecture (ISA) instruction, a machine instruction, a machine dependent instruction, micro-code, a firmware instruction, state setting data, source code or object code written in at least one programming language, and/or the like.
The computer-readable medium may be a type of medium for non-temporarily keeping and storing instructions executed by the at least one processor 131 or an arbitrary instruction-executable device. For example, the computer-readable medium may be, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, a combination thereof, and/or the like. For example, the computer-readable medium may be a portable computer disk, a hard disk, RAM, read-only memory (ROM), electrically erasable read only memory (EEPROM), flash memory, static RAM (SRAM), a compact disk (CD), a digital video disk (DVD), a memory stick, a floppy disk, a mechanically encoded device (such as a punch card), or a combination thereof.
Referring to
The at least one processor 141 may execute instructions. For example, the at least one processor 141 may execute instructions stored in the memory 143 to execute an OS or applications executed on the OS. According to at least one embodiment, the at least one processor 141 may execute instructions to instruct the AI accelerator 145 and/or the hardware accelerator 147 to perform an operation, and to obtain a performance result of the operation from the AI accelerator 145 and/or the hardware accelerator 147. According to at least one embodiment, the at least one processor 141 may be an application specific instruction set processor (ASIP) customized for a certain purpose and may support a dedicated instruction set.
The memory 143 may have a structure which is configured to store data. For example, the memory 143 may include a volatile memory device, such as dynamic RAM (DRAM) or SRAM, and moreover, may include a non-volatile memory device, such as flash memory, resistive RAM (RRAM), and/or the like. The at least one processor 141, the AI accelerator 145, and the hardware accelerator 147 may store data in the memory 143 through the bus 149 or may read the data from the memory 143.
The AI accelerator 145 may refer to hardware designed for AI applications. According to at least one embodiment, the AI accelerator 145 may include a neural processing unit (NPU) for implementing a neuromorphic structure and may generate output data by processing input data provided from the at least one processor 141 and/or the hardware accelerator 147 and may provide the output data to the at least one processor 141 and/or the hardware accelerator 147. According to at least one embodiment, the AI accelerator 145 may be programmable and may be programmed by the at least one processor 141 and/or the hardware accelerator 147.
The hardware accelerator 147 may be referred to as hardware designed to perform a certain operation at a high speed. For example, the hardware accelerator 147 may be designed to perform data conversion, such as demodulation, modulation, encoding, decoding, etc., at a high speed. The hardware accelerator 147 may be programmable and may be programmed by the at least one processor 141 and/or the hardware accelerator 147.
According to at least one embodiment, the AI accelerator 145 may execute the machine learning models described above with reference to the drawings. For example, the AI accelerator 145 may execute each of the layers described above. The AI accelerator 145 may process an input parameter, a feature map, and/or the like to generate an output including useful information. According to at least one embodiment, at least some of models executed by the AI accelerator 145 may be executed by the at least one processor 141 and/or the hardware accelerator 147.
While the inventive concepts have been particularly shown and described with reference to some embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
Number | Date | Country | Kind |
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10-2022-0089031 | Jul 2022 | KR | national |