Method And System For Mixing A Plurality Of Audio Sources In An FM Transmitter

Abstract

A plurality of digital audio signals from a plurality of sources utilizing different clocks may be processed and transmitted via an FM transmitter. The plurality of signals may have different sample rates which are converted to one same sample rate by a plurality of rate adapters. The plurality of rate adapters may be clocked at one same sample rate. The energy levels of the signals may be adjusted relative to one another and as a group. Energy level adjustments may improve FM modulation signal characteristics and audible energy levels for an end listener. The plurality of digital audio signals may be combined into one composite signal and FM modulated in the digital domain. The FM modulated signal may be converted to analog signal prior to being filtered, amplified and coupled to an antenna for transmission.

Description

FIELD OF THE INVENTION

Certain embodiments of the invention relate to FM communication. More specifically, certain embodiments of the invention relate to a method and system for mixing a plurality of audio sources in an FM transmitter.

BACKGROUND OF THE INVENTION

Electronic communication has become prolific over the last decade. While electronic communication was initially limited to the desktop, recent trends have been to make communications, media content and the Internet available anytime, anywhere and, increasingly, on any device. Already now, it is quite common to find mobile devices such as cellular phones or Personal Digital Assistants (PDAs) that incorporate a large range of communication technologies and associated software. For example, fully-featured web-browsers, email clients, MP3 players, instant messenger software, and Voice-over-IP may all be found on some recent devices.

The popularity of portable electronic devices and wireless devices that support audio applications is growing. For example, some users may utilize Bluetooth-enabled devices, such as headphones and/or speakers, to allow them to communicate audio data with their wireless handset while freeing to perform other activities. Other users may have portable electronic devices that may enable them to play stored audio content and/or receive audio content via broadcast communication, for example.

There is a drive towards making content stored on portable devices available on a variety of displays and user interfaces. For example, many portable media devices may be enabled to provide an audio/video output signal to a computer monitor or a television to allow display of, for example, digital photographs. For audio content, one possible output format may be a low-power FM transmission signal.

Portable electronics devices may comprise multiple audio communication technologies together in a single device. These portable electronic devices may require separate processing hardware and/or separate processing software, which may result in increased cost and power consumption.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method for mixing a plurality of audio sources in an FM transmitter, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

Various advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A is a block diagram of an exemplary FM receiver that communicates with handheld devices that utilize a single chip with FM radios and one or more integrated radios such as Bluetooth, GPS, WLAN, WWAN or a wire line connection, in accordance with an embodiment of the invention.

FIG. 1B is a block diagram of an exemplary single chip with multiple integrated radios that supports radio data processing, in accordance with an embodiment of the invention.

FIG. 2 is a block diagram of an exemplary single chip that supports FM operations and one or more of a plurality of optional integrated transceivers. For example, in addition to FM, the chip may support Bluetooth, GPS, WLAN, WWAN or other transceivers, in accordance with an embodiment of the invention.

FIG. 3 is a block diagram of an exemplary FM core with FM transmitter and PTU comprising a plurality of signals, in accordance with an embodiment of the invention.

FIG. 4A is a block diagram of an exemplary portion of an FM core enabling rate adaptation an combining of a plurality of audio sources prior to FM modulation, in accordance with an embodiment of the invention.

FIG. 4B is a flow chart illustrating exemplary steps for mixing digital audio signals from a plurality of audio sources in an FM transmitter, in accordance with an embodiment of the invention.

FIG. 4C is a block diagram of an exemplary portion of an FM core enabling rate adaptation and combining of a plurality of audio sources prior to FM modulation, in accordance with an embodiment of the invention.

FIG. 4D is a flow chart illustrating exemplary steps for mixing digital audio signals from a plurality of audio sources in an FM transmitter, in accordance with an embodiment of the invention

DETAILED DESCRIPTION OF THE INVENTION

Certain aspects of the invention may be found in a method and system for mixing a plurality of audio sources in an FM radio transmitter. A wireless communication device may comprise a single chip with an integrated baseband processor, FM radio transmitter and one or more optional integrated transmitters and/or receivers. The wireless communication device may be enabled to handle a plurality of audio sources. For example the wireless communication device may process and transmit inter IC sound (I²S) signals, pulse code modulation (PCM) signals, generated tones and/or buffered audio streams. The plurality of audio sources may be clocked independently. In this regard, the plurality of audio streams may undergo rate adaptation based on a determined master clock. In addition, energy level in one or more of the plurality of audio streams may be scaled prior to frequency modulation to prevent over modulation. Moreover, the energy level of one or more of the plurality of audio streams may be proportionally adjusted such that the audible output of the transmitted audio streams is appropriate for a listener.

FIG. 1A is a block diagram of an exemplary FM receiver that communicates with one or more wireless devices that utilize a single chip with FM radios and one or more optional integrated radios such as Bluetooth, GPS, WLAN, WWAN or a wire line connection, in accordance with an embodiment of the invention. Referring to FIG. 1A, there is shown an FM receiver 110, a cellular phone 104a, a smart phone 104b, a computer 104c, and an exemplary FM device equipped with one or more integrated radios 104d. In this regard, the FM receiver 110 may comprise and/or may be communicatively coupled to a listening device 108. A device equipped with an FM radio and one or more optional integrated radios, such as the single chip 106, may be able to broadcast its respective signal to a “deadband” of an FM receiver for use by the associated audio system. For example, a cellphone or a smart phone, such as the cellular phone 104a and the smart phone 104b, may transmit a telephone call for listening over the audio system of an automobile, via usage of a deadband area of the car's FM stereo system. One advantage may be the universal ability to use this feature with all automobiles equipped simply with an FM radio with few, if any, other external FM transmission devices or connections being required.

In another example, a computer, such as the computer 104c, may comprise an MP3 player or another digital music format player and may broadcast a signal to the deadband of an FM receiver in a home stereo system. The music on the computer may then be listened to on a standard FM receiver with few, if any, other external FM transmission devices or connections. While a cellular phone, a smart phone, and computing devices have been shown, a single chip that combines a Bluetooth and FM transmitter and/or receiver may be utilized in a plurality of other devices and/or systems that receive and use an FM signal.

FIG. 1B is a block diagram of an exemplary single chip with multiple integrated radios that supports radio data processing, in accordance with an embodiment of the invention. Referring to FIG. 1B, there is shown a single chip 130 that may comprise a radio portion 132 and a processing portion 134. The radio portion 132 may comprise a plurality of integrated radios. For example, the radio portion 132 may comprise an FM receive and transmit (Rx/Tx) radio 140c that supports FM communications and a plurality of optional integrated radios. For example, a cellular radio 140a that supports cellular communications, a Bluetooth radio 140b that supports Bluetooth communications, a global positioning system (GPS) receiver 140d that supports GPS communications, and/or a wireless local area network (WLAN) 140e that supports communications based on the IEEE 802.11 standards.

The processing portion 134 may comprise at least one processor 136, a memory 138, and a peripheral transport unit (PTU) 140. The processor 136 may comprise suitable logic, circuitry, and/or code that enable processing of data received from the radio portion 132. In this regard, each of the integrated radios may communicate with the processing portion 134. In some instances, the integrated radios may communicate with the processing portion 134 via a common bus, for example. The memory 138 may comprise suitable logic, circuitry, and/or code that enable storage of data that may be utilized by the processor 136. In this regard, the memory 138 may store at least a portion of the data received by at least one of the integrated radios in the radio portion 132. Moreover, the memory 138 may store at least a portion of the data that may be transmitted by at least one of the integrated radios in the radio portion 132. The PTU 140 may comprise suitable logic, circuitry, and/or code that may enable interfacing data in the single chip 130 with other devices that may be communicatively coupled to the single chip 130. In this regard, the PTU 140 may support analog and/or digital interfaces.

FIG. 2 is a block diagram of an exemplary single chip comprising an FM radio and one or more of a plurality of optional integrated radios that may transmit one or more of a plurality of audio sources. For example, in addition to FM, the single chip may support Bluetooth, GPS, WLAN, WWAN or other radios, in accordance with an embodiment of the invention. Referring to FIG. 2, there is shown the single chip 200 that may comprise a processor system 202, a peripheral transport unit (PTU) 204, one or more optional radio cores 206, a frequency modulation (FM) core 208 with the FM transmitter 226 and the FM receiver 224 integrated into the FM core 208, a common bus 201, a buffer 232 and a rate adaptor 230.

In this regard, the FM core 208 may support FM reception and/or transmission of FM data. The FM transmitter 226 may utilize signals based on the reference signal generated by the LO 227. The FM core 208 may enable transmission of data received via the PTU 204, the buffer 232 and/or a Bluetooth core 206, for example.

The processor system 202 may comprise a central processing unit (CPU) 210, a memory 212, a direct memory access (DMA) controller 214, a power management unit (PMU) 216, and an audio processing unit (APU) 218. The APU 218 may comprise a sub-band coding (SBC) codec 220. At least a portion of the components of the processor system 202 may be communicatively coupled via the common bus 201.

The CPU 210 may comprise suitable logic, circuitry, and/or code that may enable control and/or management operations in the single chip 200. In this regard, the CPU 210 may communicate control and/or management operations to the optional radio core 206, the FM core 208, the buffer 232, the rate adaptor 230 and/or the PTU 204 via a set of register locations specified in a memory map. Moreover, the CPU 210 may be utilized to process data received by the single chip 200 and/or to process data to be transmitted by the single chip 200. The CPU 210 may enable processing of data received via the one or more optional radio cores 206, via the FM core 208, and/or via the PTU 204. For example, the CPU 210 may enable processing of A2DP data and may then transfer the processed A2DP data to other components of the single chip 200 via the common bus 201. In this regard, the CPU may utilize the SBC codec 220 in the APU 218 to encode and/or decode A2DP data, for example. The CPU 210 may enable processing of data to be transmitted via the FM core 208, one or more of the optional radio cores 206 and/or via the PTU 204. The CPU 210 may be, for example, an ARM processor or another embedded processor core that may be utilized in the implementation of system-on-chip (SOC) architectures.

The CPU 210 may time multiplex FM data processing operations and data processing operations from another integrated radio such as Bluetooth for example. In this regard, the CPU 210 may perform each operation by utilizing a native clock, that is, Bluetooth data processing based on a Bluetooth clock and FM data processing based on an FM clock. The Bluetooth clock and the FM clock may be distinct and may not interact. The CPU 210 may gate the FM clock and the Bluetooth clock and may select the appropriate clock in accordance with the time multiplexing scheduling or arrangement. When the CPU 210 switches between Bluetooth operations and FM operations, at least certain states associated with the Bluetooth operations or with the FM operations may be retained until the CPU 210 switches back.

For example, in the case where the Bluetooth function is not active and is not expected to be active for some time, the CPU 210 may run on a clock derived from the FM core 208. This may eliminate the need to bring in a separate high-speed clock when one is already available in the FM core 208. In the case where the Bluetooth core 206 may be active, for example when the Bluetooth is in a power-saving mode that requires it to be active periodically, the processor may chose to use a clock derived separately from the FM core 208. The clock may be derived directly from a crystal or oscillator input to the Bluetooth core 206, or from a phase locked loop (PLL) in the Bluetooth core 206. While this clocking scheme may provide certain flexibility in the processing operations performed by the CPU 210 in the single chip 200, other clocking schemes may also be implemented.

The CPU 210 may also enable configuration of data routes to and/or from the FM core 208. For example, the CPU 210 may configure the FM core 208 so that data may be routed via an inter-IC sound (I²S) interface or a PCM interface in the PTU 204 to the analog ports communicatively coupled to the PTU 204.

The CPU 210 may also enable rate adaptation prior to FM transmission for streams of digital signals from a plurality of audio sources. One or more of the plurality of audio sources may utilize a distinct source clock from an independent oscillator to generate distinct source sampling rates. Alternatively, one or more of the plurality of audio sources may share a source clock domain. In this regard, the CPU 210 may enable rate adaptation for one or more of the streams of digital signals based on a specified master clock or sink clock. For example, the FM core may convert the plurality of sampling rates to one same sink rate for all of the streams of digital signals. In addition, the CPU 210 may enable summing of the rate converted streams of digital signals as well as scaling of the audio energy prior to FM modulation.

The CPU 210 may enable tuning, such as flexible tuning, and/or searching operations in Bluetooth for example, and/or FM communication by controlling at least a portion of the Bluetooth core 206 and/or the FM core 208. For example, the CPU 210 may generate at least one signal that tunes the FM core 208 to a certain frequency to determine whether there is a station at that frequency. When a station is found, the CPU 210 may configure a path for the audio signal to be processed in the single chip 200. When a station is not found, the CPU 210 may generate at least one additional signal that tunes the FM core 208 to a different frequency to determine whether a station may be found at the new frequency.

Searching algorithms may enable the FM core 208 to scan up or down in frequency from a presently tuned channel and stop on the next channel with received signal strength indicator (RSSI) above a threshold. The search algorithm may be able to distinguish image channels. The choice of the IF frequency during search is such that an image channel may have a nominal frequency error of 50 kHz, which may be used to distinguish the image channel from the “on” channel. The search algorithm may also be able to determine if a high side or a low side injection provides better receive performance, thereby allowing for a signal quality metric to be developed for this purpose. One possibility to be investigated is monitoring the high frequency RSSI relative to the total RSSI. The IF may be chosen so that with the timing accuracy that a receiver may be enabled to provide, the image channels may comprise a frequency error that is sufficiently large to differentiate the image channels from the on channel.

The CPU 210 may enable a host controller interface (HCI) in Bluetooth. In this regard, the HCI provides a command interface to the baseband controller and link manager, and access to hardware status and control registers. The HCI may provide a method of accessing the Bluetooth baseband capabilities that may be supported by the CPU 210.

The memory 212 may comprise suitable logic, circuitry, and/or code that may enable data storage. In this regard, the memory 212 may be utilized to store data that may be utilized by the processor system 202 to control and/or manage the operations of the single chip 200. The memory 212 may also be utilized to store data received by the single chip 200 via the PTU 204 and/or via the FM core 208. Similarly, the memory 212 may be utilized to store data to be transmitted by the single chip 200 via the PTU 204 and/or via the FM core 208. The DMA controller 214 may comprise suitable logic, circuitry, and/or code that may enable transfer of data directly to and from the memory 212 via the common bus 201 without involving the operations of the CPU 210.

The PTU 204 may comprise suitable logic, circuitry, and/or code that may enable communication to and from the single chip 200 via a plurality of communication interfaces. In some instances, the PTU 204 may be implemented outside the single chip 200, for example. The PTU 204 may support analog and/or digital communication with at least one port. Digital audio data may be transferred by a digital interface, for example, inter-IC-sound (I²S), inter-integrated circuit (I²C), pulse code modulation (PCM), universal serial bus (USB), secure digital input/output (SDIO) and/or universal asynchronous receiver transmitter (UART). For example, the PTU 204 may support at least one USB interface that may be utilized for Bluetooth data communication, at least one SDIO interface that may also be utilized for Bluetooth data communication, at least one UART interface that may also be utilized for Bluetooth data communication, and at least one inter-integrated circuit (I²C) bus interface that may be utilized for FM control and/or FM and RDS/RBDS data communication. The PTU 204 may also support at least one PCM interface that may be utilized for Bluetooth data communication and/or FM data communication, for example.

The PTU 204 may support at least one inter-IC sound (I²S) interface, for example. The I²S interface may be utilized to send high fidelity FM digital signals to the CPU 210 for processing, for example. In this regard, the I²S interface in the PTU 204 may receive data from the FM core 208 via a bus 203, for example. Moreover, the I²S interface may be utilized to transfer high fidelity audio in Bluetooth. For example, in the A2DP specification there is support for wideband speech that utilizes 16 kHz of audio. In this regard, the I²S interface may be utilized for Bluetooth high fidelity data communication and/or FM high fidelity data communication. The I²S interface may be a bidirectional interface and may be utilized to support bidirectional communication between the PTU 204 and the FM core 208 via the bus 203. The I²S interface may be utilized to send and receive FM data from external devices such as coder/decoders (CODECs) and/or other devices that may further process the I²S data for transmission, such as local transmission to speakers and/or headsets and/or remote transmission over a cellular network, for example.

The optional radio core 206 may for example be a Bluetooth core and may comprise suitable logic, circuitry, and/or code that may enable reception and/or transmission of Bluetooth data. The Bluetooth core 206 may comprise a Bluetooth transceiver 229 that may perform reception and/or transmission of Bluetooth data. In this regard, the Bluetooth core 206 may support amplification, filtering, modulation, and/or demodulation operations, for example. The Bluetooth core 206 may enable data to be transferred from and/or to the processor system 202, the PTU 204, and/or the FM core 208 via the common bus 201, for example.

The FM core 208 may comprise suitable logic, circuitry, and/or code that may enable reception and/or transmission of FM data. The FM core 208 may comprise an FM receiver 222, an FM transmitter 226 and a local oscillator (LO) 227. The LO 227 may be utilized to generate a reference signal that may be utilized by the FM core 208 for performing analog and/or digital operations. The FM receiver 222 may handle demodulation, amplification and/or filtering operations, for example. The FM transmitter 226 may handle modulation, amplification and/or filtering operations. Moreover, the FM receiver 222 may receive FM audio data and demodulate the audio data in a digital domain. The demodulated digital audio data may be converted to analog via the D/A converter 224 and analog audio may be output from the chip to a listening device. Also, analog audio may be input from an external device to the FM transmitter 226. The FM transmitter 226 may comprise an analog to digital converter (A/D) 228 that may be utilized to convert analog audio information to a digital signal for modulation in the digital domain prior to FM transmission. The FM core 208 may enable data to be transferred to and/or from the processor system 202, the PTU 204, and/or one or more optional radio cores 206 via the common bus 201 and/or the bus 203, for example. Alternatively, FM core 208 may enable data to be transferred from the PTU 204 and the buffer 232 via the rate adapter 230.

The FM core 208 may enable radio transmission and/or reception at various frequencies, such as, 400 MHz, 900 MHz, 2.4 GHz and/or 5.8 GHz, for example. The FM core 208 may also support operations at the standard FM band comprising a range of about 76 MHz to 108 MHz, for example.

The FM core 208 may also enable reception of RDS data and/or RBDS data for in-vehicle radio receivers. In this regard, the FM core 208 may enable filtering, amplification, and/or demodulation of the received RDS/RBDS data. The RDS/RBDS data may comprise, for example, information for retuning to a new channel such as a channel spacing offsets and a list of alternate channels available for transmission. The RDS/RBDS may comprise a traffic message channel (TMC) that provides traffic information that may be communicated and/or displayed to an in-vehicle user.

Digital circuitry within the FM core 208 may be operated based on a clock signal generated by dividing down a signal generated by the LO 227. The LO 227 may be programmable in accordance with the various channels that may be received by the FM core 208 and the divide ratio may be varied in order to maintain the digital clock signal close to a nominal value.

The RDS/RBDS data may be buffered in the memory 212 in the processor system 202. The RDS/RBDS data may be transferred from the memory 212 via the I²C interface when the CPU 210 is in a sleep or stand-by mode. For example, the FM core 208 may post RDS data into a buffer in the memory 212 until a certain level is reached and an interrupt is generated to wake up the CPU 210 to process the RDS/RBDS data. When the CPU 210 is not in a sleep mode, the RDS data may be transferred to the memory 212 via the common bus 201, for example.

Moreover, the RDS/RBDS data received via the FM core 208 may be transferred to any of the ports communicatively coupled to the PTU 204 via the HCI scheme supported by the single chip 200, for example. The RDS/RBDS data may also be transferred to the optional radio core 206 for communication to Bluetooth-enabled devices, for example.

In one exemplary embodiment of the invention, the single chip 200 may receive Bluetooth data, such as A2DP, SCO, eSCO, and/or MP3, for example, the Bluetooth core 206 may transfer the received data to the processor system 202 via the common bus 201. At the processor system 202, the SBC codec 220 may decode the Bluetooth data and may transfer the decoded data to the FM core 208 via the common bus 201. The FM core 208 may transfer the data to the FM transmitter 226 for communication to an FM receiver in another device.

In another exemplary embodiment of the invention, the single chip 200 may operate in a plurality of modes. For example, the single chip 200 may operate in one of an FM-only mode, a Bluetooth-only mode, and an FM-Bluetooth mode. For the FM-only mode, the single chip 200 may operate with a lower power active state than in the Bluetooth-only mode or the FM-Bluetooth mode because FM operation in certain devices may have a limited source of power. In this regard, during the FM-only mode, at least a portion of the operation of the Bluetooth core 206 may be disabled to reduce the amount of power used by the single chip 200. Moreover, at least a portion of the processor system 202, such as the CPU 210, for example, may operate based on a divided down clock from a phase locked-loop (PLL) in the FM core 208. In this regard, the PLL in the FM core 208 may utilize the LO 227, for example.

Moreover, because the code necessary to perform certain FM operations, such as tuning and/or searching, for example, may only require the execution of a few instructions in between time intervals of, for example, 10 ms, the CPU 210 may be placed on a stand-by or sleep mode to reduce power consumption until the next set of instructions is to be executed. In this regard, each set of instructions in the FM operations code may be referred to as a fragment or atomic sequence. The fragments may be selected or partitioned in a very structured manner to optimize the power consumption of the single chip 200 during FM-only mode operation. In some instances, fragmentation may also be implemented in the FM-Bluetooth mode to enable the CPU 210 to provide more processing power to Bluetooth operations when the FM core 208 is carrying out tuning and/or searching operations, for example.

FIG. 3 is a block diagram of an exemplary FM core with FM transmitter and PTU for processing RDS and digital audio data, in accordance with an embodiment of the invention. Referring to FIG. 3, there is shown a detailed portion of a single chip 200 described in FIG. 2, comprising an FM core 208, a memory 212, a CPU 210, a common bus 201. Also shown are portions of a PTU 204 which may comprise an interface multiplexer 310, a universal peripheral interface (UPI) 304, a bus master interface 302, a digital audio interface controller 306, an inter-IC sound (I²S) interface block 308, and an inter-integrated circuit (I²C) interface block 312.

The FM core 208 may comprise an FM/MPX demodulator and decoder 317, an FM/MPX modulator and encoder 317a, rate adaptors 314 and 314a, buffers 316 and 316a, an RDS/RBDS demodulator and decoder 318, a RDS/RBDS modulator and encoder 318a, a gain controller 320 and a control registers block 322. Narrowly spaced hashed arrows as illustrated by the flow arrow 332 show the flow of digital audio data. Broadly spaced hashed arrows as illustrated by the flow arrow 334 show the flow of RDS/RBDS data. Clear or blank arrows, as illustrated by the dual flow arrow 336, show the flow of control data.

The FM/MPX demodulator and decoder 317 may comprise suitable logic, circuitry, and/or code that may enable processing of FM and/or FM MPX stereo audio, for example. The FM/MPX demodulator and decoder 317 may demodulate and/or decode audio signals that may be transferred to the rate adaptor 314. The FM/MPX demodulator and decoder 317 may demodulate and/or decode signals that may be transferred to the RDS/RBDS demodulator and decoder 318.

The FM/MPX encoder 317a may comprise suitable logic, circuitry, and/or code that may enable processing of FM and/or FM MPX stereo audio, for example. The FM/MPX encoder 317a may encode audio signals that may be transferred from the rate adaptor 314a via the gain controller 320. The FM/MPX encoder 317a may encode signals that may be transferred to the RDS/RBDS modulator and encoder 318a.

The rate adaptor 314 may comprise suitable logic, circuitry, and/or code that may enable controlling the rate of the FM data received from the FM/MPX demodulator and decoder 317. The rate adaptor 314 may adapt the output sampling rate of the audio paths to the sampling clock of the host device or the rate of a remote device when a digital audio interface is used to transport the FM data. An initial rough estimate of the adaptation fractional change may be made and the estimate may then be refined by monitoring the ratio of reading and writing rates and/or by monitoring the level of the audio samples in the output buffer 316. The rate may be adjusted in a feedback manner such that the level of the output buffer is maintained. The rate adaptor 314 may receive a strobe or pull signal from the digital audio interface controller 306, for example. Audio FM data from the rate adaptor 314 may be transferred to the buffer 316. The U.S. application Ser. No. 11/176,417 filed on Jul. 7, 2005, discloses a method and system comprising a rate adaptor, and is hereby incorporated herein by reference in its entirety.

The buffer 316 may comprise suitable logic, circuitry, and/or code that may enable storage of digital audio data. The buffer 316 may receive a strobe or pull signal from the digital audio interface controller 306, for example. The buffer 316 may transfer digital audio data to the digital audio interface controller 306.

The RDS/RBDS demodulator and decoder 318 may comprise suitable logic, circuitry, and/or code that may enable processing of RDS/RBDS data from the FM/MPX demodulator and decoder 317. The RDS/RBDS demodulator and decoder 318 may provide further demodulation and/or decoding to data received from the FM/MPX demodulator and decoder 317. The output of the RDS/RBDS demodulator and decoder 318 may be transferred to the interface multiplexer 310.

The RDS/RBDS modulator and encoder 318a may comprise suitable logic, circuitry, and/or code that may enable processing of RDS/RBDS data from the FM/MPX modulator and encoder 317a. The RDS/RBDS modulator and encoder 318a may provide further modulation and/or encoding to data received from the FM/MPX modulator and encoder 317. The output of the RDS/RBDS modulator and encoder 318 may be transferred to the interface multiplexer 310.

The control registers block 322 may comprise suitable logic, circuitry, and/or code that may enable the storage of register information that may be utilized to control and/or configure the operation of at least portions of the FM core 208.

The rate adaptor 314a may comprise suitable logic, circuitry, and/or code that may enable converting the source sampling rates of digital signal streams from a plurality of audio sources prior to summing the streams for input to the FM Tx/MPX encoder 317a. The rate adaptor 314a may adapt an output or sink rate to the sampling clock of the host device or the rate of a remote device when a digital audio interface is used to transport the plurality of audio streams. An initial estimate of the rate adaptation fractional change per stream may be made and the estimate may then be refined by monitoring the level of the input buffer. The rate adaptor 314a may receive a sink clock signal from the digital audio interface controller 306, for example. Decimation and interpolation as well as fine grain rate matching may be utilized to convert the source sampling rates to the sink sampling rate. Once the plurality of audio streams are rate adapted, they may be summed.

The gain controller 320 may receive the summed plurality of audio streams and adjust the gain prior to input to the FM Tx/MPX encoder 317a. The audio energy level of the summed plurality of audio streams may be adjusted to prevent over modulation.

In operation, the FM core 208 may enable radio transmission and/or reception at various frequencies, such as, 400 MHz, 900 MHz, 2.4 GHz and/or 5.8 GHz, for example. The FM core 208 may also support operations at the standard FM band comprising a range of about 76 MHz to 108 MHz, for example. The FM core 208 may also enable reception of RDS data and/or RBDS data for in-vehicle radio receivers. In this regard, the FM core 208 may enable filtering, amplification, and/or demodulation of the received RDS/RBDS data. The RDS/RBDS data may comprise, for example, a traffic message channel (TMC) that provides traffic information that may be communicated and/or displayed to an in-vehicle user.

The memory 212 may comprise suitable logic, circuitry, and/or code that may enable data storage. In this regard, the memory 212 may be utilized to store data that may be utilized by the CPU 210 to control and/or manage the operations of the single chip 200. The memory 212 may also be utilized to store data received by the single chip 200 via the FM core 208. Similarly, the memory 212 may be utilized to store data to be transmitted by the single chip 200 via the FM core 208.

The CPU 210 may comprise suitable logic, circuitry, and/or code that may enable control and/or management operations in the single chip 200. In this regard, the CPU 210 may communicate control and/or management operations to the FM core 208 via a set of register locations specified in a memory map. Moreover, the CPU 210 may be utilized to process data received by the single chip 200 and/or to process data to be transmitted by the single chip 200. The CPU 210 may enable processing of data received the FM core 208. For example, the CPU 210 may enable processing of A2DP data and may then transfer the processed A2DP data to other components of the single chip 200 via the common bus 201. In this regard, the CPU may utilize the SBC codec 220 in the APU 218 to encode and/or decode A2DP data, for example. The CPU 210 may enable processing of data to be transmitted via the FM core 208. The CPU 210 may be, for example, an ARM processor or another embedded processor core that may be utilized in the implementation of system-on-chip (SOC) architectures.

The CPU 210 may also enable configuration of data routes to and/or from the FM core 208. For example, the CPU 210 may configure the FM core 208 so that data may be routed via an I²S interface or a PCM interface.

The CPU 210 may enable tuning, such as flexible tuning, and/or searching operations in FM communication by controlling at least a portion of the FM core 208. For example, the CPU 210 may generate at least one signal that tunes the FM core 208 to a certain frequency to determine whether there is a station at that frequency. When a station is not found, and interference is below a specified threshold, the CPU 210 may configure a path for the audio signal to be transmitted in the single chip 200. When a station is found with RSSI above a specified threshold, the CPU 210 may generate at least one additional signal that tunes the FM core 208 to a different frequency to determine whether a channel may be clear for transmission at the new frequency. The CPU 210 may create a list of available channels for FM transmission and rank the list according to lowest receive signal strength indicator (RSSI) and other factors for improved channel searching times.

The bus master interface 302 may comprise suitable logic, circuitry, and/or code that may enable communication of control data, digital audio data, and/or RDS/RBDS data between the portions of the PTU 204 shown in FIG. 2 and the common bus 201. The bus master interface 302 may transfer digital audio data and/or RDS/RBDS data to the common bus 201. The RDS/RBDS data may be transferred to the memory 212, for example. In some instances, the RDS/RBDS data may be transferred to the memory 212 when the CPU 210 is in a stand-by or sleep mode. The bus master interface 302 may push RDS/RBDS data into a buffer in the memory 212 or may pull RDS/RBDS data from a buffer in the memory 212, for example. The digital audio data may be transferred to the CPU 210 for processing, for example. The CPU 210 may generate and/or receive control data that may be communicated with the PTU 204 and/or the FM core 208 via the common bus 201.

The UPI 304 may comprise suitable logic, circuitry, and/or code that may enable the transfer of RDS/RBDS data to the bus master interface 302 from the interface multiplexer 310. The UPI 304 may also enable the communication of control data between the bus master interface 302 and the interface multiplexer 310.

The digital audio interface controller 306 may comprise suitable logic, circuitry, and/or code that may enable the transfer of digital audio data to the bus master interface 302 and/or the I²S interface block 308. The I²S interface 308 may comprise suitable logic, circuitry, and/or code that may enable transfer of the digital audio data to at least one device communicatively coupled to the single chip. The I²S interface 308 may communicate control data with the bus master interface 302.

The I²C interface 308 may comprise suitable logic, circuitry, and/or code that may enable transfer of the RDS/RBDS data to at least one device communicatively coupled to the single chip. The I²C interface 308 may also communicate control data between external devices to the single chip and the interface multiplexer 310. In this regard, the interface multiplexer 310 may communicate control data between the I²C interface 308, the UPI 304, and/or the control registers block 322 in the FM core 208.

The interface multiplexer 310 may comprise suitable logic, circuitry, and/or code that may enable the transfer of RDS/RBDS data to the UPI 304 and/or the I²C interface block 312. In this regard, the UPI 304 may generate a signal that indicates to the interface multiplexer 310 the interface to select.

The I²C interface 312 may comprise suitable logic, circuitry, and/or code that may enable transfer of the RDS/RBDS data to at least one device communicatively coupled to the single chip. The I²C interface 312 may also communicate control data between external devices to the single chip and the interface multiplexer 310. In this regard, the interface multiplexer 310 may communicate control data between the I²C interface 312, the UPI 304, and/or the control registers block 322 in the FM core 208.

FIG. 4A is a block diagram of an exemplary portion of an FM core enabling rate adaptation and combining of a plurality of audio sources prior to FM modulation, in accordance with an embodiment of the invention. Referring to FIG. 4A, there is shown a plurality of exemplary audio sources: a buffer 410a, a PCM block 410g, an inter-IC sound I²S interface 410c and a tone generator 410d; a plurality of digital audio signals output from the sources at different sampling rates 430a, 430b, 430c and 430d; a plurality of rate adapters 412a, 412b, 412c and 412d; a plurality of rate adapted digital audio signals with a common rate 432a, 432b, 432c and 432d; a plurality of weighting blocks 414a, 414b, 414c and 414d; a summation block 416; a gain controller 418; an FM modulation block 420 and an RF conditioning block 422.

The buffer 410a may comprise suitable logic and/or circuitry that may enable temporary storage of audio from a CPU prior to writing it to rate adapter 412a. The buffer helps to control timing requirements by storing data in a specified number of spaces and then writing out data from a specified number of spaces. The buffer 410 may be communicatively coupled with the rate adapter 412a and for example a CPU or memory.

The pulse coded modulation (PCM) block 410b may comprise suitable logic, circuitry and/or code that may enable transportation of coded FM analog data. The buffer 410 may be communicatively coupled with the rate adapter 412b.

The inter IC sound (I²S) block 410c comprise suitable logic, circuitry and/or code and may comprise a bidirectional interface for high fidelity FM digital signals. The I²S interface may be utilized to send and receive FM data from external devices such as coder/decoders (CODECs) and/or other devices that may further process the I²S data for transmission, such as local transmission to speakers and/or headsets and/or remote transmission over a cellular network, for example. The I²S block 410c may be communicatively coupled with rate adapter 412c.

The tone generator block 410d may comprise suitable logic, circuitry and/or code that may enable may enable writing of ring tones or DTMF event tones to the rate adapters. The tone generator block 410d may be communicatively coupled with the rate adaptor 412d.

One or more of the plurality of audio sources 410a, 410b, 410c and 410d may utilize a distinct source clock derived from an independent oscillator to generate a digital audio signal stream at an independent source sampling rate. Alternatively, two or more of the plurality of audio sources may share a source clock domain. The plurality of audio sources may be communicatively coupled with rate adapters 412a, 412b, 412c and 412d.

The rate adapters 412a, 412b, 412c and 412d may comprise suitable logic, circuitry and/or code that may enable that may enable receiving of the plurality of digital audio signal streams at different source sampling rates and may output a plurality of rate adapted digital audio signal streams at one same sink sampling rate. The sink sampling rate may be maintained at a relatively constant rate regardless of drifting in the source rates. The rate adapters 412a, 412b, 412c and 412d may be enabled to perform interpolation, decimation and/or fine grain rate adaptation. In addition, the rate adapters 412a, 412b, 412c and 412d may be driven by a sink clock which may be derived from a clock within the host or based on one or more of the source clocks.

A plurality of digital audio signal streams 432a, 432b, 432c and 432d output from the rate adaptation blocks 412a, 412b, 412c and 412d respectively, may each have the same sink sampling rate. The plurality of rate adapted digital audio signal streams may each be assigned a weight which may determine relative audio energy levels, in blocks 414a, 414b, 414c and 414d. In this regard, the audible output levels from an FM receiver may be determined by the weights assigned in the transmitter. For example, a user may be listening to music which may be muted to a determined degree so that an interrupting audible message may be heard. The weights assigned to digital audio streams in the FM transmitter may be varied such that audio effects are appropriate for a listener.

In the summation block 416, two or more of the rate adapted digital audio signal streams may be summed to form one composite digital audio signal. The summing block 416 may be communicatively coupled with the weighting blocks 414a, 414b, 414c and 414d as well as gain controller 418.

The gain controller 418 may comprise suitable logic, circuitry and/or code that may enable adjustment of the magnitude of the audio energy of the composite digital audio signal such that the energy level is appropriate for FM modulation and to prevent over modulation. The gain controller 418 may be communicatively coupled with the summing block 416 and the FM modulator block 420.

The FM modulation block 420 may comprise logic, circuitry and/or code which may enable FM modulation of the gain adjusted composite digital audio signal. FM modulation may be performed in the digital domain and may generate in-phase (I) and quadrature phase (Q) output. The FM modulation block 420 may comprise a digital to analog converter which may enable conversion of discrete digital logic levels of the FM modulated signal to an analog signal. The FM modulation block 420 may be communicatively coupled with the gain controller 418 and the RF conditioning block 422.

The RF conditioning block 422 may comprise amplifiers, filters and couplers that condition the FM analog signal for transmission via an antenna. One or more components in the RF conditioning block and/or the antenna may be integrated on the FM transmitter chip or may be located on external circuitry.

One or more of the plurality of exemplary audio sources may output digital audio signal streams 430a, 430b, 430c and 430d which may be input to the rate adapters 412a, 412b, 412c and 412d at different source sampling rates. A plurality of sink rate adapted digital audio signal streams may comprise 432a, 432b, 432c and 432d. Relative audio energy levels of the plurality of sink rate adapted digital signal streams may be determined by an assigned weighting per stream 414a, 414b, 414c and 414d. The plurality of weighted sink rate adapted digital audio signal streams may be summed in block 416 to form a composite digital audio signal stream. A gain controller 418 may scale the audio energy level of the composite stream in preparation for FM modulation in block 420. The RF conditioning block 422 may comprise radio frequency (RF) components such as filters, amplifiers and couplers for transmission of an FM modulated signal via an antenna. One or more of the components in the RF condition block 422 may be integrated or may be located on an external circuit. Although there are four different audio sources and respective signal paths in FIG. 4C, another embodiment of the invention may comprise more or fewer audio sources and signal paths.

In operation one or more of a plurality of audio sources 410a, 410b, 410c and/or 410d may output digital audio signal streams 430a, 430b, 430c and/or 430d respectively, at source sampling rates which may be different from each other. The one or more digital audio signal streams at different source sampling rates may be received by a plurality of rate adapters 412a, 412b, 412c and 412d which may be enabled by one same sink clock rate. In this regard, the different source sampling rates of the one or more digital audio signal streams may be converted to the same sink sampling rate and output from the rate adapters as one or more rate-adapted digital audio signal streams 432a, 432b, 432c and 432d. Energy levels of the one or more rate-adapted digital audio signal streams may be weighted in weighting blocks 414a, 414b, 414c and 414d. The one or more weighted digital audio signal streams may be summed in the summing block 416 and output from block 416 as a composite digital audio signal. The energy level of the composite digital audio signal may be adjusted by the gain controller 418 prior to FM modulation in block 420. FM modulation may be performed in the digital domain and the FM modulated digital signal may be converted to analog by a digital to analog converter in block 420. In-phase (I) and quadrature phase (Q) output may be generated by the FM modulation block. In addition, the FM analog signals may be filtered, amplified coupled with an antenna and transmitted in block 422.

FIG. 4B is a flow chart illustrating exemplary steps for mixing digital audio signals from a plurality of audio sources in an FM transmitter, in accordance with an embodiment of the invention. Referring to FIG. 4B, there is shown a step 460 wherein a plurality of digital audio signal streams 430a, 430b, 430c and 430d, may be received by rate adaptors 412a, 412b, 412c and 412d from two or more digital audio sources. The plurality digital audio sources may be driven by independent source oscillators or may be enabled under one clock domain. The plurality of digital audio signal streams may comprise different source sample rates. In step 462, each of the one or more rate adaptors may adapt the different source sample rates to one same sink sample rate for the plurality of digital audio signal streams. The rate adaptors may utilize decimation, interpolation and fine grained rate adaptation.

In step 464, a weight may be assigned to each of the plurality of digital audio streams to indicate a relative audio energy. This weighting may determine the proportion of audible volume for each audio stream relative to the other audible streams after the plurality of streams have been transmitted via a speaker to a listener. The weights may be adjusted over time to control desired audible effects. In step 466, the plurality of digital audio streams 432a, 432b, 432c and 432d output from the rate adaptors at one same sink sample rate may be summed in block 416 to form one composite digital audio signal. In step 468, the energy level of the composite digital audio signal may be scaled by gain controller 418 to prepare the signal for improved FM modulation. In step 470, the composite digital audio signal may be FM modulated in the digital domain and then converted to an analog signal by a digital to analog converter in the FM modulation block 420. In step 474, the analog signal may be filtered and amplified. In step 475, the analog signal may be coupled with an antenna and transmitted.

FIG. 4C is a block diagram of an exemplary portion of an FM core enabling rate adaptation and combining of a plurality of audio sources prior to FM modulation, in accordance with an embodiment of the invention. Referring to FIG. 4C, there is shown a plurality of exemplary audio sources: a buffer 410a, a PCM block 410g, an inter-IC sound I²S interface 410c and a tone generator 410d; a plurality of digital audio signals output from the sources at different sampling rates 430a, 430b, 430c and 430d; a plurality of rate adapters 412a, 412b, 412c and 412d; a plurality of rate adapted digital audio signals with a common rate 432a, 432b, 432c and 432d; a plurality of scaling blocks 440a, 440b, 440c and 440d; a summation block 416; an FM modulation block 420 and an RF conditioning block 422. Many of the blocks in FIG. 4D are the same blocks shown in FIG. 4A comprising the buffer 410a, the PCM block 410b, the I²S block 410c and the tone generator 410d; the plurality of digital audio signal streams comprising different source sampling rates: 430a, 430b, 430c and 430d; the plurality of rate adaptation blocks 412a, 412b, 412c and 412d; the plurality of digital audio signal streams comprising same sink sampling rates 432a, 432b, 432c and 432d; the FM modulation block 420 and the RF conditioning block 422.

Blocks that are new in FIG. 4C may comprise the weighting blocks 440a, 440b, 440c and 440d. The gain controller block 418 from FIG. 4A has been eliminated in FIG. 4C.

The blocks 440a, 440b, 440c and 440d scale the energy level of one or more of the plurality of digital audio signal streams 432a, 432b, 432c and 432d. These scaling blocks perform the functionality of the weighting blocks 414a, 414b, 414c and 414d as well as the gain controller 418 from FIG. 4A. The scaling blocks 440a, 440b, 440c and 440d in FIG. 4C, adjust the energy levels over time to control the proportion of energy per stream relative to the other streams as well as to control the combined energy level of all streams for improved FM modulation results. Therefore, the gain controller 418 in FIG. 4A may not be needed in certain embodiments of the invention.

In operation, one or more of a plurality of audio sources 410a, 410b, 410c and/or 410d may output digital audio signal streams 430a, 430b, 430c and/or 430d respectively, at source sampling rates which may be different from each other. The digital audio signal streams at different source sampling rates may be received by a plurality of rate adapters 412a, 412b, 412c and 412d which may be enabled by one same sink clock rate. In this regard, the different source sampling rates of the digital audio signal streams may be converted to the same sink sampling rate and output from the rate adapters as one or more rate-adapted digital audio signal streams 432a, 432b, 432c and 432d. Energy levels of the one or more rate-adapted digital audio signal streams may be scaled in scaling blocks 440a, 440b, 440c and 440d. The scaled digital audio signal streams may be summed in the summing block 416 and output from block 416 as a composite digital audio signal comprising an appropriate energy level for FM modulation. FM modulation may be performed in the digital domain and the FM modulated digital signal may be converted to analog by a digital to analog converter in block 420. In-phase and quadrature phase (Q) output may be generated by FM modulation block 420. In addition, the analog signal may be filtered, amplified coupled with an antenna and transmitted in block 422.

FIG. 4D is a flow chart illustrating exemplary steps for mixing digital audio signals from a plurality of audio sources in an FM transmitter, in accordance with an embodiment of the invention. Referring to FIG. 4D, there is shown a step 460 wherein a plurality of digital audio signal streams 430a, 430b, 430c and 430d, may be received by rate adaptors 412a, 412b, 412c and 412d from two or more digital audio sources. The plurality digital audio sources may be driven by independent source oscillators or may be enabled under one clock domain. The plurality of digital audio signal streams may comprise different source sample rates. In step 462, each of the one or more rate adaptors may adapt the different source sample rates to one same sink sample rate for the plurality of digital audio signal streams. The rate adaptors may utilize decimation, interpolation and/or fine grained rate adaptation.

In step 480, the energy level of the one or more of the plurality of digital audio streams with the same sink sampling rate 432a, 432b, 432c and 432d may be scaled for relative energy as well as a total energy level in scaling blocks 440a, 440b, 440c and 440d. In this regard, the scaling may determine the proportion of audible volume for each audible stream relative to the other audible streams after the plurality of streams have been transmitted via a speaker to a listener. The scaling may be adjusted over time to control desired audible effects. In addition, the energy level scaling of the plurality of digital audio streams may be adjusted such that the total energy may be appropriate for improved FM modulation.

In step 482, the plurality of scaled digital audio signal streams which were sampled at one same sink sample rate, are summed. In step 470, the composite digital audio signal may be FM modulated in the digital domain and then converted to an analog signal by a digital to analog converter in the FM modulation block 420. In step 474, the analog signal may be filtered and amplified. In step 475, the analog signal may be coupled with an antenna and transmitted.

In an embodiment of the invention, a plurality of digital audio signals from a plurality of sources are processed and transmitted via an FM transmitter as shown in FIG. 4A. The plurality of audio sources 410a, 410b, 410c and 410d may be clocked by different clock sources. Prior to transmission, the sample rates of the plurality of digital audio signals are converted to one same sample rate. A plurality of rate adapters 412a, 412b, 412c and 412d processing the digital audio signals may be clocked by one same sample rate.

In addition, the energy levels of the plurality of digital audio signals may be adjusted. In this regard, energy levels of individual signals may be adjusted relative to energy levels of other signals as shown in FIG. 4A414a, 414b, 414c and 414d as well as in FIG. 4C440a, 440b, 440c and 440d. Moreover, the total energy level of the plurality of digital signals may be adjusted prior to FM modulation to improve signal characteristics obtained from FM modulation. For example, in FIG. 4A block 418 the total energy level may be adjusted after the plurality of audio digital signals are combined in block 416. In another embodiment of the invention, the total energy level may be adjusted prior to combining as shown in FIG. 4C414a, 414b, 414c and 414d. In this regard, the total energy level adjustment may be performed before the plurality of digital audio signals are combined in block 416.

The combined digital audio signals may be FM modulated in the digital domain and converted to an analog signal in block 420. In block 422 the FM analog signal may for example, be filtered, amplified and coupled to an antenna for transmission.

Certain embodiments of the invention may comprise a machine-readable storage having stored thereon, a computer program having at least one code section for mixing a plurality of audio sources in an FM transmitter, the at least one code section being executable by a machine for causing the machine to perform one or more of the steps described herein.

Accordingly, aspects of the invention may be realized in hardware, software, firmware or a combination thereof. The invention may be realized in a centralized fashion in at least one computer system or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware, software and firmware may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

One embodiment of the present invention may be implemented as a board level product, as a single chip, application specific integrated circuit (ASIC), or with varying levels integrated on a single chip with other portions of the system as separate components. The degree of integration of the system will primarily be determined by speed and cost considerations. Because of the sophisticated nature of modern processors, it is possible to utilize a commercially available processor, which may be implemented external to an ASIC implementation of the present system. Alternatively, if the processor is available as an ASIC core or logic block, then the commercially available processor may be implemented as part of an ASIC device with various functions implemented as firmware.

The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context may mean, for example, any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form. However, other meanings of computer program within the understanding of those skilled in the art are also contemplated by the present invention.

While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A method for processing signals, the method comprising: converting in an FM radio, sampling rates for a plurality of input digital audio signals to a common sampling rate; andcombining within said FM radio, a corresponding plurality of converted digital signals resulting from said conversion into a single composite digital audio signal.

2. The method according to claim 1, comprising adjusting an energy level of at least a portion of said corresponding plurality of converted digital signals.

3. The method according to claim 1, comprising adjusting an energy level of each of said corresponding plurality of converted digital signals relative to each other.

4. The method according to claim 1, comprising adjusting an energy level of each of said corresponding plurality of converted digital signals prior to said combining and prior to FM modulation.

5. The method according to claim 1, comprising adjusting an energy level of each of said corresponding plurality of converted digital signals subsequent to said combining and prior to FM modulation

6. The method according to claim 1, wherein at least one of said plurality of input digital audio signals is clocked by a clock source that differs from at least a remaining portion of said plurality of input digital audio signals.

7. The method according to claim 1, comprising clocking a plurality of rate adapters utilized for said conversion at a common clock rate.

8. The method according to claim 1, comprising FM modulating said combined corresponding plurality of converted digital signals in digital domain.

9. The method according to claim 8, comprising converting said FM modulated combined corresponding plurality of converted digital signals to an analog signal.

10. The method according to claim 9, comprising transmitting said analog signal.

11. A system for processing signals, the system comprising: at least one processor that enables: conversion of sampling rates for a plurality of input digital audio signals to a common sampling rate within an FM radio; andcombining within said FM radio, a corresponding plurality of converted digital signals resulting from said conversion into a single composite digital audio signal.

12. The system according to claim 11, wherein said at least one processor enables adjustment of an energy level of at least a portion of said corresponding plurality of converted digital signals.

13. The system according to claim 11, wherein said at least one processor enables adjustment an energy level of each of said corresponding plurality of converted digital signals relative to each other.

14. The system according to claim 11, wherein said at least one processor enables adjustment of an energy level of each of said corresponding plurality of converted digital signals prior to said combining and prior to FM modulation.

15. The system according to claim 11, wherein said at least one processor enables adjustment of an energy level of each of said corresponding plurality of converted digital signals subsequent to said combining and prior to FM modulation

16. The system according to claim 11, wherein said at least one processor enables, clocking of at least one of said plurality of input digital audio signals by a clock source that differs from at least a remaining portion of said plurality of input digital audio signals.

17. The system according to claim 11, wherein said at least one processor enables clocking a plurality of rate adapters utilized for said conversion at a common clock rate.

18. The system according to claim 11, wherein said at least one processor enables FM modulation of said combined corresponding plurality of converted digital signals in digital domain.

19. The system according to claim 18, wherein said at least one processor enables conversion said FM modulated combined corresponding plurality of converted digital signals to an analog signal.

20. The system according to claim 19, wherein said at least one processor enables transmission of said analog signal.

21. A machine-readable storage having stored thereon, a computer program having at least one code section for processing signals, the at least one code section being executable by a machine for causing the machine to perform steps comprising: converting in an FM radio, sampling rates for a plurality of input digital audio signals to a common sampling rate; andcombining within said FM radio, a corresponding plurality of converted digital signals resulting from said conversion into a single composite digital audio signal.

22. The machine-readable storage according to claim 21, wherein said at least one code section comprises code for adjusting an energy level of at least a portion of said corresponding plurality of converted digital signals.

23. The machine-readable storage according to claim 21, wherein said at least one code section comprises code for adjusting an energy level of each of said corresponding plurality of converted digital signals relative to each other.

24. The machine-readable storage according to claim 21, wherein said at least one code section comprises code for adjusting an energy level of each of said corresponding plurality of converted digital signals prior to said combining and prior to FM modulation.

25. The machine-readable storage according to claim 21, wherein said at least one code section comprises code for adjusting an energy level of each of said corresponding plurality of converted digital signals subsequent to said combining and prior to FM modulation

26. The machine-readable storage according to claim 21, wherein said at least one code section comprises code for clocking at least one of said plurality of input digital audio signals by a clock source that differs from at least a remaining portion of said plurality of input digital audio signals.

27. The machine-readable storage according to claim 21, wherein said at least one code section comprises code for clocking a plurality of rate adapters utilized for said conversion at a common clock rate.

28. The machine-readable storage according to claim 21, wherein said at least one code section comprises code for FM modulating said combined corresponding plurality of converted digital signals in digital domain.

29. The machine-readable storage according to claim 28, wherein said at least one code section comprises code for converting said FM modulated combined corresponding plurality of converted digital signals to an analog signal.

30. The machine-readable storage according to claim 29, wherein said at least one code section comprises code for transmitting said analog signal.