Method and system for performing digital signal processing operations in a computer system

Abstract

A method and system for performing digital signal processing operations in a computer system are disclosed. Digital Signal Processing operations such as multiply and add (MADD) or multiply and subtract (MSUB) can be performed by general-purpose microprocessors. The DSP operations are directed to n-bit operands that are in m-bit registers. The register size (m) may be a multiple of the operand size (n). For example, the DSP operations may utilize 32-bit registers with 16-bit or 8-bit operands, or the DSP operations may utilize 64-bit registers with 32-bit, 16-bit, or 8-bit operands.

Description

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[Not Applicable]

[MICROFICHE/COPYRIGHT REFERENCE]

[Not Applicable]

BACKGROUND OF THE INVENTION

Digital Signal Processing (DSP) is the processing of a stream of information by digital means. A common DSP application is the filtering of signals to improve signal quality or to extract important information. For example, an analog signal can be digitized using a device, such as an analog-to-digital converter, to generate an output in the form of binary numbers that represent the analog signal. As an alternative to using analog electronics, DSP techniques can process the digitized analog signal.

Although the mathematical theory underlying DSP techniques such as digital filter design and signal compression can be complex, the numerical operations required to implement these techniques comprise multiplication, addition, subtraction, and binary shifting. The ability to perform DSP techniques on multiple hardware platforms is important for various applications.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

The present invention discloses a method and system for performing digital signal processing operations in a computer system. Digital Signal Processing (DSP) operations such as multiply and add (MADD) or multiply and subtract (MSUB) can be performed by general-purpose microprocessors. The DSP operations are directed to n-bit operands that are in m-bit registers. The register size (m) may be a multiple of the operand size (n). For example, the DSP operations may utilize 32-bit registers with 16-bit or 8-bit operands, or the DSP operations may utilize 64-bit registers with 32-bit, 16-bit, or 8-bit operands.

The location of a binary signal value in a larger microprocessor register is appended to the instructions. The instructions define the location of the operand with the register eliminating the need for addition shift operations.

These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of an exemplary architecture for performing Digital Signal Processing operations in a computer system in accordance with an embodiment of the present invention;

FIG. 2 is an illustration of an exemplary set of operations that may be practiced in accordance with an embodiment of the present invention; and

FIG. 3 is a flowchart illustrating an exemplary method for performing a Digital Signal Processing operation in a computer system, in accordance with a representative embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Aspects of the present invention relate to digital signal processing (DSP) operations and more specifically, to the execution of these operations in a computer system. Although the following description may refer to particular operations, other operations requiring multiplication and accumulation may be performed without departing from the spirit and scope of the present invention. For example, operations with a 32-bit register may utilize 16-bit operands, and operations with a 64-bit register may utilize 32-bit operands, 16-bit operands or 8-bit operands. Operand size may be a fraction of the size of the register.

FIG. 1 is an illustration of an exemplary architecture 100 in which a representative embodiment of the present invention may be practiced. The architecture 100 may comprise registers 101 and 103, a multiplier 109, a left shifter 111, an inverter 113, and an accumulator 115.

The first register 101 will receive a first operand 117. The second register 103 will receive a second operand 119. The bit width of the registers 101 and 103 may be larger than the bit width of the operands 117 and 119, and the register may be a multiple of the bit width of the operands 117 and 119. For example, the registers 101 and 103 may by 32 bits wide and the operands 117 and 119 may be 16 bits wide. If the operands 117 and 119 are 16 bits wide and the registers are 32 bits wide, the 16-bit operands 117 and 119 need to be placed in 32-bit registers 101 and 103 before the DSP operation can begin.

The operands 117 and 119 in the registers 101 and 103 are multiplied in the multiplier 109 to produce a product 133. The ased on a first shift register control bit at 125. The control signal at 125 can identify the location of the first operand 117 in the first register 101, and the control signal at 127 can identify the location of the second operand 119 in the second register 103. For example, a 16-bit wide operand may occupy an upper portion or a lower portion of a 32-bit wide first register.

A left shift of one position can be performed on the product 133 based on a shift control bit 135. Furthermore, the output of the left shifter 137 can be saturated to 0x7fffffff if the product 133 is 0x40000000.

The inverter 113 can negate the output of the left shifter 137 based on a subtraction bit 139. The inverter output 141 is sent to the accumulator 115 where it can be added to the content 143 of the accumulator 115. If overflow or underflow occurs when adding the shifted multiplication result to the content 143 of the accumulator 115, then the result is saturated to the maximum or minimum signed integer value. For a 32-bit accumulator register 0x7fffffff is the saturation value for a positive overflow and 0x80000000 is the saturation value for a negative overflow (underflow). A flag may be set to indicate overflow or underflow.

A set of instructions can be added to a control processor of a system to provide Digital Signal Processing (DSP) computational capability. The control processor can be a 32-bit processor, wherein each general purpose register is 32-bit wide, and the operands of the DSP computations can be 16-bit wide or less.

For example, a DSP operation could be ‘multiply and add’ (MADD) and have a format: MADD rs, rt, n

The operation performs a multiplication of the contents of the general purpose registers rs and rt, adds the multiplication result to the accumulator, and saves the final result in the n-th accumlator. Similarly, a DSP operation could be ‘multiply and subtract’ (MSUB) and have a format: MSUB rs, rt, n

An instruction set can also be extended to indicate a shift operation as required for some fixed-point formats. An instruction set can be extended further to indicate location an operand may occupy in a register of larger bit width. For example, a DSP operation could be ‘multiply operands, add the product to the accumulator, shift the product prior to the addition, the first operand is in a high position, and the second operand is in a low position’ and have a format: MADDSHL rs, rt, n

An exemplary set 200 of instructions that can be performed in a computer system are shown in FIG. 2. The instructions can correspond to op-codes comprising bits that indicate control signals 125, 127, 135, and 139 as described in reference to FIG. 1. M at 201 corresponds to ‘Multiply’. The bit b3 at 203 can indicate ‘ADD’ or ‘SUBtract’ and can also be used as bit 139 in FIG. 1. The bit b2 at 205 can indicate ‘no shift’ or ‘left Shift’ and can also be used as bit 135 in FIG. 1. The bits b1 and b1 at 207 and 209 can indicate that the operands occupy the ‘High’ or ‘Low’ portion of the registers and can also be used as control bits 125 and 127 in FIG. 1.

Although a one-to-one correspondence between bits in FIG. 1 and FIG. 2 is described, there may be elements of logic between actual bits of an op-code and the control of options in a set of DSP instructions.

FIG. 3 shows a flowchart illustrating an exemplary method performing a 16-bit operation in a 32-bit system, in accordance with a representative embodiment of the present invention.

A first operand is loaded into a first register at 301. The location of the first operand is identified at 303. For example, a 16-bit operand can occupy either the upper portion or the lower portion of the first register.

A second operand is loaded into a second register at 305. The location of the first operand is identified at 307.

The content of the first operand, located in the first register, is multiplied by the content of the second operand, located in the second register, to produce a product at 309. A third register is modified based on the product at 311. The third register can be an accumulator, and the modification to the accumulator can be and addition of subtraction of the product. To account for the format of the operands, a left shift may be included prior to the accumulator modification.

Although the above description refers to examples using 16-bit DSP operations and 32-bit computer system registers, the present invention is not limited to the particular aspects described. Variations of the examples provided above may be applied to a variety of DSP operations without departing from the spirit and scope of the present invention.

Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in an integrated circuit or in a distributed fashion where different elements are spread across several circuits. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.

While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A method for performing a digital signal processing operation, wherein the method comprises: loading a first operand into a first location of a first register; loading a second operand into a second location of a second register; and multiplying the first register by the second register to produce a product.

2. The method of claim 1, wherein the first operand comprises 16 bits, the first register comprises 32 bits, and the first location is an upper portion of the first register.

3. The method of claim 1, wherein the first operand comprises 16 bits, the first register comprises 32 bits, and the first location is a lower portion of the first register.

4. The method of claim 1, wherein the second operand comprises 16 bits, the second register comprises 32 bits, and the second location is an upper portion of the second register.

5. The method of claim 1, wherein the second operand comprises 16 bits, the second register comprises 32 bits, and the second location is a lower portion of the second register.

6. The method of claim 1, wherein the method further comprises: modifying a third register with the product.

7. The method of claim 6, wherein the modifying is adding.

8. The method of claim 6, wherein the modifying is subtracting.

9. The method of claim 6, wherein the method further comprises: shifting the product prior to modifying the third register with the product.

10. A system for performing a digital signal processing operation: a first register for storing a first operand, wherein the first operand occupies a first location in the first register; a second register for storing a second operand, wherein the second operand occupies a second location in the second register; and a multiplier for multiplying the first register by the second register to produce a product.

11. The system of claim 10, wherein the first operand comprises 16 bits, the first register comprises 32 bits, and the first location is an upper portion of the first register.

12. The system of claim 10, wherein the first operand comprises 16 bits, the first register comprises 32 bits, and the first location is a lower portion of the first register.

13. The system of claim 10, wherein the second operand comprises 16 bits, the second register comprises 32 bits, and the second location is an upper portion of the second register.

14. The system of claim 10, wherein the second operand comprises 16 bits, the second register comprises 32 bits, and the second location is a lower portion of the second register.

15. The system of claim 10, wherein the system further comprises: a left shifter for selectively shifting the product.

16. The system of claim 10, wherein the system further comprises: an inverter for selectively inverting the product.

17. The system of claim 10, wherein the system further comprises: an accumulator for adding a third register to the product.