Patent Application
20080109782
I. Field
This disclosure relates to methods and systems for performing signal pin assignments in high pin-count devices, such as field programmable gate arrays and/or application specific integrated circuits.
II. Description of Related Art
Field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs) are two types of devices that are often used during product development of electronic systems. FPGAs and/or ASICs are typically used during the process of product development to “debug” a system design in order to determine a “final” design that may then implemented in a final product that is sold to customers. The final system design may or may not include FPGAs and/or ASICs. For instance, circuits implemented in the FPGAs and/or ASICs during system development may be implemented in custom designed integrated circuits in the “final” product.
Both FPGAs and ASICs allow product designers to quickly make changes to a product (e.g., circuit) design during the development phase of a system or product (e.g., such as a microprocessor). For instance, FPGAs and ASICs contain standard circuit elements (such as logic gates, input/output structures, etc.) that may be connected to one another to implement a desired device, or circuit design. By changing the connections in the FPGA or ASIC device, iterations of the design can be tested relatively quickly as compared to reproducing the entire design (e.g., an entire new microprocessor component).
In the case of FPGAs, the various circuit elements implemented in an FPGA electronic device are selectively connected to one another using electrically programmable interconnects. Such interconnects may be implemented using, for example, flash memory cells. Because interconnects in an FPGA are electrically programmable (and erasable), changes to a system or product design can be made very quickly and often without even removing the FPGA from a printed circuit board in which it is included, where the system or product design is implemented using the printed circuit board. This allows for very quick evaluation of design “fixes” during product debug. FPGAs, however, are generally slower and less complex than ASIC devices. Also, FPGAs typically consume more power than comparable ASIC devices.
ASIC devices, on the other hand, are generally faster (have better circuit performance), allow for implementing more complex designs and consume less power than comparable FPGA devices. However, in contrast to FPGAs, the various circuit elements implemented in ASIC devices are selectively interconnected using masking layers, such as contact layers and/or metal layers of a semiconductor process used to manufacture the ASIC device. Therefore, implementing design changes in an ASIC device takes longer than in an FPGA, as one or more masking layers for the ASIC device must be produced to implement each iteration of a particular design. The decision whether to use an FPGA or an ASIC, accordingly, depends on the particular situation.
FPGAs and ASICs, notwithstanding their relative complexity, are generally, what may be termed, high pin-count devices. For instance, FPGAs and ASICs may be assembled in electronic device packages (e.g., ball-grid arrays) that have hundreds of package pins, which include power supply pins, signal pins, special function pins, among any number of other types of package pins. A device design (e.g., a circuit design) may be implemented in an FPGA or ASIC by assigning “logical pins” of the device design to package pins of the FPGA or ASIC. “Logical pins” of the device design may be defined as signals used in the device design that must be externally accessible (e.g., input and output signals of the device design) once the device design is implemented in the FPGA or ASIC.
Assigning the logical pins of a device design to the package pins of an FPGA or ASIC device may be a very complex process. For instance, the process of assigning the logical pins to the package pins must take into account a number of factors, such as the compatibility of the properties of the logical pins with the properties of the package pins, timing considerations for the input and output signals of the device design, and board layout considerations for implementing the FPGA or ASIC in a system board, among any number of other considerations that must be taken into account when assigning the logical pins to the package pins. Current approaches for making such logical pin to package pin assignments have certain drawbacks.
One approach that is currently used for assigning logical pins to device design pins is to perform a manual assignment of the logical pins to the package pins. In such an approach, a design engineer manually selects the package pin that is to be assigned to each logical pin of the device design. For designs of even moderate complexity, such a process is highly labor intensive and requires a great amount of skill on the part of the engineer performing the pin assignments. As the complexity of the device design being implemented increases, the ability to achieve an acceptable set of logical pin to package pin assignment becomes non-practical using such a manual approach.
A second approach that is used for assigning logical pins to package pins is the use of graphical tools that assist in the assignment process. Such tools provide a visual representation of the FPGA or ASIC device. The visual representation of the FPGA or ASIC illustrates the limitations and/or properties of the package pins (such as through color coding or shading). Such tools may also provide an engineer making logical pin to package pin assignments with an indication when the properties of a logical pin do not match the properties of a package pin or a signal pin bank in which the package pin is included. As is known, signal pins in FPGA devices may be divided into “signal pin banks”, where the signal pin banks share certain properties, such as power supply voltage, input reference voltage and differential reference voltage, as some examples. While an improvement over a completely manual assignment approach, the use of such graphical tools is still a highly labor intensive process and requires a significant amount of skill on the part of the design engineer performing the assignment, especially for more complex designs.
A third approach for performing logical pin to package pin assignments is the use of automated place and route software. In the first two approaches discussed above, logical pin to package pin assignments may be performed before completion of the device design to be implemented in an FPGA or ASIC, such approaches may reduce system development time, as system board layout and the process of designing the device being implemented in the FPGA may be done in parallel. However, in the third approach, system board design cannot be done in parallel as the logical pin to package pin assignments are not completed until after the device design is complete. Additionally, place and route software applications do not take into account timing considerations and location of interfaces of device design to other components on the system board (e.g., board layout considerations).
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.
The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools and methods which are given by way of example and meant to be illustrative, not limiting in scope. In various embodiments, one or more of the above-described problems have been reduced or eliminated, while other embodiments are directed to other improvements.
Methods and systems for assigning package pins of an electronic device to logical pins of a device design to be implemented on the electronic device are disclosed. One example method includes receiving a technology description file for the electronic device, where the technology description file includes a catalog of information for the electronic device. The catalog of information for the electronic device may include a description of each package pin of the electronic device including, for each package pin: (i) a signal bank assignment, (ii) a pin type, (ii) a physical location and an (iv) electronic device pin name. The catalog of information for the electronic device may further include a description of each type of input/output structure available on the electronic device. The description for each type of input/output structure may include one or more of: (i) input and output voltages, (ii) input reference voltages and (iii) differential reference voltages, which may be used to determine signal pin bank properties.
The example method further includes receiving a design description file for the device design, where the design description file includes a catalog of information for the device design, such as information regarding the input and output properties of the design. The catalog of information for the device design may include, for each logical pin of the device design: (i) a device design pin name, (ii) an input/output type, an input/output direction; and (iii) assignment heuristics, where the assignment heuristics include information for assigning the logical pins to the package pins, such as direct pin assignments and signal bank limitations, for example.
The example method also includes creating a database from the technology description file and the design description file. The database may be created by combining the information in the catalog of information for the electronic device and the catalog of information for the device design. The database is then used to programmatically assign the package pins of the electronic device to the logical pins of the device design.
In particular methods, the package pins of an electronic device are assigned to logical pins of a device design in multiple passes. In such an approach, logical pins of the device design that have assignment heuristics that include a direct pin assignment may be assigned in a first pass (e.g., a first pass through the database). Logical pins of the device design with assignment heuristics that include a bank limitation may be assigned in a second pass. A bank limitation may be defined as a limitation on the signal pin banks of the electronic device to which a particular logical pin may be assigned. Such a bank limitation may be defined for timing considerations, board layout considerations, or for any number of other reasons. After completion of the first two passes for assigning package pins to the logical pins, logical pins of the device design with assignment heuristics that include an unrestricted assignment designator may be assigned. Logical pins with unrestricted assignment designators may be assigned to any available package pin with compatible signal pin bank and package pin properties.
Once assignment of package pins to logical pins is complete, the example method may further include creating one or more output files including the pin assignments. For instance, a file that may be used by place and route software may be generated. Additionally, a spreadsheet file that graphically illustrates the package pin to logical pin assignments may be generated as an alternative to, or in addition to the place and route output file. Depending on the particular embodiment, other output files may also be generated, such as a list of restrictions for system board layout for a printed circuit board in which the electronic device will be implemented.
Exemplary embodiments are illustrated in referenced figures of the drawings. It is intended that the embodiments and figures disclosed herein are to be considered illustrative rather than restrictive.
Methods for assigning package pins of an electronic device, such as a field programmable gate array (FPGA) and/or an application specific integrated circuit (ASIC) are disclosed. Such methods may be implemented using a computer workstation that includes a machine readable medium storing instructions that, when executed, implement such methods. For the sake of clarity, the methods described herein will be described generally with reference to FPGA devices. However, it will be appreciated that the methods described herein may also be used for assigning package pins for ASIC devices or any number of other types of devices.
Part of the process of implementing a device design using an FPGA (or an ASIC) is the process of assigning package pins of a particular FPGA device to logical pins of the device design, where the logical pins of the device design correspond with the input and output signals of the device design. As part of the process of assigning package pins to logical pins, a number of considerations may be taken into account. For instance, timing considerations for the signals associated with the logical pins may be considered, as well as the physical location of the package pin assignments for the logical pins on the FPGA device (e.g., for circuit board layout considerations). When assigning package pins to logical pins, the compatibility of the properties of the package pins with the properties of the logical pins is also considered. For instance, a package pin with a 3.3V power supply voltage should not be assigned to a logical pin that is defined as a 2.5V input/output structure. In such a case, the package pin properties would be incompatible with the logical pin properties.
The method 100 may be used for assigning package pins of an FPGA device to logical pins of a device design, while taking into account considerations such as those noted above. The method 100 includes, at block 110, receiving a technology description file, such as at a computer workstation. In this situation, the technology description file of the method 100 is a data file that is readable by a workstation implementing the method 100.
The technology description file received at block 110 includes a catalog of information about a particular FPGA device and electronic device package combination (the “FPGA device” or “FPGA”). For instance, the technology description file includes descriptive information regarding the particular FPGA device, such as (i) a listing of the package pins of the FPGA device, (ii) information regarding the groupings of pins in particular signal pin banks, and (iii) information regarding the types of input/output structures available on the particular FPGA device, among any number of other details about the FPGA device that could be used in the process of assigning package pins of the FPGA to logical pins of a device design. The technology description file is specific to a particular FPGA device/electronic device package combination. Accordingly, once prepared, a given technology description file may be used for assigning package pins of a particular FPGA device included in a particular electronic device package (e.g., a 512 pin ball-grid array) to logical pins of any device design that is to be implemented on that particular combination.
The method 100 also includes receiving a design description file at block 120. The design description file of the method 100 may also be a data file that is readable by a workstation implementing the method 100. The design description file includes a catalog of information regarding a particular device design to be implemented on an electronic device, such as an FPGA (or ASIC). In the examples described herein, the design description file includes information only about the input and output structures of a given device design. For these examples, the design description file does not include a complete description of the given device being implemented. For instance, the design description file includes descriptions of the logical pins of the device design that are to be assigned to package pins of the FPGA device on which the design is to be implemented. The design description file may also include information regarding groupings of logical pins (e.g., buses) and properties of the logical pins (e.g., input/output type, reference voltages, etc.).
Additionally, the design description file may include assignment heuristics that are used in assigning package pins of an FPGA to logical pins of a device design. The assignment heuristics may define criteria for pin assignments such as (i) direct pin assignments, (ii) limitations on the signal pin banks of the FPGA to which given logical pins can be assigned. Alternatively, the assignment heuristics for certain logical pins may not include any limitations on assignment. In this situation, such logical pins may be assigned to any package pin where the signal pin bank properties (e.g., power supply voltage) and package pin properties (e.g., pin function) are compatible with the logical pin properties of those “unrestricted” pins.
The method 100 further includes, at block 130, creating a pin assignment database from the technology description file and the design description file. The pin assignment database may be created by simply combining the information in the technology description file with the information in the design description file. The database may take the form of a spreadsheet or, alternatively, could be implemented in a database application, such as a relational database application. Regardless of the particular form of the pin assignment database, the information in the pin assignment database is used for assigning package pins of the FPGA device described in the technology description file to logical pins of the device design described in the design description file.
The method 100 further includes, at block 140, programmatically assigning package pins of the FPGA device described in the technology description file to the logical pins of the device design described in the received design description file. The pin assignments may be accomplished using a computer workstation that includes a machine readable medium which stores instructions that, when executed, assign package pins of the FPGA to logical pins using the information included in the pin assignment database. The machine readable medium storing the instructions may be physically included in the computer workstation or, alternatively, may be accessed by the work station over a computing network.
For the pinout 200, package pins are arranged in rows 210 and columns 220. The rows 210 for the pinout 200 are designated with the letters A-F and the columns 220 are designated with the numbers 1-6. Physical pin locations of the pinout 200 are referred to by their corresponding row and column intersection. For instance, the package pin the in upper left corner of the pinout 200 is referenced as pin A1. Likewise, the pin in the bottom right corner of the pinout 200 is referred to as pin F6.
As shown in
Pins F3 and F4 of the pinout 200 are designated ‘C’, which indicates that these pins are configuration pins for an FPGA corresponding with the pinout 200. In
Methods for assigning package pins to logical pins as described herein may also include producing one or more output files that include the assignments made by such methods.
The output file 300 may include a listing of each package pin of the pinout 200 and its corresponding logical pin assignment. Further, the output file 300 may include additional information, such as information for use in implementing a corresponding device design in the FPGA corresponding with the pinout 200. This additional information may include signal bank properties, such as supply and reference voltages, for example. Furthermore, the output file 300 may be in a format that is usable by a place and route application, such as in a data file that may be termed a “constraints file.” The output file 300 may then be used in conjunction with the design of a printed circuit board in which the associated FPGA device used to the implement the device design is to be used.
In the output file 400, in like fashion as in
The output files described above with respect to
The table 500 in
It will be appreciated that the table 500 does not list every package pin for the package pinout 200 illustrated in
In row 525, package pin F3 of the package pinout 200 illustrated in
One of the power supply package pins (A1) and one of the ground pins (F1) of the package pinout 200 illustrated in
In row 540, package pin A2 of the package pinout 200 illustrated in
The table 500 includes example information and package pin descriptions that may be included in a technology description file. It will be appreciated that a technology description file used for pin assignments in the methods described herein would list each package pin of an FPGA for which pin assignments are being made, along with a corresponding description of each pin. Further, any number of other pin types and/or functions may be included in such a technology description file. For instance, reference voltage package pins may be defined to provide input reference voltages, differential references voltages, or any other appropriate reference voltages that may be used for a particular FPGA device. Also, where appropriate, any number of additional types of configuration pins may be described in such a technology description file. For instance, JTAG pins may be implemented in an FPGA device and described in a corresponding technology description file. Still further, other types of signal pins may be described in a technology description file. For instance, such signal pins may include differential pairs, input only pins and output only pins, among any number of other possible signal pin types.
The table 600 in
The IO structures discussed below with respect to
The table 600 includes columns 605,610,615,620 and rows 635,640,645,650,655. Each row describes a specific IO structure with information for each IO structure being included in the columns of the table 600. For example, each row of column 605 in the table 600 includes a designator “GROUP”. The GROUP designator is used to group compatible IO structures together in the technology description file. For instance, as shown in column 610 of the table 600, the structures described in rows 635,640 are designated as being part of GROUP “33V”, which indicates that the IO structures described in rows 635,640 operate at a power supply voltage of 3.3V and are, therefore, compatible with respect to operating voltage (e.g., may be located in the same signal pin bank due to their same operating voltage).
In
Column 620 in
The IO structures described in rows 645,650,655 are all part of a GROUP 25V (e.g., use a 2.5 V operating voltage), as is indicated in column 610 of these rows. The IO structures of GROUP 25V are designated IO25_1 in row 645, IO25_2 in row 650 and DIFF_25 in row 655. While these structures are compatible with respect to operating voltage, they may not be located in the same signal pin banks due to their reference voltages. For instance, the IO structure IO25_1 uses a reference voltage of 0.8 V, as is indicated in column 620 of row 645. In comparison, the IO structure IO25_2 uses a reference voltage of 0.9V, while the IO structure DIFF_25 uses a reference voltage of 1.1 V. Because each of the IO structures of the GROUP 25V uses a different reference voltage, package pins of a corresponding FPGA that are assigned to logical pins of a device design using these IO structures would be located in signal pin banks with bank properties that match both their operating voltage (2.5 V) and their respective reference voltages. Those working in this area will appreciate that additional IO structures may be described in such a technology description file that are compatible with one, or all of the IO structures of the GROUP 25V (e.g., a 2.5 V IO structure that does not use a reference voltage).
The design description file represented by the table 700 includes groups of signal pins. The signal groups are designated in column 705 of the table 700. Column 710 lists the logical pin signal names of the device design for each of the signal groups designated in column 705. In the table 700, listings of signal groups each begin with a designation of a group name in column 705. The signal pins of each signal group are then listed on subsequent lines of the table 700. Each designation in column 705 indicates the beginning of a new signal group. Of course, alternative approaches may be used separating signal groups in the table 700. For instance, blank lines could be used to separate signal groups in the table 700. Such an approach would allow for readily defining signal groups that include only a single logical pin or defining groups of related pins. For such groups, a signal group designation may, or may not be included in column 705.
Using methods for assigning package pins to logical pins as described herein, the logical pins of each signal group of the table 700 may be assigned to FPGA package pins in sequence in order to assure that related logical pins are assigned in close physical proximity to one another on the FPGA package (e.g., for timing considerations or physical location on the FPGA package).
In
Respective signal directions of the logical pins of the device design of
Column 725 of the table 700 includes assignment heuristics for the logical pins listed in the design description file of
The table 700 includes four signal groups. The first signal group 735 is designated “CONFIG” in column 705. The CONFIG signal group 735 includes two logical pins “DEV_CFG1” and “DEV_CFG2”, as indicated respectively in column 710 on the two lines following the designation of the CONFIG signal group 735 in column 705. DEV_CFG1 and DEV_CFG2 are single logical pins (bus width of “1”) that are to be assigned to package pins of an FPGA. The width of “1” for these logical pins is indicated in column 715 of the table 700. Further, DEV_CFG1 is designated as an input only pin in column 720, while DEV_CFG2 is designated as an output only pin.
As noted above, column 725 of the table 700 includes assignment heuristics for the logical pins of a device design represented by the design description file of
Both the assignment heuristics (in column 725) and the designations of the IO structures to use (in column 730) may be designated for a signal group as a whole (e.g., for the CONFIG signal group 735), or may be designated for each logical pin (or bus) individually. For instance, column 730 of the table 700 designates the IO structure IO33_2 should be used with assigning logical pins of the CONFIG signal group 735 to package pins of the FPGA. However, column 730 also designates the IO structure of DEV_CFG2 as IO33_1. In this situation, the designation for the individual logical pin (DEV_CFG2) would override the signal group designation for the CONFIG signal group 735. Also, individual logical pin assignment heuristics may override signal group assignment heuristics in a similar fashion.
Using the foregoing approach for the device design of
The table 700 of
The assignment heuristics of the BUS1 signal group are designated in column 725 as “@1DN” for the entire signal group. The designation of @1DN for assignment heuristics is what may be termed a bank limitation with an order designation. The “@” symbol is an indication that the logical pins associated with this assignment heuristic are to be assigned only to logical pins in a specific signal pin bank (or banks) of the FPGA. In this example, the pins are only to be assigned to bank 1 of an FPGA associated with the package pinout 200 shown in
The assignment heuristics for the BUS1 signal group 740 further includes an order designator of “DN” (down). The DN order designator indicates, for this assignment heuristic, that the pins of bank 1 of the pinout 200 should be assigned from top to bottom in the order they are listed in the pin assignment database. For instance, assuming the pins of bank 1 are listed in row-wise fashion in the pin assignment database (e.g., A2, A3, B1, B2 . . . ), the logical pins of the signal group BUS1 would be assigned to available package pins in bank 1 of the pinout 200 starting with pin A2 and proceeding through the list of package pins in order.
Assuming that all of the pins in bank 1 are available, assigning package pins to the logical pins of the BUS1 signal group in the above described situation would result in the following pin assignments. The logical pin DEV_CLK1 would be assigned to the package pin A2 of the pinout 200 as input only pins using IO33_1 as an input structure. The four logical pins of the bus DATA1 would be assigned to package pins A3, B1, B2 and B3 in sequence as input/output pins using IO33_1 as an IO structure.
Alternatively, an order designator of “UP” (up) could have been used in the assignment heuristic for the BUS1 signal group 740 instead of the DN order designator. In this situation, logical pins of the BUS1 signal group 740 would be assigned to package pins of the pinout 200 starting with the last pin of bank 1 (e.g., C3) and proceeding up the listing in order (e.g., C3, C2, C1, B3 . . . ).
The description of the BUS2 signal group 745 in the device description file of
The assignment heuristics for the BUS2 signal group 745 are designated as “@2NE.” As with the assignment heuristics for the BUS1 signal group 740, the @2NE assignment heuristic is a bank-limited assignment heuristic, which indicates that the logical pins of the BUS2 signal group 745 are only to be assigned to bank 2 of the pinout 200 shown in
The assignment heuristic for the BUS2 signal group 745 includes a directional designator of “NE” (north-east), as compared to an order designator (e.g., DN). The NE order designator for this assignment heuristic indicates that the pins of bank 2 of the pinout 200 should be assigned from south to north and west to east using standard map coordinates overlaid on the pinout 200. For instance, assuming that all the pins of bank 2 are available, the logical pins of the signal group BUS2 would be assigned as follows. The logical pin DEV_CLK2 would be assigned to the package pin E1 of the pinout 200. The four logical pins of the bus DATA1 would be assigned to package pins D1, F2, E2 and D2 in sequence.
Alternatively for the NE directional designation, the package pins of the pinout 200 could be assigned to the logical pins of the BUS2 signal group 745 in a serpentine directional fashion, first moving north, then moving east one column, then moving south. In this situation, the package pins of bank 2 would be assigned to the logical pins of the BUS2 signal group 745 as follows. The logical pin DEV_CLK2 would be assigned to the package pin E1 of the pinout 200. The four logical pins of the bus DATA1 would be assigned to package pins D1, D2, E2 and F2 in sequence. Depending on the particular embodiment, a different directional designator may be used for such an approach.
Other combinations of map coordinates may be used as directional designators for assignment heuristics. Each of these combinations would include (i) one of north and south and (ii) one of east and west. Therefore, the list of possible directional indicators includes NE, NW, EN, WN, SE, SW, ES and WS, though others could be used. Such directional designators may be applied in the fashions described above, or in any other appropriate way.
The MISC pin group 750 includes logical pins “MISC_1” and “MISC_2”, where each has a width of “1” designated in column 715. MISC_1 is an input only pin, while MISC_2 is an input/output pin using IO25_2 from the table 600 as an IO structure.
MISC_1 has assignment heuristics that are designated as “PU33V.” Such assignment heuristics may be termed as specific-purpose or specific-function assignment heuristics. The PU33V designation, for this example, indicates that the logical pin MISC_1 should be assigned to a package pin of the pinout 200 that is able to operate as a 3.3 V pull-up device (e.g., does not include a pull-down structure). Depending on the particular FPGA device being used to implement the device design described in the table 700, only certain package pins of the pinout 200 may support such an operation. Thus, based on the PU33V assignment heuristic, the logical pin MISC_1 would be assigned to an available pin of the pinout 200 that supports the specific function of operation as a 3.3V pull-up. Of course, other special-purpose or special-function assignment heuristics are possible, such as JTAG interface pins or scan chain functions, for example. For purposes of package pin to logical pin assignments, special-purpose or special-function assignment heuristics may be considered to be direct pin assignment heuristics due to the fact that there may be a limited number of package pins that support the desired function or purpose of the logical pin.
As shown in
The method 900 includes, at block 910, selecting a logical pin with direct assignment heuristics (direct assignment logical pin) from the database. As discussed above, logical pins with special-purpose or special-function assignment heuristics may also be considered to be direct assignment logical pins and, therefore, may also be selected at block 910. In the method 900, package pins are assigned to logical pins of the device design in the order that the logical pins are listed in the pin assignment database. Therefore, at block 910 the first direct assignment logical pin listed in the pin assignment database that has not previously been assigned to a package pin is selected.
Applying the method 900 to the device design of
At block 920 of the method 900, a determination is made whether the package pin (or special-purpose pin) specified in the direct pin assignment heuristics of the selected logical has already been assigned to another logical pin of the device design. If the specified package pin (or special-purpose pin) has already been assigned to another logical pin, the method 900 will move to block 930 and a failure of the method will be indicated to a user (e.g., engineer) implementing the method 900 on, for example, a computer workstation. Once a failure is indicated, assignment of package pins to logical pins typically is halted. This approach allows the user to modify the design description file to address the reason for failure of the pin assignment method. This approach is generally applied for handling indications of failure in the methods described herein.
In the event that the specified package pin (or special-purpose pin) has not been previously assigned, the method 900 then moves to block 940 where a determination is made whether bank properties have been previously assigned to the signal pin bank in which the specified package pin is included. If bank properties have not been assigned, the method 900 moves to block 950, where bank properties are assigned to the signal pin bank that includes the specified package pin. The bank properties are assigned in accordance with the properties of the selected logical pin. For instance, in this example, the selected logical pin is the DEV_CFG1 logical pin.
Referring to
Once bank properties are assigned (or a determination has been made that bank properties were previously assigned), the method 900 moves to block 960 where a comparison of the properties of the selected logical pin is made with package pin properties of the specified package pin. Additionally, if the bank properties were previously assigned, a comparison of the logical pin properties with the previously assigned bank properties is made. If it is determined, at block 960, that the package pin properties and/or the bank properties of the specified package pin are not compatible with the properties of the logical pin, as specified in the pin assignment database (e.g., from the design description file), the method 900 moves to block 930 and a failure of the method will be indicated to a user and handled in a manner as described above.
In the event that the package pin properties and bank properties of the specified package pin are compatible with the selected logical pin, the method 900 moves to block 970 and the specified package pin is assigned to the selected logical pins. Additionally, the bank properties for the signal pin bank in which the specified package pin is included are updated based on any bank property assignments made at block 950. The package pin assignments and updated bank properties may be included in one or more output files that are used by other design tools (e.g., place and route applications) for example. The output files may take any appropriate form and the exact format of these files depends on the particular embodiment. Further, the selected logical pin and specified package pin may be removed from the pin assignment database or noted in the database as being previously assigned.
At block 980, a determination is made as to whether the pin assignment database includes any additional logical pins with direct pin assignment heuristics (e.g., including special-purpose or special-function pins) that have not been previously assigned to package pins. If there are additional unassigned logical pins with direct pin assignment heuristics, the method 900 returns to block 910 and the next direct assignment logical pin is selected and assigned using the method 900, as described above. For instance, in this example, the logical pin DEV_CFG2 would be selected for assignment. In the event that there are not any additional direct assignment logical pins, the method 900 moves to block 990 and package pins are assigned to bank-limited logical pins, such as by using the method illustrated in
In the method 1000, it is assumed that bank properties for the signal pin banks of the FPGA device have been previously assigned. It will be appreciated, however, that the method 1000 may also include assignment of bank properties, such as was described above with respect to the method 900. These operations for assigning bank properties have not been included in the method 1000 for purposes of brevity and clarity.
The method 1000 includes, at block 1005, selecting a logical pin of the device design with bank-limited assignment heuristics. As with the assignment of direct assignment logical pins in the method 900, package pins are assigned to bank-limited logical pins of the device design in the order that the bank-limited logical pins are listed in the pin assignment database for the method 1000. Therefore, at block 1005 the first bank-limited logical pin listed in the pin assignment database that has not previously been assigned to a package pin is selected. Of course, selection of bank-limited logical pins could be made in other fashions.
Applying the method 1000 to the device design of
After selecting the DEV_CLK1 logical pin, the method 1000 moves to block 1010, where a determination is made as to whether there are unassigned pins in the banks specified in the bank-limited assignment heuristics. As discussed above, the assignment heuristics for the DEV_CLK1 pin include a bank-limitation for assignment to only bank 1 of the FPGA device. However, the bank-limitation may specify multiple banks. For instance the bank-limited assignment heuristics could specify signal pin bank 1 and 3, for example. The method 1000 is applicable for both single and multiple bank limitations.
If it is determined, at block 1010, that there are not any available package pins in the signal pin banks specified in the bank-limited assignment heuristics for assignment to the selected logical pin, the method 1000 moves to block 1015 and an indication of failure, such as previously described, is provided to a user. As a result of failure of the method 1000, assignment of package pins to logical pins is halted.
If it is determined that there are package pins available in the specified signal pin banks, the method 1000 moves to block 1020 where one of the specified signal pin banks is selected. In the case of multiple signal pin banks being specified, a selection process may be applied. For instance, the signal pin bank with the greatest number of available package pins may be selected. Of course, any number of other criteria could also be applied to select a signal pin bank at block 1020.
After selection of a signal pin bank at block 1020, the method 1000 moves to block 1025 where an unassigned pin of the selected bank is identified for possible assignment to the selected bank-limited logical pin. Identifying a package pin at block 1025 is done in accordance with the assignment heuristics for the selected logical pin. For example, for the DEV_CLK1 logical pin, the assignment heuristics for the BUS1 signal group 735 (which includes the DEV_CLK1 logical pin) are designated as @1DN, which was discussed above. Therefore, the selection of the package pin at block 1025 should be made in accordance with the DN order designator. As an example, referring to the pinout 200 of
At block 1030, the bank properties and pin properties of the package pin identified at block 1025 are compared to the properties of the selected logical pin. If the bank properties and pin properties are compatible (match), the method 1000 moves to block 1040 where the identified package pin is assigned to the selected logical pin in a similar fashion as was described above with respect to the method 900. The method then moves to block 1045 where a determination is made as to whether there are additional bank-limited logical pins to be assigned to package pins in the pin assignment database. If there are additional bank-limited logical pins to assign, the method 1000 returns to block 1005 and assigns the next bank-limited logical pin in accordance with the method 1000. If there are not additional bank-limited logical pins to assign, the method 1000 moves to block 1050 and package pins are assigned to unrestricted logical pins, such as by using the method illustrated in
In the event that the bank properties and/or pin properties of the identified package pin do not match the properties of the selected logical pin, the method 1000 moves to block 1035 where a determination is made as to whether there are additional unassigned package pins available in the selected signal pin bank. If there are, the method 1000 returns to block 1025 and continues. If there are no unassigned package pins available in the selected bank, the method 1000 returns to block 1010 and continues. If a only single signal pin bank was included in the bank-limitation for the selected logical pin, a determination would then be made at block 1010 that there are no available pins for assignment and the method would proceed to block 1015 and fail. If additional signal pin banks were included in the bank limitation for the selected logical pin, the method 1000 would continue at block 1010, as has discussed above.
In the method 1100, as with the method 1000, it is assumed that bank properties for the signal pin banks of the FPGA device have been previously assigned. It will be appreciated, however, that the method 1100 may also include assignment of bank properties, such as was described above with respect to the method 900. These operations for assigning bank properties have not been included in the method 1100 for purposes of brevity and clarity.
The method 1100 includes, at block 1110, selecting a logical pin of the device design with unrestricted assignment heuristics (an unrestricted logical pin). As with the assignment of direct assignment and bank-limited logical pins in the methods 900 and 1000, in the method 1100, package pins are assigned to unrestricted logical pins of the device design in the order that the bank-limited logical pins are listed in the pin assignment database. Therefore, at block 1110 the first unrestricted logical pin listed in the pin assignment database that has not previously been assigned to a package pin is selected. Of course, selection of unrestricted logical pins could be made in other fashions.
Applying the method 1100 to the device design of
After selecting the MISC_2 logical pin, the method 1100 moves to block 1120, where a determination is made as to whether there are any unassigned package pins on the FPGA. If it is determined, at block 1120, that there are not any available package pins, the method 1100 moves to block 1130 and an indication of failure, such as previously described, is provided to a user. As a result of failure of the method 1100, assignment of package pins to logical pins is halted to afford the user the opportunity to correct the cause of the failure.
If it is determined that there are package pins available, the method 1100 moves to block 1140 where one of the available package pins is selected. In the case of multiple package pins being available, a selection process may be applied. For instance, the first available package pin listed in the pin assignment database may be selected. Of course, any number of other criteria could also be applied to select an available package pin at block 1140.
At block 1150, the bank properties and pin properties of the package pin identified (selected) at block 1140 are compared to the properties of the selected logical pin (e.g., MISC_2). If the bank properties and pin properties are compatible (match), the method 1100 moves to block 1170, where the identified package pin is assigned to the selected logical pin in a similar fashion as was described above with respect to the method 900. The method 1100 then moves to block 1180 where a determination is made as to whether there are additional unrestricted logical pins to be assigned in the pin assignment database. If there are additional unrestricted logical pins to assign, the method 1100 returns to block 1110 and assigns the next unrestricted logical pin in accordance with the method 1100. If there are no additional unrestricted logical pins to be assigned to package pins, the method 1100 moves to block 1190 and output files with pin assignment information and bank properties for the FPGA, such as those output files previously described with respect to
In the event that the bank properties and/or pin properties of the identified package pin do not match the properties of the selected logical pin, the method 1100 moves to block 1160 where a determination is made as to whether there are additional unassigned package pins available. If there are, the method 1100 returns to block 1140 and continues. If there are not any unassigned package pins available, the method 1100 moves to block 1130 and an indication of failure is provided to the user.
While a number of aspects and embodiments have been discussed above, it will be appreciated that various modifications, permutations, additions and/or sub-combinations of these aspects and embodiments are possible. It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions and/or sub-combinations as are within their true spirit and scope.
