1. Field of the Invention
The present invention relates to basic input/output system (BIOS) recovery, and more particularly, to a method and a system for providing an auxiliary BIOS code in an auxiliary BIOS memory utilizing time expiry control.
2. Description of the Prior Art
A basic input/output system (BIOS) is essential for a computer system such as a personal computer (PC). Damage to a BIOS code stored in a BIOS memory, which is a non-volatile memory such as a FLASH memory, typically leads to malfunction of the PC.
A method for solving this problem is providing a main BIOS code and an auxiliary BIOS code, where both of main and auxiliary BIOS codes are stored in the same BIOS memory. According to this method, if a memory mapping error of the main BIOS code occurs, the auxiliary BIOS code will be executed. Another method for solving the same problem is providing a main BIOS code stored in a main BIOS memory and an auxiliary BIOS code stored in an auxiliary BIOS memory, where the main and auxiliary BIOS memories are connected to the same interface and have the same storage volume. For example, if the storage volume of the main BIOS memory is 2M bits, the storage volume of the auxiliary BIOS memory is also 2M bits. According to this method, if there exists a difference between a specific value read from the main BIOS memory and a corresponding value read from the auxiliary BIOS memory, the auxiliary BIOS code will be executed. Both of the methods mentioned above require double the storage volume of BIOS memory resources in contrast to the architecture with single BIOS code.
It is an objective of the claimed invention to provide a method and a system for providing an auxiliary basic input/output system (BIOS) code in an auxiliary BIOS memory utilizing time expiry control.
A method for providing an auxiliary BIOS code in a computer system is disclosed, where the computer system includes a central processing unit (CPU) for executing an operation system (OS) program. According to one embodiment of the claimed invention, the method comprises: providing a main BIOS memory for storing a main BIOS code to be executed in a main mode; providing an auxiliary BIOS memory for storing the auxiliary BIOS code to be executed in an auxiliary mode; and in the main mode, if a specific time interval expires and the OS program is not successfully executed, disabling the main BIOS code, enabling the auxiliary BIOS code, and resetting the computer system to switch from the main mode to the auxiliary mode.
A computer system is further disclosed. According to one embodiment of the claimed invention, the computer system comprises: a CPU for executing an OS program; a main BIOS memory coupled to the CPU for storing a main BIOS code to be executed in a main mode; a control circuit coupled to the CPU for time expiry control; and an auxiliary BIOS memory coupled to the control circuit for storing an auxiliary BIOS code to be executed in an auxiliary mode. In the main mode, if a specific time interval expires and the OS program is not successfully executed, the control circuit disables the main BIOS code, enables the auxiliary BIOS code, and resets the computer system to switch from the main mode to the auxiliary mode.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Please refer to
As provided in this embodiment, the computer system 100 further comprises a main basic input/output system (BIOS) memory 130, a control circuit 210, and an auxiliary BIOS memory 230, where the main BIOS memory 130 and the control circuit 210 are coupled to the CPU 110 through a low pin count (LPC) interface 120, and the auxiliary BIOS memory 230 is coupled to the control circuit 210 through a serial peripheral interface (SPI) 220. According to this embodiment, the main BIOS memory 130 and the auxiliary BIOS memory 230 are non-volatile memories, and more particularly, FLASH memories. The main BIOS memory 130 is utilized for storing a main BIOS code to be executed in a main mode, which is a normal mode for normal operations of the computer system 100 in this embodiment. In addition, the auxiliary BIOS memory 230 is utilized for storing an auxiliary BIOS code to be executed in an auxiliary mode. In this embodiment, if the main BIOS code is considered damaged, the computer system 100 switches from the main mode to the auxiliary mode.
As shown in
In this embodiment, the control circuit 210 further comprises a storage unit 212, where the control circuit 210 utilizes the storage unit 212 to store a parameter that typically represents an operation mode such as the main mode or the auxiliary mode mentioned above. Please refer to
In addition, the control circuit 210 is also utilized for time expiry control. As shown in
In Step 910, if the parameter P is equal to 11, Step 912 is then executed. In Step 912, the control circuit 210 enables the timing unit 214, i.e., the counter in this embodiment. An initial value of the counter value C is set to be 0. A loop comprising Steps 914, 916, and 918 is executed repeatedly until the parameter P is changed by the OS program or an application program executed in the environment provided by the OS program. Please note that if the OS program is successfully executed, the main BIOS code is not considered damaged. After the OS program or the application program mentioned above changes the parameter P to be 10, the loop is broken by executing Step 924, so the control circuit 210 clears the counter, i.e., the counter value C is changed to be 0.
On the other hand, every time when Step 916 is executed, the counter value C is changed with an increment of one. As time goes by, the counter value C approaches the predetermined threshold value Cp gradually. In Step 918, if the counter value C is less than or equal to the predetermined threshold value Cp, Step 914 is then executed. However, in Step 918, if the counter value C is greater than the predetermined threshold value Cp, i.e., the specific time interval expires, Step 920 is executed and the parameter P is set to be 01 by the control circuit 210. Please note, the expiry of the specific time interval represents that the OS program is not successfully executed, so the main BIOS codes is considered damaged. Therefore, in Step 922, the control circuit 210 disables the main BIOS code, enables the auxiliary BIOS code, and resets the computer system 100 by sending out a reset signal RST (not shown) through the LPC interface 120 to switch from the main mode to the auxiliary mode.
In the auxiliary mode according to this embodiment, Steps 910, 930, and 950 are executed since in the main mode, the control circuit 210 set the parameter P to be 01 (in Step 920). After Step 950, Step 952 is entered and the control circuit 210 disables the main BIOS code and enables the auxiliary BIOS code. As a result, the auxiliary BIOS code is executed as a backup of the main BIOS code. It is unnecessary that the auxiliary BIOS memory 230 has the same storage volume as that of the main BIOS memory 130 since the auxiliary BIOS memory 230 is coupled to the CPU 110 through the control circuit 210 rather than direct coupling through the LPC interface 120. The storage volume of the auxiliary BIOS memory 230 and costs thereof can be reduced correspondingly in contrast to the prior art.
It is noted that by setting the value of the parameter P to be 00, both of the main and auxiliary BIOS codes can be disabled as needed. In this situation, after the checking operations of the parameter P in Steps 910, 930, 950, and 970 are executed, Step 972 is then entered, so both of the main and auxiliary BIOS codes are disabled.
A variation of the first embodiment is similar to the first embodiment but the computer system 100 according to this variation further has BIOS auto-recovery functionality in the auxiliary mode. In this variation, Step 952 shown in
A second embodiment of the present invention is similar to the first embodiment but the LPC interface 120 is replaced with a firmware hub (FWH) interface in the second embodiment.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.