Method and system for quantum circuit synthesis using quaternion algebra

Abstract

Quantum circuits are synthesized based on a projective gate set derived from a set of single-qubit gates, typically a basis set such as the Clifford+T gates or the V-gates. An initial projective gate set is used to determine at least one characteristic of a quaternion algebra, and the quaternion algebra is used to define a new projective gate set. Exactly synthesizable unitaries are identified, and a circuit approximating a target unitary is defined in the single-qubit gate set by mapping from the new projective gate set.

Description

FIELD

The disclosure pertains to quantum circuit synthesis.

BACKGROUND

Quantum circuit synthesis typically involves complex number-theoretic computations. A set of quantum gates is selected to serve as a basis, and various basis-specific approaches are used to synthesize a target unitary in the selected basis. Some methods for bases such as the Clifford+T basis, the V-basis, and the Fibonacci anyon basis are available, but these methods are limited to a single basis. In addition, for some bases, it is unclear how to synthesize a target unitary, or if such a synthesis is possible. Synthesized circuits are often based on approximate unitaries that correspond to the target unitary within a specified precision, so that the target unitary is synthesized based on exactly synthesizable unitaries. Unfortunately, conventional synthesis methods are limited in the available selection of bases, and synthesis methods applicable to arbitrary bases are needed.

SUMMARY

Quantum circuit synthesis methods based on a predetermined single-qubit gate set include determining an initial projective gate set (PGS) associated with the single-qubit gate set. A set of elements of a quaternion algebra related to the PGS is determined, and in some cases, the associated quaternion algebra and elements of the quaternion algebra are established. Based on a maximal order and a set of ideals associated with the quaternion algebra, a final projective gate set (PGS*) is determined. A target unitary is mapped to a set of unitaries that are exactly representable based on PGS*, and based on a PGS/PGS* mapping, the target unitary is synthesized in the single-qubit gate set. Various single-qubit gate sets such as the Clifford+T gates, the V-gates, and the Fibonacci gates can be used. In some cases, target unitaries are approximated using exactly synthesizable unitaries defined by the final projective gate set that are then mapped into the single-qubit gate set.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates method for quantum circuit synthesis using a projective gate set (PGS) corresponding to a single-qubit gate set.

FIG. 2 illustrates a representative method of quantum circuit synthesis based on a quaternion algebra corresponding to a PGS.

FIG. 3 illustrates a representative method of determining a set of quaternions based on a maximal order and an associated set of ideals.

FIG. 4 illustrates a representative method of determining a set of generators U based on a quaternion algebra corresponding to a PGS.

FIGS. 5-6 illustrate representative methods of exact synthesis using projective gate sets and associated quaternion characteristics.

FIG. 7 illustrates a representative classical computing environment for implementation of the disclosed methods for determination of projective gate sets, ideals, maximal orders, special unitaries, quaternion algebras, and other related methods, including exact and approximate circuit synthesis.

FIG. 8 illustrates a representative quantum and classical computing environment for implementation of the disclosed methods, including a compiler for establishing quantum circuits based on series of gates determined using projective gate sets, ideals, maximal orders, special unitaries, and quaternion algebras, and a quantum computer that implements circuits synthesized by the compiler.

DETAILED DESCRIPTION

As used in this application and in the claims, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “comprises.” Further, the term “coupled” does not exclude the presence of intermediate elements between the coupled items.

The systems, apparatus, and methods described herein should not be construed as limiting in any way. Instead, the present disclosure is directed toward all novel and non-obvious features and aspects of the various disclosed embodiments, alone and in various combinations and sub-combinations with one another. The disclosed systems, methods, and apparatus are not limited to any specific aspect or feature or combinations thereof, nor do the disclosed systems, methods, and apparatus require that any one or more specific advantages be present or problems be solved. Any theories of operation are to facilitate explanation, but the disclosed systems, methods, and apparatus are not limited to such theories of operation.

Although the operations of some of the disclosed methods are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed systems, methods, and apparatus can be used in conjunction with other systems, methods, and apparatus. Additionally, the description sometimes uses terms like “produce” and “provide” to describe the disclosed methods. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

In some examples, values, procedures, or apparatus are referred to as “lowest”, “best”, “minimum,” or the like. It will be appreciated that such descriptions are intended to indicate that a selection among many used functional alternatives can be made, and such selections need not be better, smaller, or otherwise preferable to other selections.

As used herein, ζ_n is an n^th root of unity. Sets are generally denoted in boldface text, without italics, and in some cases, as so-called blackboard bold. For example, the set of integers can be noted as or Z. The Pauli gates are represented as

$X=\left(\begin{array}{cc}0& 1\\ 1& 0\end{array}\right),Y=\left(\begin{array}{cc}0& -i\\ i& 0\end{array}\right),Z=\left(\begin{array}{cc}1& 0\\ 0& -1\end{array}\right)$ and the identity gate is I. In the description of circuit synthesis, gate and gate set descriptions or specifications are sometimes referred to as gates or gate sets for convenience.

Overview

Quantum circuit synthesis requires representation of an arbitrary unitary in a basis set of available gates. For some unitaries, exact syntheses may be unavailable, and approximate syntheses are used. In addition, some quantum circuits are defined as repeat-until-success (RUS) circuits in which a selected computation result is obtained only in some instances. The disclosed methods and apparatus pertain to factoring unitaries using a selected basis (and possibly as RUS designs) and embedding them into a quaternion algebra A. A unitary is rescaled such that a corresponding quaternion q defines an integral and primitive right ideal I of maximal order M of A. The right ideal I is factored into a product of maximal primitive ideals, and products of maximal primitive ideals are combined into principal ideals. The quaternion q can be represented as a product of generators of principal ideals q_k and units u_k as u₀q₁u₁ . . . q_m-1u_m-1q_mu_m. Each u_k,q_k is mapped to a unitary matrix or product of such matrices. If A is definite, the generators of the unit group of M are computed. If A is indefinite, generators can be obtained if A is split at a unique real place so that the unit group is a Fuchsian group. Typically, if the generators of the principal ideals q_k are known to belong to a finite set G, the factorization of unitaries can be found.

The disclosed methods and apparatus are suitable for a variety of gate sets, including gate sets corresponding to SU (2)_k, the V-basis, unitaries over rings such as [½,ζ₈,1/p₁,1/p₂] or [½,ζ₁₆,1/p₁,1/p₂], or gate sets such as described in Forest et al., “Exact synthesis of single-qubit unitaries over Clifford-cyclotomic gate sets,” arXiv:1501.04944 (January 2015). Note that the Clifford group coincides with matrices over [½,ζ₄], ignoring a global phase. The disclosed methods typically involve finding a special description of exactly synthesizable matrices over a single-qubit quantum gate set, or a larger single-qubit quantum gate set that includes an original single-qubit quantum gate set and admits the special description of exactly synthesizable matrices. A correspondence between a projective gate set (PGS) and a single-qubit quantum gate set (GS) is determined. Several heuristics are provided that allow determination of an equivalent projective gate set suitable for a given quantum gate set. These can be based on CM fields that cover a wide class of number fields including cyclotomic number fields. In particular, heuristics for gate sets related to su(2) level k anyons and unitary matrices over the ring [1/p,ζ_n] for a rational prime p are provided. The correspondences take into account the irrelevance of global phase of unitary matrices in quantum computing applications. Number fields used for particular gate sets can be simplified by dealing with normalization factors in a particular way.

Representative methods determine correspondences between projective gate sets and elements of quaternion algebra. Some particular examples show detailed correspondences of selected quaternion algebras and single-qubit gates. Maximal orders of quaternion algebras related to projective gate sets are determined using several approaches, and sets of ideals corresponding to projective gate sets are established. A set of ideals describing a selected gate set can be found algorithmically given a maximal order and mapping from the gate set to a quaternion algebra. Upon finding a projective gate set defined by a maximal order and a set of ideals, a search method is applied to evaluate whether a new gate set is equivalent to the original gate set or only includes the original gate set as a subset. Exact synthesis methods define an exact decomposition of any unitary matrix using the associated maximal order, ideal, and quaternion algebra, typically based on syntheses over a projective gate set. Given a maximal order, a set of ideals, and correspondences between a single-qubit gate and a projective gate set, and an explicit description of the correspondence based on quaternion algebra and associated gates, a compact description of unitary matrices that can be decomposed using the projective gate set is obtained.

Quaternion Algebra

Quaternion algebras are written as

$B=\left(\frac{a,b}{F}\right)$ and any element of B can be written as q=x+yα+zβ+wαβ,x,y,z,w∈F. Conjugation is defined as q*=x−yα−zβ−wαβ. A reduced trace function trd(q) is defined as trd(q)=q+q*=2×. A reduced norm function nrd(q) is defined as qq*=x²−αy²−βz²+αβw². Elements of the form xI+yiX+ziZ+wiY,x,y,z,w∈F, wherein I is the identity and X, Y, Z are the Pauli matrices, form a quaternion algebra

$B=\left(\frac{-1,-1}{F}\right).$

All single qubit unitaries over the Clifford+T gate set are elements of

$B=\left(\frac{-1,-1}{\mathbb{Q}\left({\zeta }_8+{\zeta }_8^{-1}\right)}\right).$

Quaternion algebras and associated operations can be represented with computer-implementable instructions in various ways, and quaternions can be stored as 4-element row or column matrices, or otherwise stored and processed. The methods disclosed herein can be implemented with these or other representations.

Elements of the group SU(2) over [½,ζ_n] can be mapped to a quaternion algebra as follows. Any element of [ζ_n] can be written as α+ζ_nb for a, b from (ζ_n)∩. Thus, any element of SU(2) over [½,ζ_n] can be written as:

$\left(\begin{array}{cc}\left(a+b{\zeta }_n\right)& -{\left(c+d{\zeta }_n\right)}^{*}\\ \left(c+d{\zeta }_n\right)& {\left(a+b{\zeta }_n\right)}^{*}\end{array}\right)=\frac{1}{2^k}\left(aI+b\left(\begin{array}{cc}{\zeta }_n& 0\\ 0& {\zeta }_n^{*}\end{array}\right)-c\mathrm{IY}+d\left(\begin{array}{cc}0& {\zeta }_n\\ {\zeta }_n^{*}& 0\end{array}\right)\right).$

The identity matrix I can be mapped to 1 and iY can be mapped to element j in the quaternion algebra. Mappings for

$M_1=\left(\begin{array}{cc}{\zeta }_n& 0\\ 0& {\zeta }_n^{*}\end{array}\right),M_2=\left(\begin{array}{cc}0& {\zeta }_n\\ {\zeta }_n^{*}& 0\end{array}\right)$ are needed. Two cases are described below in which quaternion q corresponds to unitary U, det(U)=nrd(q).

Case 1: 4|n

In this case, √{square root over (−1)} is in (ζ_n) and any x in (ζ_n) has real and imaginary parts in (ζ_n)∩ Therefore, using the correspondence 1↔I,i↔Z,j↔Y,k↔iX between quaternions and Pauli matrices, the elements of SU(2) over [½,ζ_n] can be mapped to elements of quaternion algebra

$\left(\frac{-1,-1}{\mathbb{Q}\left({\zeta }_b\right)\bigcap ℝ}\right).$ It can be shown thatM₁=Re(ζ_n)I+Im(ζ_n)iZ,M₂=iYRe(ζ_n)+iXIm(ζ_n).Therefore, M₁↔Re (ζ_n)+i Im(ζ_n),M₂ ↔j Re(ζ_n)+k Im(ζ_n).

Case 2: 4|n

In this case, Im(ζ_n)=sin(2π/n) is not in (ζ_n) and the mapping 1↔I, i↔2iZ sin(2π/n), j↔iY,k↔2iX sin(2π/n) can be used. It can be shown thatM₁↔Re(ζ_n)+i/2,M₂↔jRe(ζ_n)+k/2

Note that i²=−4 sin² (2π/k)=4 cos²(2π/k)−4=(ζ_n+ζ_n⁻¹)²=ζ_n²+ζ_n⁻²−2. Therefore, the quaternion algebra

$\left(\frac{{\left(2\cos \left(2\pi k/n\right)\right)}^2-4,-1}{\mathbb{Q}\left({\zeta }_n\right)\bigcap ℝ}\right)$ is used.

Other bases can use these or different quaternion algebras. Fibonacci anyons can be written in the form

$\left(\begin{array}{cc}a+b{\zeta }_{10}& -{\left(\left(c+d{\zeta }_{10}\right)\sqrt{\tau }\right)}^{*}\\ \left(c+d{\zeta }_{10}\right)\sqrt{\tau }& {\left(a+b{\zeta }_{10}\right)}^{*}\end{array}\right),\tau =\frac{\sqrt{5-1}}{2},$ a,b,c,d∈ This can be rewritten as

$\mathrm{aI}+b\left(\begin{array}{cc}{\zeta }_{10}& -0^{*}\\ 0& {\zeta }_{10}^{*}\end{array}\right)-c\left(\mathrm{iY}\sqrt{\tau }\right)+d\sqrt{\tau }\left(\begin{array}{cc}0& {\zeta }_{10}^{*}\\ {\zeta }_{10}& 0^{*}\end{array}\right).$ Fibonacci anyons can use the mapping 1↔I,i↔2iZ sin(2πk/10), j↔iY√{square root over (τ)}, k↔2iX sin (2πk/10)√{square root over (τ)} which can be associated with the quaternion algebra

$\left(\frac{{\left(2\cos \left(2\pi /10\right)\right)}^2-4,-\tau }{\mathbb{Q}\left({\zeta }_{10}\right)\bigcap ℝ}\right).$ The Fibonacci matrix representation then can be expressed as a+b((i+s)/2)−cj+d((js+k)/2),s=Re(ζ₁₀). Quaternions 1,(s+j)/2,j,(S*j+k/2) form a basis of maximal order.

In general, syntheses using su(2)_k anyons can be based on quaternion algebras of the form

$\left(\frac{{\left(2\cos \left(2\pi /n\right)\right)}^2-4,-3_q}{{\mathbb{Q}}^{+}\left({\zeta }_n\right)}\right)$ for n=k+2, wherein

$3_q=\frac{q^{3/2}-q^{-3/2}}{q^{1/2}-q^{1/2}},$ q=ζ_n.

Quaternion-Based Circuit Synthesis

Referring to FIG. 1, a representative quantum circuit synthesis method 100 based on a projective gate set obtained using a quaternion mapping includes receiving an input target unitary and precision at 102. Typically, a selected single-qubit gate set is previously provided, but can be input as well. At 104, the target unitary is approximated, if necessary, based on unitaries exactly synthesizable over a remapped projective gate set PGS*. These unitaries can be previously calculated and stored or computed as needed at 114. An exact synthesis of the approximate target unitary is computed at 106. At 108, correspondence between a PGS and the PGS* is used to translate the circuit from the PGS* to the PGS associated with a single-qubit gate set (GS) and the remapped projective gate set PGS* is determined. In some cases, the original PGS and the remapped PGS* are substantially the same. At 110, a circuit is obtained based on the PGS/PGS* correspondence, so that a circuit is available as a sequence of gates from the gate set GS. The circuit is typically used to defined a series of gates in a quantum computer.

Projective Gate Set Determination

Referring to FIG. 2, a method of quantum circuit synthesis 200 using one or more projective gate sets includes receiving a single-qubit gate set (GS) at 202 that can be any arbitrary gate set. At 204, one or more heuristic procedures are applied to GS such as representative procedures 208 that can be performed based on computer-executable instructions stored in one or more computer memory devices. At 206, a projective gate set (PGS) is obtained, typically represented at 207 in a form M[F, b] (discussed in detail below), and at 210, a quaternion algebra corresponding to the PGS is determined. At 212, a maximal order and a set of ideals associated with the quaternion algebra are determined and a new projective gate set PGS* (sometimes referred to as a remapped PGS herein) is computed at 214. Based on PGS*, exactly synthesizable unitaries are determined at 215. At 216, PGS and PGS* are compared. If PGS* is equivalent to PGS, then a mapping between PGS and PGS* is obtained at 217. Otherwise, different heuristics are tried or the initial gate set is extended at 218. A quantum circuit synthesis for a selected target unitary based on the PGS* can be output at 230, or a definition of the quaternion algebra associated with the GS and/or a PGS/PGS* mapping can be stored for future circuit synthesis. Mathematical details of the method 200 are further described below.

Typically, a single-qubit gate set V₁, . . . , V_n is provided that may or may not be known to be complete. The gates V_i are defined over a particular number field. The gate set V₁, . . . , V_n can be transformed using various approaches so as to form a projective gate set (PGS) having matrices U₁, . . . , U_n in the form:

$M\left[F,b\right]=\left(\begin{array}{cc}x& -y^{*}\sqrt{b}\\ y\sqrt{b}& x^{*}\end{array}\right),$ wherein F is a minimal CM-field over which diagonal entries for each of the gates V₁, . . . , V_n can be found. Several heuristics can be used. For example, each of the gates V_i can be multiplied by a scalar so that each can be defined over a simpler number field. One convenient example of such a CM-field is a cyclotomic field that is generated by the primitive n^th root of unity. If a square root of an element of the real subfield F⁺ of F corresponds to an off-diagonal entry, this value is selected for b. If there are several possible values of b, a value corresponding to a square free algebraic integer is selected. If a gate V_j has a determinant that is one, rescaling can be done and in many cases such rescaling is sufficient to make the rescaled value an element of M[F,b]. If a gate U₁, . . . , , U_n has a determinant that is not one and is diagonal with a root of unity on the diagonal, then find U₁, . . . , U_n such that:

$V_j\rho V_j^{*}=\frac{U_j\rho U_j^{*}}{\det U_j},$ wherein ρ is an arbitrary 2 by 2 Hermitian matrix. For example, for

$V_j=\left(\begin{array}{cc}1& 0\\ 0& {\zeta }_n\end{array}\right),{\zeta }_n=e^{2\pi i/n},$ then

$U_j=\left(\begin{array}{cc}1+{\zeta }_n& 0\\ 0& 1+{\zeta }_n^{*}\end{array}\right).$ If none of these approaches are effective, V_j can be expressed a product of matrices that can be transformed using the above approaches.

Some representative mappings of a set GS to a PGS are shown in Table 1 below.

TABLE 1
Single-qubit gate sets mapped to projective gate sets
GS	F, b	Gates	PGS
V-basis	F = Q[i], b = 1	$V_z=\frac{1}{\sqrt{5}}\left(\begin{array}{cc}1+2i& 0\\ 0& 1-2i\end{array}\right)$	$U_z=\left(\begin{array}{cc}1+2i& 0\\ 0& 1-2i\end{array}\right)$
Clifford+T	F = Q[ζ8], b = 1	$V_j=\left(\begin{array}{cc}1& 0\\ 0& {\zeta }_n\end{array}\right)$	$U_j=\left(\begin{array}{cc}1+{\zeta }_8& 0\\ 0& 1+{\zeta }_8^{*}\end{array}\right)$
Fibonacci	F = Q[ζ10], b = τ	$\hspace{1em}\begin{array}{c}{V}_j=\left(\begin{array}{cc}\tau & -\sqrt{\tau }\\ \sqrt{\tau }& \tau \end{array}\right),\\ \tau =\frac{\sqrt{5}-1}{2}\end{array}$	$U_j=\left(\begin{array}{cc}\tau & -\sqrt{\tau }\\ \sqrt{\tau }& \tau \end{array}\right)$
SU(2) level k anyons	$\hspace{1em}\begin{array}{c}F=Q\left[q\right],\\ b=\frac{-\left(q^{3/2}-q^{-3/2}\right)}{\left(q^{1/2}-q^{-1/2}\right)}\\ q={\zeta }_{k+2}\end{array}$
Matrices over	F = Q[ζn], b = 1
Z[ζn, 1√p1, . . . 1√pm],
pk a rational prime.

After determining a PGS based on the initial GS, a set of elements of a quaternion algebra is obtained that correspond to the PGS. A value D is found that is a totally positive algebraic integer in F⁺ such that F=F⁺[√{square root over (−D)}], and a quaternion algebra

$A=\left(\frac{-D,-b}{F^{+}}\right)$ having a basis 1, i, j, k is selected for use. For example, if F=Q[ζ_c], then F⁺=Q[ζ_n+ζ_n⁻¹]. If 4|n, then F=F⁺[√{square root over (−1)}] and D=−1. Otherwise, D=(ζ_n+ζ_n⁻¹)²−4. A mapping

$\mu :M\left[F,b\right]\to \left(\frac{-D,-b}{F^{+}}\right)$ is then found, comprising μ(I)=1,μ(√{square root over (−D)}Z)=i,μ(√{square root over (−b)}X)=j,q_k=μ(U_k), wherein X, Z are Pauli matrices. In other examples, different Pauli matrices or combinations of Pauli matrices can be used.

With the mapping μ, an order O is then constructed that contains all q_k, and a maximal order containing O is constructed. Alternatively, a maximal finite subgroup of a group generated by a set of some q_k, is found. An order O can then be constructed based on generators of the group. In another alternative, if quaternion basis elements i, j, k can be expressed using q_k, then the order Z_F⊕Z_Fi⊕Z_Fj⊕Z_Fk is used, and an associated maximal order is found. The maximal order is then checked to determine that it contains all q_k. If not, the q_k, can be rescaled. In yet another example, if the quaternion algebra is described as

$\left(\frac{-1,-1}{F^{+}}\right)$ such that 2 is equal to ζ² up to a unit of F⁺, wherein ζ is an algebraic integer in F⁺ then the maximal order

$Z_F\oplus \frac{\zeta Z_F}{2}\left(i+1\right)\oplus \frac{\zeta Z_F}{2}\left(j+1\right)\oplus \frac{Z_F}{2}\left(1+i+j+k\right)$ may be suitable.

With the maximal order determined, a set of ideals related to the set of elements of the quaternion algebra A is found. As noted above, the maximal order contains all of the q_k The set of ideals is given by S={p|q_kq_k*Z_F⊂p}, wherein p is a prime ideal in Z_F, and can be built by prime factorization of ideals q_kq_k*Z_F. Sets of ideals for representative bases are summarized in Table 2.

TABLE 2
Ideals for representative bases
Basis	F, b, F+	S
V basis	F = Q[i], b = 1, F+ = Q	S =   5
Clifford + T basis	F = Q[ζ8], b = 1, F+ =   [{square root over (2])}	S =   |1 + ζ8|2   [{square root over (2)}]
Fibonacci basis	F = Q[ζ10], b = τ, F+ =   [τ]	S =    |τ|

Non-unit generators Q corresponding to the maximal order M and the set of ideals S can be found along with unit generators U corresponding to M. The unit generators and the maximal order M are then mapped to a new PGS referred to as PGS*. In some cases, this procedure is unsuccessful, either due to computational difficulties or a deficiency in the original gate set. In other cases, PGS* does not correspond precisely to the original gate set but includes some added operations that extend the original gate set. Even if a gate set is known to be universal, an efficient procedure for using the gate set to represent an arbitrary unitary is not necessarily available.

Referring to FIG. 3, a method 300 includes receiving the maximal order M and the set of ideals S at 302. At 304, if the maximal order M has class number 1, then the set of unit generators Q is determined by enumerating right principal ideals with norm from S and finding their generators at 306. If the maximal order M does not have class number 1, then at 310, a determination is made as to whether an ideal principality graph can be made. If not, at 312, additional choices in earlier steps can be tried. Otherwise, the ideal principality graph can be made, and Q is defined as a set of quaternions corresponding to leaves of the ideal principality graph at 314. At 316, Q is returned, if available.

Referring to FIG. 4, a method 400 of determining unit generators U associated with M includes obtaining a specification of a quaternion algebra at 402. At 404, it is determined if the quaternion algebra is totally definite. If so, a unit group of the quaternion algebra is computed and generators U (finite) are determined at 408. If not, at 410, it is determined if the quaternion algebra is split at exactly one place at infinity. If not, alternative procedures can be evaluated at 412. If so, a unit group of the quaternion algebra is computed and generators U are determined at 414. If available, the unit generators U are returned at 416.

With reference to FIG. 5, a method 500 of exact synthesis includes receiving an element q of the maximal order M having a norm that factors into prime ideals from the set of ideals Sat 502. At 504, an exact synthesis procedure is performed (shown below in Table 3), and at 506 a list of elements of U, Q are output such that q=q₁ . . . q_m.

TABLE 3
Pseudo-code for exact synthesis using M and Q
L ← empty list
while q is not a unit of M
Find g from Q such that:
1) g−1 q is in M
2) ideal nrd(g−1 q)   F+ has less prime factors
then ideal nrd(q)   F+
Append g to the end of L
q   g−1 q
end while
Decompose q in terms of generators of unit group of M **
and get list u1,...,us such that q = u1..us
Append u1,...,us to the end of list L

A method 600 for obtaining a description of exact unitaries is illustrated schematically in FIG. 6. A maximal order M, a set of ideals, and a quaternion mapping μ described above are received at 602, and M is represented as M=p₁q₁⊕p₂q₂⊕p₃q₃⊕p₄q₄. At 606, matrices M are output from the set defined byM=p₁μ⁻¹(q₁)⊕p₂μ⁻¹(q₂)⊕p₃μ⁻¹(q₃)⊕p₄μ⁻¹(q₄)

As discussed above, for G chosen to be a subset of _S (all elements s of such that nrd(s) factors into elements of S), G⊂ can be found. However, it can be further shown that any element of _S can be written as a product q₁ . . . q_nuα wherein quaternions q₁, . . . , q_n are from a finite set ext_S() and u is an element of a unit group of maximal order , and α is an element of F. If one of the following conditions holds u can be written as a product of finite number elements of gen_u(): (1) F is a totally real number field, and

$\left(\frac{a,b}{F}\right)$ is a totally definite quaternion algebra, or (2) F is a totally real number field, and

$\left(\frac{a,b}{F}\right)$ is split in exactly one real place. It will be appreciated that several methods for determining ext_S() gen_u(), and q₁ . . . q_nuα are known and can be selected for such determinations.

Thus, a finite set of quaternions G can be found such that any element of _S can be written as q₁ . . . q_n for q_k elements of G. A method for such factorization of elements of _S into a finite set of quaternions is illustrated in the pseudo-code of Table 4. Additional procedures used include procedures for finding generators of a maximal order, testing membership in a maximal order, computing the discriminant of a quaternion algebra, returning a sequence length (procedure LENGTH), finding a number of ideals in a set S that does not divide the discriminant (procedure TOT-IDEALS), determining valuation vS(x)=Σ_p∈Sv_p(x_F), wherein v_p is a p-adic valuation of the ideal xF of number field F, procedure IS-TSI-CLASS-GROUP-TRIVIAL returns true if the two sided ideal class group of

$\left(\frac{a,b}{F}\right)$ is trivial, procedures for computing the generators of prime ideals with norm that divides discriminant of

$\left(\frac{a,b}{F}\right),$ procedure IDEAL-GENERATOR which determines a generator of right principal ideal, procedures for conjugation of maximal orders by an element, multiplication of ideals and maximal orders, ideals inversion, and conjugation of ideals by quaternion, and procedure UNIT-DECOMPOSE which decomposes a unit of maximal order into a product of generators of the unit group of when

$\left(\frac{a,b}{F}\right)$ is either totally definite or

$\left(\frac{a,b}{F}\right)$ splits in exactly one place. In addition, MAX-ORDER, PARENT-ID, IDEAL-ID are defined asMAXORDER(s₁,s₂,s₃,q)=(s₃,q),PARENT-ID(s₁,s₂,s₃,q)=s₂,IDEAL-ID(s₁,S₂,S₃,=s₁,respectively, wherein S₁, S₂, S₃ are integers, and q is from

$\left(\frac{a,b}{F}\right).$

Pseudo-code for some of these procedures is listed in Tables 5-8 and others can be implemented with conventional computational algebra systems.

TABLE 4
Factorization of elements of    S into a finite set of quaternions
Input: Maximal order     of (a,bF),
set S of prime ideals of    F, an element q of
such that nrd(q)    F factors into ideals from
S (assumes that two side ideal class group of (a,bF)
is trivial)
1: procedure EXACT-SYNTHESIS-2(   , S, q)
2:  (C, q) ← EXACT-SYNTHESIS-STAGE-1(   , S, q)
3:  Add TWO-SIDED-DECOMPOSE(q,    , S) to the end of C
4:  return C
5: end procedure
Output: Outputs q1 . . . qmu1 . . . un = q where qi are from extS(   )
and uj are generators of the unit group of

TABLE 5
Additional procedures for the method shown in Table 4.
Input: Maximal order     of (a,bF),
set S of prime ideals of    F
1: procedure FIND-S-GENERATORS(   , S)
2:  M     SPANNING-TREE-SIZE(   , S)
3:  if M = ∞ then
4:   return ∅
5:  else
6:   Adj     MAX-ORDERS-ADJ(   , S)
7:   (s0, q0)     CONJ-CLASS-DESCR(   )
8:   V     sequence of levels of TS(   ) of size M, each level
is empty
9:   V0     (0, 0, s0, q0)     Sequence of length one
10:   V1     S-NEIGHBOURS(Adj, 1, V0[1])
11:   for all k = 2, . . . , M do
12:     Vk     NEW-LEVEL(Adj, s0, Vk−1, Vk−2)
13:   end for
14:   return {q : (s0, q) = MAX-ORDER(v), v ϵ Vk, k = 1, . . . , M}
15:  end if
16: end procedure
Output: Set of canonical generators genS(   ) if GS(   ) finite
and ∅ otherwise
Input: Maximal orders adjacency description Adj, s0 - conjugacy class
of    , vertices description of the current layer Vc
of the previous layer Vpr.
17: procedure NEW-LEVEL(Adj, s0, Vc, Vpr)
18:  Vnew     empty sequence of vertex descriptions
19:  for all m = 1, . . . , LENGTH(Vc) do
20:   N     S-NEIGHBOURS(Adj, m, Vc[m])
21:   O     MAX-ORDER(Vpr[PARENT-ID(Vc[m])])
22:   for all v′ ϵ N do
23:     if IDEAL-ID(v) = IDEAL-ID(v′) then
24:      if IS-EQUAL(O, MAX-ORDER(v′)) then
25:       Append v′ to Vnew
26:      end if
27:     else
28:      Append v′ to Vnew
29:     end if
30:    end for
31:   end for
32:   return Vnew
33: end procedure

TABLE 6
Additional procedures for the method shown in Table 4.
Input: Maximal orders adjacency description Adj,
index of the vertex description in its level m,
vertex description v
1: procedure S-NEIGHBOURS(Adj,m,v)
2:  (s,q) ← MAX-ORDER(v)
3:  N ← empty sequence of vertex descriptions
4:  for all k = IDEAL-ID(v),...,TOTAL-IDEALS do
5:   Append v ∈ {(k,m,s′,qq′):(s′,q′) ∈ Adjs,k} to N
6:  end for
7:  return N
8: end procedure
Output: Vertex descriptions of S-veighbours of v
Input: si,qi defining a maximal order qi   siqi−1
si is the maximal order with index si
in the sequence output by CONJ-CLASSES-LIST
9: procedure IS-EQUAL((s1,q1),(s2,q2))
10:  if s1 = s2 then
11:       1,...,   1 ← CONJ-CLASSES-LIST
12:   Let g1,...,gm be generators of   si
13:   q ← q1−1q2
14:   return TRUE if all qgkq−1 are from   s1, FALSE otherwise
15:  else
16:   return FALSE
17:  end if
18: end procedure
Output: TRUE if maximal orders are equal and FALSE otherwise

TABLE 7
Additional procedures for the method shown in Table 4.
Input: Maximal order     of (a,bF),
set S of prime ideals of    F
procedure SPANNING-TREE-SIZE(   , S)
Adj1,1, . . . , Adjm,l     MAX-ORDERS-ADJ(S)
(s0, q0)     CONJ-CLASS-DESCR(   )
E1     {(s0, j, i) : (j, q) ϵ Adjs0,i, i = 1, . . . , l, j ≠ s0}
k     1
while Ek is not empty do
for all (s, j, i) ϵ Ek do
if #{(s, q) : (s, q) ϵ Adjj,i, s ≠ s0} > 0 then
Ek+1     Ek+1 ∪ {(j, s, i)}
end if
for all i′ = i + 1, . . . , l do
Ek+1     Ek+1 ∪ {(j, s′, i′) : (s′, q) ϵ Adjj,i′, s′ ≠ s0}
end for
end for
if Ek+1 is equal to one of E1, . . . , Ek then
return ∞
else
k     k + 1
end if
end while
return k
end procedure
Output: Depth of the TS(   ) if its finite and ∞ otherwise

TABLE 8
Additional procedures for the method shown in Table 4.
Input: Maximal order     of (a,bF),
set S of prime ideals of    F, an element q of
such that nrd(q)    F factors into ideals from S
(assumes that two side ideal class
group of (a,bF)
is trivial)
1: procedure EXACT-SYNTHESIS-1(   , S, q)
2:  genS(   )     FIND-S-GENERATORS(   , S)    Precomputed
3:  G     {PRIMITIVE-REPR(   , x) : x ϵ genS(   )}     Precomputed
4:  Let S0 = {p1, . . . , pt} be all elements of S
that does not divide the discriminant of (a,bF)
5:  q     PRIMITIVE-REPR(   , q)
6:  C     empty sequence of quaternions
7:  while vS0(nrd(q)) > 0 do
8:   Find qmin from G such that qmin−1q is in
and vS0(nrd(qmin−1q)) minimal possible
9:   Add qmin to the end of C, q     qmin−1q
10:  end while
11:  Add TWO-SIDED-DECOMPOSE(q,    , S) to the end of C
12:  return C
13: end procedure
Output: Outputs q1, . . . , qm, u1, . . . , un such that there product is q, where qi are from
genSpr (   ) and uj are generators of the unit group
14: procedure TWO-SIDED-DECOMPOSE(q,    , S)
(assumes that two side ideal class group of (a,bF)
is trivial)
15:  Q1, . . . , QM - generators of prime ideals with the norm that divides discriminant
of (a,bF)
and from S
16:  C     empty sequence of quaternions
17:  Find α from F such that αq is integral and nrd(αq) does not divide the
discriminant of (a,bF),
q     αq
18:  while vS(nrd(q)) > 0 do
19:   Find qmin from Q1, . . . , QM such that qmin−1q is in
20:   Add qmin to the end of C, q     qmin−1q
21:  end while
22:  Add UNIT-DECOMPOSE(q) to the end of C
23:  return C, α
24: end procedure
Input: Maximal order     of (a,bF),
an element q of
(assumes that two side ideal class group of (a,bF)
is trivial)
25: procedure PRIMITIVE-REPR(   , q)
26:  I     (q   q−1)
27:  Ipr     PRIMITIVE-IDEAL(I)
28:  return IDEAL-GENERATOR(I)
29: end procedure

Representative Computing Environments

FIG. 7 and the following discussion are intended to provide a brief, general description of an exemplary computing environment in which the disclosed technology may be implemented. Although not required, the disclosed technology is described in the general context of computer executable instructions, such as program modules, being executed by a personal computer (PC). Generally, program modules include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. Moreover, the disclosed technology may be implemented with other computer system configurations, including hand held devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, mainframe computers, and the like. The disclosed technology may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

With reference to FIG. 7, an exemplary system for implementing the disclosed technology includes a general purpose computing device in the form of an exemplary conventional PC 700, including one or more processing units 702, a system memory 704, and a system bus 706 that couples various system components including the system memory 704 to the one or more processing units 702. The system bus 706 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. The exemplary system memory 704 includes read only memory (ROM) 508 and random access memory (RAM) 710. A basic input/output system (BIOS) 712, containing the basic routines that help with the transfer of information between elements within the PC 700, is stored in ROM 708. As shown in FIG. 7, the system memory 704 stores computer-executable instructions for quaternion mapping, defining special unitaries, finding projective gate sets, algebraic computations, and exact/approximate circuit synthesis in memory portions 716, 711, 718, 720, 721, respectively.

The exemplary PC 700 further includes one or more storage devices 730 such as a hard disk drive for reading from and writing to a hard disk, a magnetic disk drive for reading from or writing to a removable magnetic disk, and an optical disk drive for reading from or writing to a removable optical disk (such as a CD-ROM or other optical media). Such storage devices can be connected to the system bus 706 by a hard disk drive interface, a magnetic disk drive interface, and an optical drive interface, respectively. The drives and their associated computer readable media provide nonvolatile storage of computer-readable instructions, data structures, program modules, and other data for the PC 700. Other types of computer-readable media which can store data that is accessible by a PC, such as magnetic cassettes, flash memory cards, digital video disks, CDs, DVDs, RAMs, ROMs, and the like, may also be used in the exemplary operating environment.

A number of program modules may be stored in the storage devices 730 including an operating system, one or more application programs, other program modules, and program data. Storage of quantum syntheses and instructions for obtaining such syntheses can be stored in the storage devices 730. A user may enter commands and information into the PC 700 through one or more input devices 740 such as a keyboard and a pointing device such as a mouse. Other input devices may include a digital camera, microphone, joystick, game pad, satellite dish, scanner, or the like. These and other input devices are often connected to the one or more processing units 702 through a serial port interface that is coupled to the system bus 706, but may be connected by other interfaces such as a parallel port, game port, or universal serial bus (USB). A monitor 746 or other type of display device is also connected to the system bus 706 via an interface, such as a video adapter. Other peripheral output devices, such as speakers and printers (not shown), may be included. In some cases, a user interface is display so that a user can input a circuit for synthesis, and verify successful synthesis.

The PC 700 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 760. In some examples, one or more network or communication connections 750 are included. The remote computer 760 may be another PC, a server, a router, a network PC, or a peer device or other common network node, and typically includes many or all of the elements described above relative to the PC 700, although only a memory storage device 762 has been illustrated in FIG. 7.

The personal computer 700 and/or the remote computer 760 can be connected to a logical a local area network (LAN) and a wide area network (WAN). Such networking environments are commonplace in offices, enterprise wide computer networks, intranets, and the Internet.

When used in a LAN networking environment, the PC 700 is connected to the LAN through a network interface. When used in a WAN networking environment, the PC 700 typically includes a modem or other means for establishing communications over the WAN, such as the Internet. In a networked environment, program modules depicted relative to the personal computer 700, or portions thereof, may be stored in the remote memory storage device or other locations on the LAN or WAN. The network connections shown are exemplary, and other means of establishing a communications link between the computers may be used.

With reference to FIG. 8, an exemplary system for implementing the disclosed technology includes computing environment 800, where compilation into PES derived quantum circuits is separated from the quantum processing that consumes the compiled circuits. The environment includes a quantum processing unit 802 and one or more monitoring/measuring device(s) 846. The quantum processor executes quantum circuits that are precompiled by classical compiler unit 820 utilizing one or more classical processor(s) 810. The precompiled quantum circuits are downloaded into the quantum processing unit via quantum bus 806. Synthesis procedures associated with quaternion algebras and projective gates are stored in a memory 821, and special unitaries or procedures associated with such unitaries are stored in a memory 803.

With reference to FIG. 8, the compilation is the process of translation of a high-level description of a quantum algorithm into a sequence of quantum circuits. Such high-level description may be stored, as the case may be, on one or more external computer(s) 860 outside the computing environment 800 utilizing one or more memory and/or storage device(s) 862, then downloaded as necessary into the computing environment 800 via one or more communication connection(s) 850. Gate sets (circuits) 805 defined using projective gate sets and quaternion algebra based synthesis are coupled to the quantum processor 802.

Having described and illustrated the principles of the disclosed technology with reference to the illustrated embodiments, it will be recognized that the illustrated embodiments can be modified in arrangement and detail without departing from such principles. For instance, elements of the illustrated embodiments shown in software may be implemented in hardware and vice-versa. Also, the technologies from any example can be combined with the technologies described in any one or more of the other examples. It will be appreciated that procedures and functions such as those described with reference to the illustrated examples can be implemented in a single hardware or software module, or separate modules can be provided. The particular arrangements above are provided for convenient illustration, and other arrangements can be used.

Claims

1. A quantum circuit synthesis method implemented on a classical processor, comprising: with the classical processor, selecting a single-qubit gate set; andwith the classical processor, processing the single-qubit gate set and determining a projective gate set corresponding to the single-qubit gate set, wherein the projective gate includes gates representable in a form

2. The quantum circuit synthesis method of claim 1, further comprising determining a mapping of the projective gate set to a quaternion algebra.

3. The quantum circuit synthesis method of claim 2, wherein determining the mapping comprises establishing elements of the quaternion algebra.

4. The quantum circuit synthesis method of claim 2, wherein the mapping is associated with a selected nth root of unity.

5. The quantum circuit synthesis method of claim 4, wherein the mapping is associated with an 8th or 10th root of unity.

6. The quantum circuit synthesis method of claim 2, wherein the elements of the quaternion algebra are established based on at least one Pauli matrix.

7. The quantum circuit synthesis method of claim 2, wherein the elements of the quaternion algebra are established so that a first element corresponds to an identity matrix and a second element is associated with at least one of a Pauli X, Y, or Z matrix.

8. The quantum circuit synthesis method of claim 2, further comprising determining a maximal order associated with the quaternion algebra that includes elements corresponding to the single-qubit gate set.

9. The quantum circuit synthesis method of claim 8, further comprising determining a set of ideals corresponding to the single-qubit gate set.

10. The quantum circuit synthesis method of claim 2, wherein the single-qubit gate set is associated with the Clifford+T basis or the V-basis.

11. A quantum circuit synthesizer, comprising: a processor; andat least one memory coupled to the processor and having stored thereon processor-executable instructions for a method that includes:with the processor, selecting a single-qubit gate set, andwith the processor, processing the single-qubit gate set and determining a projective gate set corresponding to the single-qubit gate set, wherein the projective gate set includes gates representable in a form

12. The quantum circuit synthesizer of claim 11, wherein the method further comprises determining a mapping of the projective gate set to a quaternion algebra.

13. The quantum circuit synthesizer of claim 11, wherein determining the mapping comprises establishing elements of the quaternion algebra.

14. The quantum circuit synthesizer of claim 11, wherein the mapping is associated with a selected nth root of unity.

15. The quantum circuit synthesizer of claim 11, wherein the mapping is associated with an 8th or 10th root of unity.

16. The quantum circuit synthesizer of claim 11, wherein the elements of the quaternion algebra are established based on at least one Pauli matrix or wherein the elements of the quaternion algebra are established so that a first element corresponds to an identity matrix and a second element is associated with at least one of a Pauli X, Y, or Z matrix.

17. The quantum circuit synthesizer of claim 11, wherein the method further comprises determining a maximal order associated with the quaternion algebra that includes elements corresponding to the single-qubit gate set.

18. The quantum circuit synthesizer of claim 11, wherein the method further comprises determining a set of ideals corresponding to the single-qubit gate set.

19. The quantum circuit synthesizer of claim 11, wherein the single-qubit gate set is associated with the Clifford+T basis or the V-basis.