Patent Application
20140281132
Non-volatile memory systems, such as flash memory, have been widely adopted for use in consumer products. Flash memory may be found in different forms, for example in the form of a portable memory card that can be carried between host devices or as a solid state disk (SSD) embedded in a host device.
Some flash memory management systems employ self-caching architectures for data buffering and data caching. For example, caching may be used for data buffering where data received from the host device is first stored in a portion of the memory designated as the cache and is later copied to a portion of the flash memory designated as a main storage area (such as a multi-level cell (MLC) type flash memory). As another example, caching may be used for control data storage to improve operation time. Control data may include mapping tables and other memory management data used by in the flash memory.
When a host device sends a write command with data to a flash memory device, it is typically desirable to write that data into the flash memory as quickly as possible to make room for a next data write command and avoid making the host wait. Typically, a flash memory device will write received data into the cache portion of memory as soon as it is received. However, because the process of writing into flash memory generally takes a fixed amount of time for each write operation, the pattern of data writes from a host can slow down the ability of a flash memory device to handle the influx of data, particularly when the host writes data in small fragments.
In order to address the problem noted above, a method and system for coalescing writes of data fragments received from a host prior to writing the data fragments into flash memory is disclosed.
According to a first aspect of the invention, a method of storing data received from a host system is disclosed. The method includes, in a memory device having a non-volatile memory, a volatile memory and a controller in communication with the non-volatile memory and volatile memory, the controller receiving data fragments from the host system. Each data fragment consists of an amount of data less than a physical page size managed in the non-volatile memory. The method continues with storing the data fragments in the volatile memory as they are received and, upon receiving a predetermined number of the data fragments, aggregating that predetermined number of data fragments into a single write command having a cumulative amount of data equal to the physical page size managed in the flash memory. Upon aggregating the predetermined number of data fragments, the cumulative amount of data aggregated in the single write command is then written in one programming operation into the non-volatile memory.
According to another aspect, a mass storage memory system, includes an interface adapted to receive data from a host system, a volatile memory, a non-volatile memory, and a controller in communication with the interface, volatile memory and the non-volatile memory. The controller is configured to receive data fragments from the host system, where each data fragment contains an amount of data less than a physical page size managed in the non-volatile memory. The controller is further configured to store the data fragments in the volatile memory as they are received and, upon receiving a predetermined number of the data fragments, aggregate the predetermined number of data fragments into a single write command having a cumulative amount of data equal to the physical page size managed in the flash memory. Upon aggregating the predetermined number of data fragments, the controller writes the cumulative amount of data aggregated in the single write command in one programming operation into the non-volatile memory.
In different implementations, the data aggregated in the single write command may include control data generated by the controller containing index information on a location for the data in the non-volatile memory. The index information may be aggregated into a single entry having index information for all of the data fragments in the predetermined number of data fragments. In other alternative implementations, the method and system may, if a predetermined amount of time elapses prior to receiving the predetermined number of data fragments, aggregate data fragments currently stored in the volatile memory into an abbreviated single write command having less than the predetermined number of data fragments; and then write the abbreviated single write command to the non-volatile memory.
A flash memory system suitable for use in implementing aspects of the invention is shown in
The storage device 102 contains a controller 106 and a memory 110. As shown in
One or more types of data may be cached in RAM 114 in storage device 102. One type of data that may be cached in storage device 102 is host data, which is data sent to or received from the host device 100. Another type of data that may be cached in storage device 102 is control data. Other types of data for caching are contemplated. The memory 110 may include non-volatile memory (such as NAND flash memory). One or more memory types may compose memory 110, including without limitation single level cell (SLC) type of flash configuration and multi-level cell (MLC) type flash memory configuration. The SLC flash may be configured as a binary cache 118 and SLC or MLC may be used as main storage 120.
In one implementation, the processor 108 of the storage device 102 may execute memory management instructions 116 (which may be resident controller memory 112) for operation of the memory management functions, such as detailed in
ARAM 206 may be RAM provisioned for control data caching. In this way, ARAM 206 may be considered a permanent control data caching area. For example, ARAM 206 may contain a group allocation table (GAT) page cache. Part or all of the control data stored in memory 110 may be stored in cache RAM in controller 106 to improve operation speed. TRAM 204 may include a data buffer 208 that is provisioned for host data caching for host data to/from flash 214 (e.g. binary cache 118). In this way, TRAM 204 may be considered a permanent host data caching area. In one embodiment, the TRAM data buffer 208 may be sized to hold at least a number of host data fragments that equal an amount of data equal to a physical page size managed in flash memory, such as the binary cache 118. The flash memory 214 may be divided into one or more different portions (such as four portions as illustrated in
Referring now to
When fragments of LGs are written into the binary cache 118, they are mapped in a table referred to as a binary cache index (BCI) 306 to track the logical to physical address relationship for a data fragment 308 associated with a LG currently written into a binary cache block 310. Although the binary cache indices 306 are one type of control data that is typically stored in the binary cache portion of flash memory 110, a copy of all or a portion of the binary cache indices 312 may also be maintained (cached) in RAM 114 due to frequent use or recent use. Logical group address tables (GAT) 314 are kept in main storage flash memory 120. The GAT pages 314 provide the logical to physical mapping for logical groups of data and, as with the binary cache indices 306, a copy of some or all of the GAT pages may also be cached in RAM 114 in the storage device 102. The cached GAT pages 316 point to the physical locations for the update or intact blocks in main storage flash memory 318 for each of the respective logical groups.
In the embodiment illustrated in
Control data may include data related to managing and/or controlling access to data stored in memory 110. The binary cache 118 may store up-to-date fragments of the logical groups (LGs). The main storage may comprise the data storage for the LGs. Control data may be used to manage the entries in memory, such as entries in binary cache 118 and main storage 120. For example, a binary cache index (BCI) may receive a Logical Block Address (LBA), and may map/point to the most up-to-date fragment(s) of the LG in binary cache 118. The GAT may receive the LBA address and map to the physical location of the LG in the main storage 120.
The processor 108 (executing the memory management instructions 23) may assign one or more portions in memory (such as volatile memory) for caching of the one or more types of data. For example, the processor 108 may assign or allocate portions of volatile memory in controller memory 112 as one or more cache storage areas, as discussed in more detail below. The one or more cache storage areas in controller memory 112 may include a portion (or all) of the BCI and GAT that is stored in flash memory 110.
The processor 108 may assign an area of volatile memory as a “permanent” cache storage area, which is an area that cannot be reclaimed by the processor 108 for a different purpose (such as for caching of a different type of data). The processor 108 may also assign an area of volatile memory as a “temporary” cache storage area, which is an area that can be reclaimed by the memory management functions for a different purpose (such as for caching of a different type of data). The processor 108 may determine whether there is a storage area available for use as a temporary data cache area. If so, the processor 108 may assign the available storage area for use as the temporary data cache area. The available storage area may be used as the temporary data cache area until the available storage area is reclaimed for another purpose.
As discussed above, data fragments 308 will eventually be written to binary cache blocks. However, when data fragments 308 are first received at a storage device 102, they are stored in volatile memory such as TRAM 204 with other volatile memory in the controller 106. Referring now to
If a predetermined number of data fragments have been received (at 406) then an aggregated binary cache index entry is generated. The aggregated binary cache index entry, also referred to herein as a BCI delta, includes location information in the binary cache for each of the received data fragments that are to be aggregated and sent in a single flash write message to the binary cache. The BCI delta may be an entry with multiple pointers, each pointer directed to a different data fragment to be aggregated (at 410). The controller then coalesces (e.g. aggregates) the received fragments and the BCI delta into a single command having a payload size of one binary cache physical page (at 412). The information in a BCI delta may have a same data size as one of the host data fragments.
After coalescing the BCI delta and the data fragments, the controller then writes the data fragments and corresponding BCI delta index entry to the binary cache 118 in a single flash write operation (at 414). Alternatively, if the predetermined number of data fragments has not yet been received by the controller 106, then the controller continues to wait and store data fragments in volatile memory until enough data fragments have been received to complete the binary cache size physical page of data. Thus, in a first embodiment, the decision for when the controller 106 will send data fragments that have been received and stored in controller memory 112 may be exclusively based on whether the predetermined number of fragments necessary to generate a physical page worth of data have been received.
In an alternative embodiment, the process may optionally include the additional criteria of monitoring an elapsed time from when the first data fragment currently in the controller memory 112 was received. For example, if one or more data fragments have been received, but the predetermined number has not yet been received, then the controller 106 may look at an elapsed time from when the first of the data fragments currently in controller RAM was received and, if the time is greater than a predetermined amount of time (at 406, 408) then the controller may send to the binary cache whatever data fragment or fragments (currently less than the predetermined number) are currently in the volatile controller memory. The predetermined time may be a fixed or variable time measured as an elapsed time since the first of the fragments currently in volatile memory was received. The controller may include an internal timer function that provides a time stamp to the first received data fragment and then periodically checks the timer to see if the time difference between the current time and the time stamp has reached a threshold. The threshold may be set to any of a number of lengths of time, for example 5 seconds, at the time of manufacture.
This abbreviated single write message would be assembled by generating an abbreviated BCI delta that includes location information for the one or more data fragments (at 410) and then coalescing the one or more data fragments and the abbreviated BCI delta entry into an abbreviated single write command. This abbreviated single write command would be sent into the binary cache and written in a single flash write operation. Thus, although the optimal amount of data fragments would not be sent in this embodiment, the optional steps of also determining whether a predetermined amount of time has elapsed would permit the controller to avoid unnecessary delays in getting data fragments into the binary cache if the host is not particularly active or if the number of data fragments are very low and infrequent. The process of storing data fragments in volatile memory, coalescing the different data fragments until a predetermined amount have been reached, or optionally, until a predetermined amount of time has elapsed, may be continually repeated.
As part of executing the process described above with respect to
Referring to
In contrast, as illustrated in the time line 600 of
Although certain NAND programming times, data fragment sizes, and physical page sizes have been assumed in the examples above, any of a number of different programming timing, data fragment sizes, and physical page sizes, or combinations thereof, may be implemented in different embodiments.
As disclosed above, a system and method may gather multiple fragments of received host data in controller RAM before issuing a single program command to the NAND. Instead of programming one received data fragment at a time to the NAND as in the current write algorithms, the disclosed system and method allows programming multiple fragments at a time. Therefore, coalescing data fragment writes from a host in RAM in the memory device may effectively reduce the amount of NAND programming operations. Whenever a write command with a data fragment is received from the host, the memory device stores the fragment temporarily in the controller RAM memory and/or in the NAND internal memory latches. When a favorable number of fragments are gathered, the controller will then move this group of fragments from the temporary location in RAM to the NAND flash cells of the flash memory using a minimal number of programming operations.
In an alternative embodiment, the process of improving the efficiency of writing to NAND flash memory from RAM may further include a mechanism for minimizing the number of control writes to the NAND for each fragment. Instead of a separate control write for each data fragment in the BCI, a BCI delta is disclosed where index information that is written into the NAND references multiple fragments in a single BCI delta entry. Combining these two features may improve the amount of data that is programmed per die page and improves the random input/output performance of the memory device. Ideally, the size of the total amount of fragments that are gathered to be programmed at the same time should be smaller than or equal to a physical page size in NAND (e.g. the binary cache). In this way, the RAM cache coalescing steps noted above may help to reduce the amount of NAND programming operations by using each NAND programming operation more efficiently.
It is intended that the foregoing detailed description be understood as an illustration of selected forms that the invention can take and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of this invention.
