This is a continuation of application Ser. No. 08/340,766, filed Nov. 16, 1994 now abandoned.
Number | Name | Date | Kind |
---|---|---|---|
3840862 | Ready | Oct 1974 | |
4885680 | Anthony et al. | Dec 1989 | |
5025365 | Mathur et al. | Jun 1991 | |
5133061 | Melton et al. | Jul 1992 | |
5206941 | Eikill et al. | Apr 1993 | |
5257361 | Doi et al. | Oct 1993 | |
5325503 | Stevens et al. | Jun 1994 | |
5325504 | Tipley et al. | Jun 1994 | |
5467459 | Alexander et al. | Nov 1995 | |
5481691 | Day, III et al. | Jan 1996 |
Number | Date | Country |
---|---|---|
A-2 150 424 | Apr 1973 | FRX |
WO 93 04429 | Mar 1993 | WOX |
Entry |
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Handy, "the Cache Memory Book", 1993, pp. 14-22. |
Schneider et al., "Concepts in Data Structures & Software Development", 1991, pp. 261-274 & 285-294. |
Intel, "Intel 386 DX Microprocessor Hardware Reference Manual", 1991, pp. 7-3 to 7-8. |
Patent Abstracts of Japan, vol. 18, No. 630 (P-1835), Nov. 30, 1994, JP-A-06 243045, Sep. 2, 1994. |
Proceedings of the Annual International Symposium on Computer Architecture, Chicago, Apr. 18-21, 1994, Seznec, Andre. "Decoupled Sectored Caches: conciliating low tag implementation cost and low miss ratio," pp. 384-393. |
Number | Date | Country | |
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Parent | 340766 | Nov 1994 |