Patent Application
20080197454
The present invention relates to devices formed from a semiconductor substrate, such as a crystalline silicon substrate, and, more particularly to a method and system for removing impurities from low-grade crystalline silicon wafers, including by gettering impurities using phosphorus diffusion on damaged surfaces of such substrates.
Materials alternatives for solar cells range from single-crystal, electronic-grade (EG) silicon to relatively dirty, metallurgical-grade (MG) silicon. EG silicon yields solar cells having efficiencies close to the theoretical limit of all silicon materials, but at a prohibitive price. On the other hand, the less expensive MG silicon typically fails to produce working solar cells. There may be other semiconductor materials that are useful for solar cell fabrication. In practice, however, nearly 90% of commercial solar cells are made of crystalline silicon.
Several factors determine the quality of silicon materials that may be useful for solar cell fabrication. These factors may include, for example, transition metal and/or other dopant content and their distribution throughout the silicon substrate. Transition metals pose a principal challenge to the efficiency of crystalline silicon solar cells. Multicrystalline silicon solar cells may tolerate transition metals such as iron (Fe), copper (Cu), or nickel (Ni) in concentrations up to 1016 cm3, because metals in multicrystalline silicon are often found in less electrically active inclusions or precipitates, often located at structural defects (e.g., grain boundaries), rather than being atomically dissolved. However, no simple correlation exists between the total metal content of the semiconductor wafer and cell efficiencies across different. Accordingly, understanding the physics and the properties of metal clusters in solar cells, as well as using these properties to operational and economic advantage, could yield significant process and product improvements. Such improvements, because of their associated enhanced economies and manufacturability, are likely to make solar power attractive and practical for an essentially unlimited number of energy demands.
The purity requirements for the semiconductor materials that may be useful in solar cells typically are not as stringent as are those for the integrated circuitry industry. In fact, the solar cell industry may sometimes use recycled, scrapped, or rejected semiconductor material from the integrated circuitry industry. However, transition metal impurities are known to decrease the solar cell conversion efficiency. This leads to poor performance and a poor cost-to-performance ratio. While the impurities may be removed using a variety of well-known techniques for purifying silicon, known techniques add additional cost to the solar cell manufacturing process. This, in essence, vitiates the motivation for using such lower quality Refined Metallurgical silicon RMG wafers.
In attempting to use a lower-grade silicon for solar cell and similar applications, approaches employing phosphorus gettering have been proposed. One particular approach seeks to perform phosphorus gettering during the fabrication of a solar cell emitter. A modification to this approach changes the temperature profile of the phosphorus diffusion by adding a low temperature tail in the process. This further modification may result in carrier lifetime enhancements beyond those of more traditional phosphorus gettering techniques.
A known phosphorus gettering process for a silicon wafer seeks to enhance carrier lifetime during phosphor indiffusion when forming the p-n junction. Unfortunately, this known phosphorus gettering technique has generated mixed results. For example, in one instance an increase of carrier lifetime of as much as three times has been observed on regions having low dislocation densities. On the other hand, in regions of high dislocation densities, no measurable carrier lifetime increase occurred.
While other approaches have been made, no approach provides the benefits of occurring prior to solar cell fabrication or without requiring a complicated lapping process for semiconductor wafer preparation.
Accordingly, there is the need for a process, including a phosphorus gettering process that not only getters impurities, but also removes impurities from the semiconductor wafer and that prior to cell fabrication.
There is the need for a process that removes impurities from semiconductor wafers, while at the same time providing for the formation of gettering sites to enhance the diffusion of impurities from the substrate. Yet, this need must be met without further expense and process complexity.
Yet a further need exists for a process for impurity gettering in a semiconductor substrate wherein the gettering sites at a desired location of the wafer may be formed before gettering occurs. Such a process would most advantageously provide for the surface of the substrate to be prepared for a gettering process, and then exposed to phosphorus gettering.
Meeting the above-stated needs could provide a significant improvement in the formation of silicon wafers from lower-grade silicon, thereby aiding to make solar power generation systems using such solar cells much more economical and achievable.
Techniques are here disclosed for providing improved semiconductor solar cells using low grade semiconductor material. The presently disclosed process and system remove impurities in a semiconductor substrate such as a refined metallurgical-grade crystalline silicon substrate or device. The process includes forming lattice damage on at least one, and preferably two, sides of the semiconductor substrate. This may include mechanically inducing damage. Thereafter, phosphorus gettering the substrate at a sufficient temperature and time causes impurities to diffuse close to the gettering centers of the substrate surface. Optionally, a subsequent hydrogen treatment may passivate defects in the silicon substrate. A subsequent etch step then removes the damaged regions along with the gettered impurities. Principally, the present disclosure relates to silicon materials, although use of other semiconductor materials may be within the scope of the presently claimed method and system.
According to another aspect of the disclosed subject matter, therefore, a solar cell pre-processing method and associated system are provided for removing impurities from low-grade crystalline silicon wafers. The disclosed pre-processing method and system remove impurities from low-grade crystalline semiconductor wafers having high impurity content. The process and system damage at least one surface of the semiconductor wafer, either in the semiconductor wafer forming step or in a separate step, to form a region on the surface that includes a plurality of gettering centers. The gettering centers attract impurities from the substrate during subsequent processing. The subsequent processes include diffusing impurities from the substrate using a phosphorus gettering process that includes impregnating the wafer surface with a phosphorus material that facilitates the formation of impurity clusters associated with the gettering centers. Then, the process and system remove from the at least one surface a portion comprising the impregnated phosphorus material and the impurity clusters to yield a semiconductor wafer comprising a substrate having a generally reduced impurity content. The low-grade semiconductor wafer may be, for example, refined metallurgical grade crystalline silicon or upgraded metallurgical grade crystalline silicon material.
These and other advantages of the disclosed subject matter, as well as additional novel features, will be apparent from the description provided herein. The intent of this summary is not to be a comprehensive description of the claimed subject matter, but rather to provide a short overview of some of the subject matter's functionality. Other systems, methods, features and advantages here provided will become apparent to one with skill in the art upon examination of the following FIGUREs and detailed description. It is intended that such additional systems, methods, features and advantages be included within this description, be within the scope of the accompanying claims.
The features, nature, and advantages of the disclosed subject matter may become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:
The method and system of the present disclosure permit removing impurities from low-grade crystalline silicon wafers for concentrating impurities and related complexes, in particular, transition metal clusters, existing throughout a semiconductor substrate. As a result of using the presently disclosed subject matter, an improvement in the properties of low-grade semiconductor materials, such as RMG or UMG silicon, occurs. Such improvement allows use of refined MG (RMG) silicon, for example, in producing solar cells as may be used in solar power generation and related uses.
The method and system of the present disclosure, moreover, particularly benefits the formation of semiconductor solar cells using RMG silicon or other non-electronic grade semiconductor materials. The present disclosure may find application in the economical manufacture of solar cells, allowing the formation of solar cells in greater quantities and in a greater number of fabrication facilities than has heretofore been possible.
The present invention is a process for removing impurities in a semiconductor substrate such as a silicon substrate. The process comprises first creating a damaged region preferably on both sides of a low-grade silicon wafer. This may be done by sawing the ingot into numerous wafers. Here the parameter of ingot sawing (e.g. slurry size) may be changed in order to create optimal damage. Thereafter, the wafer is submitted to phosphorus diffusion for a sufficient temperature and time period to assure effective phosphorus gettering. After the gettering process follows the removal of the impurities in the damaged surfaces.
Among various technical advantages and achievements herein described, certain ones of particular note include the ability to reduce the amount of impurities present in a semiconductor wafer such as a silicon wafer in a process occurring prior to the standard solar cell fabrication. The disclosed subject matter enables processes for inexpensively making wafer treatments needed for highly efficient mass scale solar cell production. Still further, the present disclosure makes possible advantageous use of saw damage that may be inherently present after slicing a silicon ingot into wafers. That is the inherent saw damage that occurs in slicing a semiconductor wafer benefits attracting impurities in favorable thermodynamic process conditions. Also, by adding one or more contaminated layers with controlled levels of foreign atoms at the wafer surface, the disclosed process supports gettering impurities during a favorable thermodynamic treatment. The foreign atoms may include metals (e.g., iron, nickel and copper) and non-metals (e.g., phosphorus, oxygen). The process of the present disclosure removes a highly contaminated layer at the surface of the wafer using etching prior to the solar cell fabrication. The process, thereby, reduces the concentration of electrically active species within grains, while concentrating metallic impurities at grain boundaries in multicrystalline silicon. Such active species may include dislocations and metallic impurities. The disclosed subject matter, therefore, generates denuded zones in silicon wafers by applying treatments that reduce the concentration of non-surface electrically active species. Such non-surface electrically active species may be, for example, intra-grain dislocations and metallic impurities.
Laying a context for the present disclosure,
In contrast,
The present disclosure includes significant use of phosphorus gettering manipulation of a “denuded zone” to achieve silicon wafers having properties similar to silicon wafer 70 of
The present disclosure establishes thermal conditions for dissolving metals from grown-in clusters or precipitates and moving relatively fast diffusing and some portion of relatively slow diffusing metals into gettering centers at or near the damaged surface region of the semiconductor wafer. After the disclosed phosphorus gettering process occurs, the near-surface layer having impurity clusters at or near the gettering centers, as well as the phosphorus impregnated portions of the semiconductor wafer surface may be etched off, as herein described.
Mechanical damage 92 may be created on both top surface 82 and bottom surface 94 of silicon wafer 80. Photovoltaic starting materials, e.g., crystalline or multicrystalline silicon ingots, oftentimes have higher impurities than do most EG ingots. Therefore, semiconductor wafer 80, when cut from such silicon ingots have also high bulk defects and impurities 94 content which are distributed in the wafer. Semiconductor substrate 90 may further include dispersed lattice defects, small clusters of metallic impurities, grain boundaries, and medium-size clusters of metallic impurities. The present description of aspects of one side of semiconductor wafer 80 may apply to either or both sides. Such grain boundaries may separate lattice orientations and, thereby, individual grains within semiconductor substrate 90.
Assuming phosphorus to be distributed uniformly in regions 98 and 99, concentrations may reach approximately 1×1020 atoms/cm3. In this manner, top surface 82 and bottom surface 84 may become a phosphorus impregnated or implanted regions.
The present disclosure takes advantage of the wire-saw damaged surfaces 82 and 84 of semiconductor wafer 80. That is, the wire-saw damage has the characteristics of attracting metallic impurities by lattice damage and related defects generated mechanically and thermally. This means, those structural defects serve as external gettering centers for metallic impurities during thermal treatment and post-anneal cooling as indicated in
Generally dispersed, relatively small impurity clusters 94 will partially or almost completely dissolve under proper thermodynamic conditions, and the freed metallic impurities will migrate from a general dispersion within semiconductor substrate 90 to a concentrated state in regions 98 and 99. As such, there may be other ways beyond the wire saw to cause the now desirable surface conditions. Alternatively, there may be ways of modifying the conventional wire saws and/or sawing processes as may be used in cutting a semiconductor wafer 80 from a semiconductor ingot. Still further, the present disclosure contemplates the use of various measurements and control means for determining, controlling and varying the amount of wire saw damage that semiconductor wafer 80 may experience. Such modifications may be designed to enhance the defect gettering effects of the wire-saw damage and are clearly within the scope of the presently claimed subject matter.
Regardless of the wire-saw process employed, at some level, the wafer formation process causes damage which is transformed into suitable lattice defects used for external gettering of metallic impurities.
Thus, as
As a result of the gettering and clustering of impurities toward top surface 82 and bottom surface 84, the impurities transition from being generally dispersed in a semiconductor wafer to becoming concentrated close to the surfaces of respective wafers. A cooling step follows the annealing step for forming and retaining the metal-containing clusters within the surface regions. This increases the purity level of the semiconductor wafer in regions from which the impurities are gettered. The disclosed method and system remove the largely contaminated wafer surface layer, including the impurity clusters, to yield a semiconductor wafer having a generally higher purity level. Removed thickness may vary between 1 μm-40 μm using standard etching procedures for removal.
The disclosed subject matter, therefore, includes adding purposely at least one contaminated surface layer, containing metallic impurities with a concentration ranging from 1010-1017 cm−3, on top of the saw damaged surfaces of the wafer. This layer adds defined amounts of metallic species which will favor the formation of large inter-metallic clusters during the annealing treatment. Large impurity clusters form partially in the near-surface regions and thereby getter impurities, so that the procedure is similar to the one described above which involves annealing at sufficiently high temperature, cooling at a thermodynamically favorable rate and then removing the layer using standard etching techniques.
Although various embodiments which incorporate the teachings of the present disclosure have been shown and described in detail herein, those skilled in the art may readily devise many other varied embodiments that still incorporate these teachings. For example, many different types of phosphorus gettering steps, etch and cleaning steps and other processing steps may be performed in association with the disclosed process and system. Also the present embodiments may be implemented in a batch or single wafer processes or in repeated sequences of annealing and processing steps as herein detailed, all such modifications falling within the scope of the present disclosure. The foregoing description of the preferred embodiments, therefore, is provided to enable any person skilled in the art to make or use the claimed subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the innovative faculty. Thus, the claimed subject matter is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
