Patent Application
20240403061
The disclosure belongs to the technical field of option setting for basic input output system, and particularly relates to a method and system for setting options of a basic input output system (BIOS), a device and a storage medium.
As server technologies are constantly promoted and developed, performances, functions and ease of use of servers are constantly enhanced. A growing number of BIOS Setup configuration options are provided in the servers, and different clients can configure different option combinations according to their own business requirements. In a setting process, the following problems may be encountered: 1. a situation that clients are generally required to check status values of combined options in a business mode, 2. batch modification of the combined options, 3. batch modification of multi-node combined options, 4. configuration switching of combined options in different application modes of nodes, and 5. a situation that options take effects at next re-startup after being set by the clients. It is commonly required to enter a BIOS Setup interface to set options. However, a business operation mode generally exists in an operating system (OS). Even if the clients can enter the Setup interface through re-startup, batch modification and switching bring tremendous amount of work and adaptation cost to research, development, testing, operation and maintenance, which troubles users and is not conducive to ease of use of a server system.
In order to solve the above problems, the disclosure provides a method and system for setting options of a basic input output system (BIOS), a device and a storage medium. The BIOS carries out logical processing by means of some flag bits, such that the options are synchronized and set between different combination modes are implemented, and operation is simple.
In order to achieve the above objective, the disclosure employs a method as follows:
A method for setting options of a BIOS includes steps as follows:
Further, the first combination structure includes a first header, an offset and a value corresponding to each option, and a default value corresponding to each option.
Further, the second combination structure further includes a second header. The second header includes a first byte and a second byte. The first byte is a byte of a value corresponding to a mode in the BIOS. The second byte is a byte when a user sets the options.
Further, the configure value represents an invalid mode, a first valid mode and a second valid mode.
The invalid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 0.
The first valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 1.
The second valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 2.
Further, the BIOS clears the configure value in the second combination structure under the condition that the configure value read from the second combination structure is the invalid mode. A configure value of the first combination structure is sent to the baseboard management controller by means of an intelligent platform management interface (IPMI). The configure value of the first combination structure is set as 1.
Further, the BIOS calculates a first cyclic redundancy check code in the first combination structure under the condition that the configure value read from the second combination structure is the first valid mode. Moreover, the baseboard management controller is triggered to calculate a second cyclic redundancy check code of an option in the second combination structure. Startup is continued under the condition that the first cyclic redundancy check code is the same as the second cyclic redundancy check code.
The BIOS acquires the option in the second combination structure under the condition that the first cyclic redundancy check code is different from the second cyclic redundancy check code. The option is written into a BIOS storage module. The option in the second combination structure written into the BIOS storage module is set as 0. Re-startup is carried out after setting is completed.
Further, the BIOS restores the option of the first combination structure to a default value under the condition that the configure value read from the second combination structure is the second valid mode. The option is set as 0. Re-startup is carried out after setting is completed.
The disclosure further provides a system for setting options of a BIOS. The system includes a creating module, a sending module and a setting module.
The creating module is configured to number different option combination modes and create a first combination structure of the options for storing numbers of the different option combination modes.
The sending module is configured to send a default option combination mode value to a baseboard management controller and form a second combination structure in the baseboard management controller.
The setting module is configured to read configure values from the second combination structure and execute different operations for option setting according to different configure values.
The disclosure further provides a device. The device includes:
The disclosure further provides a Non-Volatile readable storage medium. The Non-Volatile readable storage medium is configured to store a computer program. When the computer program is executed by a processor, the processor performs steps of the above methods.
Effects provided in the summary are only effects of some embodiments of the disclosure, rather than all effects of the disclosure. One of the above methods has advantages or beneficial effects as follows:
The disclosure provides a method and system for setting options of a BIOS, a device and a storage medium. The method includes: numbering different option combination modes; creating a first combination structure of the options configured to store numbers of the different option combination modes; sending a default option combination mode value from the BIOS to a baseboard management controller, and forming a second combination structure in the baseboard management controller; and reading configure values from the second combination structure, and executing different operations for option setting according to different configure values. On the basis of the method for setting options of a BIOS, a system for setting options of a BIOS, a device and a storage medium are provided. According to the disclosure, the options occupy a small storage space of the baseboard management controller, such that cost of a memory is saved. The BIOS carries out logical processing by means of some flag bits, such that the options are synchronized and set between the different combination modes are implemented. Moreover, when out-of-band modification is performed on the options, it is only required to set an offset and a value corresponding to an option in the baseboard management controller on a command. Non-research-and-development personnel only need to have a corresponding offset corresponding table to modify the options, such that simpleness is achieved and operation is easy. Finally, load default operation on the options is simple, and only one-bit modification is required.
The disclosure is generally used on an application based on a baseboard management controller and an IPMI, and occupies a small storage space of the baseboard management controller. The logic for sending and synchronization of an option in the BIOS is simple. Operation for setting options of BIOS by non-research-and-development personnel is simple. Operation for loading default of the options is simple. Switching between the different option combination modes is simple.
In order to clearly describe the technical features of the disclosure, the disclosure will be described below in detail with some embodiments and the drawings. The following disclosure provides plenty of different examples or instances for implementing different structures of the disclosure. In order to simplify the disclosure, components and arrangements in particular instances will be described below. In addition, the disclosure can repeat reference numbers and/or letters in different instances. Such repetition is for simplicity and clarity, and does not indicate relations between various examples and/or arrangements discussed. It should be noted that components illustrated in the drawings are not certainly drawn to scale. Descriptions of well-known assemblies and processing technologies and processes are omitted in the disclosure, such that unnecessary limitation on the disclosure is avoided.
The disclosure integrates codes through BIOS and BMC to cover application scenarios of the clients, and uses the out-of-band management tool BMC and intelligent platform management interface (IPMI) commands to set options. Thus, research, development and maintenance cost is reduced and competitiveness of products is improved. BMC is a baseboard management controller, and BIOS is a basic input output system.
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Some embodiments of the disclosure provide a method for setting options of a basic input output system (BIOS), which sets the BIOS options on the basis of a baseboard management controller (BMC) and intelligent platform management interface (IPMI) manner. The method includes: number different option combination modes; create a first combination structure of the options configured to store numbers of the different option combination modes; send a default option combination mode value from the BIOS to a baseboard management controller, and form a second combination structure in the baseboard management controller; and read configure values from the second combination structure, and execute different operations for option setting according to different configure values.
The configure value represents an invalid mode, a first valid mode and a second valid mode.
The invalid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 0.
The first valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 1.
The second valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 2.
The BIOS clears the configure value in the second combination structure under the condition that the configure value read from the second combination structure is the invalid mode. A configure value of the first combination structure is sent to the baseboard management controller by means of an IPMI. The configure value of the first combination structure is set as 1.
The BIOS calculates a first cyclic redundancy check code in the first combination structure under the condition that the configure value read from the second combination structure is the first valid mode. Moreover, the baseboard management controller is triggered to calculate a second cyclic redundancy check code of an option in the second combination structure. Startup is continued under the condition that the first cyclic redundancy check code is the same as the second cyclic redundancy check code.
The BIOS acquires the option in the second combination structure under the condition that the first cyclic redundancy check code is different from the second cyclic redundancy check code. The option is written into a BIOS storage module. The option in the second combination structure written into the BIOS storage module is set as 0. Re-startup is carried out after setting is completed.
The BIOS restores the option of the first combination structure to a default value under the condition that the configure value read from the second combination structure is the second valid mode. The option is set as 0. Re-startup is carried out after setting is completed.
In the disclosure, firstly, the modes of different option combinations are numbered by the BIOS. Secondly, a specific option combination structure is created in the BIOS, the combination structure has a header and stores numbers of the modes. Each option corresponds to an offset and a value. Moreover, the BIOS stores a default value corresponding to each option. The baseboard management controller is not required to consider how an option in the BIOS option structure is composed, and only required to receive offsets and values sent from the BIOS and sequentially sort the offsets and values to form a temporary structure. The baseboard management controller stores bytes of special values in a header of the temporary structure. One is a byte of a value corresponding to a mode in the BIOS and is referred to as A. The other one is a byte when a user sets the options and is referred to as B. The BIOS and baseboard management controller only need to perform logical processing according to such bytes to achieve option settings, synchronization, and switching.
At step S201, a machine is started.
The BMC is empty. A default option combination mode value is sent to the baseboard management controller by the BIOS. The structure of the baseboard management controller only generates a header, the header storing synchronized mode value A and value B which is 0 by default. When a user wants to switch a specific mode, A is modified. The BIOS carries out switching according to value A at next startup. Operation steps of specific options are fixed in mode A.
At step S202, an option and a configure value in the baseboard management controller is set by means of ipmi write command of a user.
At step S203, the configure value is read from the second combination structure of the baseboard management controller by the BIOS by means of ipmi read command. Determine a mode represented by the configure value. The configure value represents an invalid mode, a first valid mode and a second valid mode. The invalid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 0. The first valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 1. The second valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 2. Execute S204 in a case that the configure value is 0 or invalid. Execute S206 in a case that the configure value is 1. Execute S209 in a case that the configure value is 2.
At step S204, the configure value in the second combination structure is cleared by the BIOS. A configure value of the first combination structure is sent to the baseboard management controller by means of an IPMI. The configure value of the first combination structure is set as 1.
At step S205, continue startup, wait to restart the machine next time, and not set the configure value by the baseboard management controller.
At step S206, a first cyclic redundancy check code in the first combination structure is calculated by the BIOS. The baseboard management controller is triggered to calculate a second cyclic redundancy check code of an option in the second combination structure. Determine whether the first cyclic redundancy check code is the same as the second cyclic redundancy check code by the BIOS. Execute S205 under the condition that the first cyclic redundancy check code is the same as the second cyclic redundancy check code. Execute S207 under the condition that the first cyclic redundancy check code is different from the second cyclic redundancy check code.
At step S207, write the option in the second combination structure in the baseboard management controller to a BIOS non-volatile random-access memory (Nvram) by the BIOS by means of ipmi read command, and set flag bit B of the configure value as 0x0.
At step S208, restart the machine automatically after setting is completed, and not set the configure value by the baseboard management controller.
At step S209, the option of the first combination structure is restored to a default value by the BIOS. The BIOS set flag bit B of the configure value as 0x0, and carry out re-startup after setting is completed.
Innovation points of some embodiments of the disclosure are as follows: firstly, the modes of different option combinations are numbered by the BIOS. Secondly, a specific option combination structure is created in the BIOS, the combination structure has a header and stores numbers of the modes. Each option corresponds to an offset and a value. Moreover, the BIOS stores a default value corresponding to each option. The baseboard management controller is not required to consider how an option in the BIOS option structure is composed, and only required to receive offsets and values sent from the BIOS and sequentially sort the offsets and values to form a temporary structure. The baseboard management controller stores bit of special values in a header of the temporary structure. One is bit of a value corresponding to a mode in the BIOS and is referred to as A. The other one is bit when a user sets the options and is referred to as B. The BIOS and baseboard management controller only need to perform logical processing according to such bit to achieve option settings, synchronization, and switching.
According to the method for setting options of a BIOS provided in some embodiments of the disclosure, the options occupy a small storage space of the BMC, such that cost of a memory is saved. The BIOS carries out logical processing by means of some flag bits, such that the options are synchronized and set between the different combination modes are implemented. Moreover, when out-of-band modification is performed on the options, it is only required to set offset and value corresponding to an option in the BMC on a command. Non-research-and-development personnel only need to have a corresponding offset corresponding table to modify the options, such that simpleness is achieved and operation is easy. Finally, load default operation on the options is simple, and only one-bit modification is required.
On the basis of the method for setting options of a BIOS provided in some embodiments of the disclosure, some embodiments of the disclosure further provide a system for setting options of a BIOS.
The creating module is configured to number different option combination modes and create a first combination structure of the options for storing numbers of the different option combination modes.
The sending module is configured to send a default option combination mode value to a baseboard management controller and form a second combination structure in the baseboard management controller.
The setting module is configured to read configure values from the second combination structure and execute different operations for option setting according to different configure values.
In the creating module, the first combination structure includes a first header, an offset and a value corresponding to each option, and a default value corresponding to each.
In the sending module, the second combination structure further includes a second header. The second header includes a first byte and a second byte.
The first byte is a byte of a value corresponding to a mode in the BIOS. The second byte is a byte when a user sets the options. The configure value represents an invalid mode, a first valid mode and a second valid mode. The invalid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 0. The first valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 1. The second valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 2.
In the setting module, the BIOS clears the configure value in the second combination structure under the condition that the configure value read from the second combination structure is the invalid mode. A configure value of the first combination structure is sent to the baseboard management controller by means of an IPMI. The configure value of the first combination structure is set as 1.
The BIOS calculates a first cyclic redundancy check code in the first combination structure under the condition that the configure value read from the second combination structure is the first valid mode. Moreover, the baseboard management controller is triggered to calculate a second cyclic redundancy check code of an option in the second combination structure. Startup is continued under the condition that the first cyclic redundancy check code is the same as the second cyclic redundancy check code.
The BIOS acquires the option in the second combination structure under the condition that the first cyclic redundancy check code is different from the second cyclic redundancy check code. The option is written into a BIOS storage module. The option in the second combination structure written into the BIOS storage module is set as 0. Re-startup is carried out after setting is completed.
The BIOS restores the option of the first combination structure to a default value under the condition that the configure value read from the second combination structure is the second valid mode. The option is set as 0. Re-startup is carried out after setting is completed.
According to the system for setting options of a BIOS provided in some embodiments of the disclosure, the options occupy a small storage space of the BMC, such that cost of a memory is saved. The BIOS carries out logical processing by means of some flag bits, such that the options are synchronized and set between the different combination modes are implemented. Moreover, when out-of-band modification is performed on the options, it is only required to set offset and value corresponding to an option in the BMC on a command. Non-research-and-development personnel only need to have a corresponding offset corresponding table to modify the options, such that simpleness is achieved and operation is easy. Finally, load default operation on the options is simple, and only one-bit modification is required.
Some embodiments of the disclosure further provides a device. The device includes:
Firstly, the modes of different option combinations are numbered by the BIOS. Secondly, a specific option combination structure is created in the BIOS. The combination structure has a header and stores numbers of the modes. Each option corresponds to an offset and a value. Moreover, the BIOS stores a default value corresponding to each option. The baseboard management controller is not required to consider how an option in the BIOS option structure is composed, and only required to receive offsets and values sent from the BIOS and sequentially sort the offsets and values to form a temporary structure. The baseboard management controller stores bytes of special values in a header of the temporary structure. One is a byte of a value corresponding to a mode in the BIOS and is referred to as A. The other one is a byte when a user sets the options and is referred to as B. The BIOS and baseboard management controller only need to perform logical processing according to such bytes to achieve option settings, synchronization, and switching.
At step S201, a machine is started.
The BMC is empty. A default option combination mode value is sent to the baseboard management controller by the BIOS. The structure of the baseboard management controller only generates a header, the header storing synchronized mode value A and value B which is 0 by default. When a user wants to switch a specific mode, A is modified. The BIOS carries out switching according to value A at next startup. Operation steps of specific options are fixed in mode A.
At step S202, an option and a configure value in the baseboard management controller is set by means of ipmi write command of a user.
At step S203, the configure value is read from the second combination structure of the baseboard management controller by the BIOS by means of ipmi read command. Determine a mode represented by the configure value. The configure value represents an invalid mode, a first valid mode and a second valid mode. The invalid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 0. The first valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 1. The second valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 2. Execute S204 in a case that the configure value is 0 or invalid. Execute S206 in a case that the configure value is 1. Execute S209 in a case that the configure value is 2.
At step S204, the configure value in the second combination structure is cleared by the BIOS. A configure value of the first combination structure is sent to the baseboard management controller by means of an IPMI. The configure value of the first combination structure is set as 1.
At step S205, continue startup, wait to restart the machine next time, and not set the configure value by the baseboard management controller.
At step S206, a first cyclic redundancy check code in the first combination structure is calculated by the BIOS. The baseboard management controller is triggered to calculate a second cyclic redundancy check code of an option in the second combination structure. Determine whether the first cyclic redundancy check code is the same as the second cyclic redundancy check code by the BIOS. Execute S205 under the condition that the first cyclic redundancy check code is the same as the second cyclic redundancy check code. Execute S207 under the condition that the first cyclic redundancy check code is different from the second cyclic redundancy check code.
At step S207, write the option in the second combination structure in the baseboard management controller to a BIOS Nvram by the BIOS by means of ipmi read command, and set flag bit B of the configure value as 0x0.
At step S208, restart the machine automatically after setting is completed, and not set the configure value by the baseboard management controller.
At step S209, the option of the first combination structure is restored to a default value by the BIOS. The BIOS set flag bit B of the configure value as 0x0, and carry out re-startup after setting is completed.
Innovation points of some embodiments of the disclosure are as follows: firstly, the modes of different option combinations are numbered by the BIOS. Secondly, a specific option combination structure is created in the BIOS, the combination structure has a header and stores numbers of the modes. Each option corresponds to an offset and a value. Moreover, the BIOS stores a default value corresponding to each option. The baseboard management controller is not required to consider how an option in the BIOS option structure is composed, and only required to receive offsets and values sent from the BIOS and sequentially sort the offsets and values to form a temporary structure. The baseboard management controller stores bit of special values in a header of the temporary structure. One is bit of a value corresponding to a mode in the BIOS and is referred to as A. The other one is bit when a user sets the options and is referred to as B. The BIOS and baseboard management controller only need to perform logical processing according to such bit to achieve option settings, synchronization, and switching.
According to the device for setting options of a BIOS provided in some embodiments of the disclosure, the options occupy a small storage space of the BMC, such that cost of a memory is saved. The BIOS carries out logical processing by means of some flag bits, such that the options are synchronized and set between the different combination modes are implemented. Moreover, when out-of-band modification is performed on the options, it is only required to set offset and value corresponding to an option in the BMC on a command. Non-research-and-development personnel only need to have a corresponding offset corresponding table to modify the options, such that simpleness is achieved and operation is easy. Finally, load default operation on the options is simple, and only one-bit modification is required.
It should be noted that the method of the disclosure further provides an electronic device. The electronic device includes a communication interface, which may exchange information with other devices such as a network device; and a processor, which is connected to the communication interface to exchange information with other devices and configured to execute a virtualization system monitoring method provided in at least one above methods when running a computer program. The computer program is stored in a memory. Certainly, various assembles in the electronic device are coupled together by means of a bus system during practical application. It can be understood that the bus system is configured for connection and communication between these assembles. The bus system includes a data bus, a power bus, a control bus and a status signal bus. The memory in some embodiments of the disclosure is configured to store various types of data to support operations of the electronic device. Instances of such data include any computer program configured to be operated on the electronic device. It can be understood that the memory may be a volatile memory or a non-volatile memory, and may also include both the volatile memory and the non-volatile memory. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a ferromagnetic random-access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc or a compact disc read-only memory (CD-ROM). The magnetic surface memory may be a magnetic disc memory or a magnetic tape memory. The volatile memory may be a random-access memory (RAM), which serves as an external cache. Through illustrative but not limitative description, plenty of forms of RAMs can be used, such a static random-access memory (SRAM), a synchronous static random-access memory (SSRAM), a dynamic random-access memory (DRAM), a synchronous dynamic random-access memory (SDRAM), a double data rate synchronous dynamic random-access memory (DDRSDRAM), an enhanced synchronous dynamic random-access memory (ESDRAM), a synclink dynamic random-access memory (SLDRAM) and a direct rambus random-access memory (DRRAM). The memory described in some embodiments of the disclosure includes but is not limited to these and any other suitable types of memories. The methods disclosed in some embodiments of the disclosure can be applied to or implemented by a processor. The processor may be an integrated circuit chip having a signal processing capability. In an implementation process, steps of the above method can be completed by an integrated logic circuit of hardware or an instruction in a form of software in the processor. The above processor may be a general-purpose processor, a chip for digital signal processing (DSP) or other programmable logic devices, a discrete gate or transistor logic device, or a discrete hardware component, etc. The processor can implement or execute methods, steps and logic blocks disclosed in some embodiments of the disclosure. The general-purpose processor can be a microprocessor or any conventional processor, etc. Steps of the method disclosed in combination with some embodiments of the disclosure can be directly executed by a hardware decoding processor or a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, and the storage medium is located in the memory. The processor reads a program in the memory and completes the steps of the aforementioned method in combination with hardware of the processor. The processor implements corresponding flows in the methods of some embodiments of the disclosure when executing the program, which will not be repeated herein for the sake of brevity.
Some embodiments of the disclosure further provides a Non-Volatile readable storage medium. The Non-Volatile readable storage medium is configured to store a computer program. When the computer program is executed by a processor, the processor performs method steps as follows:
Firstly, the modes of different option combinations are numbered by the BIOS. Secondly, a specific option combination structure is created in the BIOS. The combination structure has a header and stores numbers of the modes. Each option corresponds to an offset and a value. Moreover, the BIOS stores a default value corresponding to each option. The baseboard management controller is not required to consider how an option in the BIOS option structure is composed, and only required to receive offsets and values sent from the BIOS and sequentially sort the offsets and values to form a temporary structure. The baseboard management controller stores bytes of special values in a header of the temporary structure. One is a byte of a value corresponding to a mode in the BIOS and is referred to as A. The other one is a byte when a user sets the options and is referred to as B. The BIOS and baseboard management controller only need to perform logical processing according to such bytes to achieve option settings, synchronization, and switching.
At step S201, a machine is started.
The BMC is empty. A default option combination mode value is sent to the baseboard management controller by the BIOS. The structure of the baseboard management controller only generates a header, the header storing synchronized mode value A and value B which is 0 by default. When a user wants to switch a specific mode, A is modified. The BIOS carries out switching according to value A at next startup. Operation steps of specific options are fixed in mode A.
At step S202, an option and a configure value in the baseboard management controller is set by means of ipmi write command of a user.
At step S203, the configure value is read from the second combination structure of the baseboard management controller by the BIOS by means of ipmi read command. Determine a mode represented by the configure value. The configure value represents an invalid mode, a first valid mode and a second valid mode. The invalid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 0. The first valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 1. The second valid mode refers to the mode where the configure value of the second combination structure in the baseboard management controller is 2. Execute S204 in a case that the configure value is 0 or invalid. Execute S206 in a case that the configure value is 1. Execute S209 in a case that the configure value is 2.
At step S204, the configure value in the second combination structure is cleared by the BIOS. A configure value of the first combination structure is sent to the baseboard management controller by means of an IPMI. The configure value of the first combination structure is set as 1.
At step S205, continue the startup, wait to restart the machine next time, and not set the configure value by the baseboard management controller.
At step S206, a first cyclic redundancy check code in the first combination structure is calculated by the BIOS. The baseboard management controller is triggered to calculate a second cyclic redundancy check code of an option in the second combination structure. Determine whether the first cyclic redundancy check code is the same as the second cyclic redundancy check code by the BIOS. Execute S205 under the condition that the first cyclic redundancy check code is the same as the second cyclic redundancy check code. Execute S207 under the condition that the first cyclic redundancy check code is different from the second cyclic redundancy check code.
At step S207, write the option in the second combination structure in the baseboard management controller to a BIOS Nvram by the BIOS by means of ipmi read command, and set flag bit B of the configure value as 0x0.
At step S208, restart the machine automatically after setting is completed, and not set the configure value by the baseboard management controller.
At step S209, the option of the first combination structure is restored to a default value by the BIOS. The BIOS set flag bit B of the configure value as 0x0, and carry out re-startup after setting is completed.
Innovation points of some embodiments of the disclosure are as follows: firstly, the modes of different option combinations are numbered by the BIOS. Secondly, a specific option combination structure is created in the BIOS, the combination structure has a header and stores numbers of the modes. Each option corresponds to an offset and a value. Moreover, the BIOS stores a default value corresponding to each option. The baseboard management controller is not required to consider how an option in the BIOS option structure is composed, and only required to receive offsets and values sent from the BIOS and sequentially sort the offsets and values to form a temporary structure. The baseboard management controller stores bit of special values in a header of the temporary structure. One is bit of a value corresponding to a mode in the BIOS and is referred to as A. The other one is bit when a user sets the options and is referred to as B. The BIOS and baseboard management controller only need to perform logical processing according to such bit to achieve option settings, synchronization, and switching.
According to the storage medium for setting options of a BIOS provided in some embodiments of the disclosure, the options occupy a small storage space of the BMC, such that cost of a memory is saved. The BIOS carries out logical processing by means of some flag bits, such that the options are synchronized and set between the different combination modes are implemented. Moreover, when out-of-band modification is performed on the options, it is only required to set offset and value corresponding to an option in the BMC on a command. Non-research-and-development personnel only need to have a corresponding offset corresponding table to modify the options, such that simpleness is achieved and operation is easy. Finally, load default operation on the options is simple, and only one-bit modification is required.
Some embodiments of the disclosure further provide a storage medium, that is, a computer storage medium, a non-volatile computer-readable storage medium. For instance, the storage medium includes a memory storing a computer program. The above computer program can be executed by a processor to complete steps of the aforementioned method. The non-volatile computer-readable storage medium may be a FRAM, an ROM, a PROM, an EPROM, an EEPROM, a Flash Memory, a magnetic surface memory, an optical disc, a CD-ROM or other memories.
Those of ordinary skill in the art can understand that all or some steps of the above method embodiments can be completed by related hardware instructed by the program. The aforementioned program can be stored in a computer-readable storage medium. The program executes the steps of the above method embodiments when executed. The aforementioned storage medium includes a mobile storage device, an ROM, an RAM, a magnetic disc or an optical disc and other media that can store program code. Alternatively, when the above integrated unit in the disclosure is implemented in a form of a software functional module and sold or used as an independent product, the integrated unit can also be stored in a computer-readable storage medium. On the basis of such understanding, methods of some embodiments of the disclosure in essence or the part contributing to the prior art can be embodied in a form of software products. The computer software products are stored in a storage medium and include several instructions for causing an electronic device (which may be a personal computer, a server or a network device, etc.) to execute all or part of the method in each embodiment of the disclosure. The aforementioned storage medium includes a mobile storage device, an ROM, an RAM, a magnetic disc or an optical disc and other media that can store program code.
For the description of the related parts in the processing device and storage medium for setting options of a BIOS provided in some embodiments of the disclosure, reference can be made to the detailed description of the corresponding parts in the method for setting options of a BIOS provided in some embodiments of the disclosure, which will not be repeated herein.
It should be noted that relational terms such as first and second herein are merely used to distinguish one entity or operation from another entity or operation without certainly requiring or implying any such actual relation or order between such entities or operations. In addition, the term “include”, “comprise” or their any other variations is intended to cover a non-exclusive inclusion, such that inherent elements of a process, a method, an article or a device including a series of elements are included. Under the circumstance of no more limitations, an element limited by the phrase “comprising a . . . ” or “including a . . . ” does not exclude other same elements in a process, a method, an article or a device including the element. In addition, the parts of the above methods provided in some embodiments of the disclosure that have the same implementation principles with the corresponding methods in the prior art are not described in detail, so as to avoid repetition.
Particular embodiments of the disclosure are described above in combination with the drawings, but do not limit the scope of protection of the disclosure. Those skilled in the pertained field can make modifications or variations in other different forms on the basis of the above description. There are no need and no way to exhaust all embodiments. On the basis of the methods of the disclosure, various modifications or variations that can be made by those skilled in the art without creative labor still fall within the scope of protection of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210135046.9 | Feb 2022 | CN | national |
The present application is a National Stage Application of PCT International Application No. PCT/CN2022/138452 filed Dec. 12, 2022, which claims the benefit of priority to Chinese Patent Application No. 202210135046.9, filed with the China National Intellectual Property Administration on Feb. 11, 2022 and entitled “Method and system for setting options of BIOS, device and storage medium”, the disclosure of which is hereby incorporated by reference in its entirety. To the extent appropriate, a claim of priority is made to each of the above disclosed applications.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/138452 | 12/12/2022 | WO |
