Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers

Information

  • Patent Grant
  • 7975110
  • Patent Number
    7,975,110
  • Date Filed
    Monday, March 20, 2006
    20 years ago
  • Date Issued
    Tuesday, July 5, 2011
    15 years ago
Abstract
A servo controller for a disk drive controller comprising a storage device that stores communication information for a plurality of devices and a serial port controller located on the servo controller that communicates with the storage device, that receives a request to communicate with one of the plurality of devices, and that allows communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol.
Description
FIELD

The present invention relates generally to storage systems, and more particularly to disk drive servo controllers.


BACKGROUND

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.


Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and disk drives. In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.


The main memory is typically smaller than disk drives and may be volatile. Programming data is often stored on the disk drive and read into main memory as needed. The disk drives are coupled to the host system via a disk controller that handles complex details of interfacing the disk drives to the host system. Communications between the host system and the disk controller is usually provided using one of a variety of standard I/O bus interfaces.


Typically, a disk drive includes one or more magnetic disks. Each disk (or platter) typically has a number of concentric rings or tracks (platter) on which data is stored. The tracks themselves may be divided into sectors, which are the smallest accessible data units. A positioning head above the appropriate track accesses a sector. An index pulse typically identifies the first sector of a track. The start of each sector is identified with a sector pulse. Typically, the disk drive waits until a desired sector rotates beneath the head before proceeding with a read or write operation. Data is accessed serially, one bit at a time and typically, each disk has its own read/write head.



FIG. 1 shows a disk drive system 100 with platters 101A and 101B, an actuator 102 and read/write head 103. Typically, multiple platters/read and write heads are used. Platters 101A-101B have assigned tracks for storing system information, servo data and user data.


The disk drive is connected to the disk controller that performs numerous functions, for example, converting digital data to analog head signals, disk formatting, error checking and fixing, logical to physical address mapping and data buffering. To perform the various functions for transferring data, the disk controller includes numerous components.


To access data from a disk drive (or to write data), the host system must know where to read (or write data to) the data from the disk drive. A driver typically performs this task. Once the disk drive address is known, the address is translated to cylinder, head and sector based on platter geometry and sent to the disk controller. Logic on the hard disk looks at the number of cylinders requested. Servo controller firmware instructs motor control hardware to move read/write heads 103 to the appropriate track. When the head is in the correct position, it reads the data from the correct track.


Typically, read and write head 103 has a write core for writing data in a data region, and a read core for magnetically detecting the data written in the data region of a track and a servo pattern recorded on a servo region.


A servo system 104 detects the position of head 103 on platter 101A according to a phase of a servo pattern detected by the read core of head 103. Servo system 104 then moves head 103 to the target position.


Servo system 104 servo-controls head 103 while receiving feedback for a detected position obtained from a servo pattern so that any positional error between the detected position and the target position is negated.


Typically, a servo controller in system 104 communicates with various serial port programmable devices coupled via a serial port interface. The serial port interface enables transmission of commands and configuration data. One such device is shown in FIG. 3, as the “read channel device 303”. An example of such a product is “88C7500 Integrated Read channel” device sold by Marvell Semiconductor Inc®.


There is no standard for these various serial port devices to communicate with the servo controller. For example, length of address and length of data fields may vary from one device to the next. Hence, a single serial port connection is not typically used for plural devices having different protocols. Conventional techniques require a separate controller for each device. This is commercially undesirable because it adds costs and extra logic on a chip.


Therefore, what is desired is an efficient system that allows an embedded disk controller to communicate with plural devices through a single serial port controller interface.


SUMMARY

A servo controller for a disk drive controller comprises a storage device that stores communication information for a plurality of devices. A serial port controller located on the servo controller communicates with the storage device, receives a request to communicate with one of the plurality of devices, and allows communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol.


In other features of the invention, the storage device includes at least one register. Logic that enables the plurality of devices to receive at least one of a write request and a read request. The serial port controller arbitrates between a plurality of the requests to communicate. The serial port controller communicates with at least one client device and receives the plurality of the requests to communicate from the at least one client device. The communication information includes at least one of address information, write data information, and read data information. The serial port controller outputs an enabling signal to the one of the plurality of devices according to the communication information and the request. A routing device communicates with the serial port controller, the storage device, and the plurality of devices and allows data to flow at least one of to and from the plurality of devices. At least one of the serial port controller and the storage device are located on one of an integrated circuit (IC) and a system on a chip (SOC) with the servo controller.


A method for communicating with serial port devices with a servo controller for a disk drive controller comprises storing communication information for a plurality of devices in a storage device, communicating with the storage device at serial port controller located on the servo controller, receiving a request to communicate with one of the plurality of devices at the serial port controller, and allowing communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol.


In other features of the invention, the storage device includes at least one register. The method further comprises enabling the plurality of devices to receive at least one of a write request and a read request. The serial port controller arbitrates between a plurality of the requests to communicate. The serial port controller communicates with at least one client device and receives the plurality of the requests to communicate from the at least one client device. The communication information includes at least one of address information, write data information, and read data information. The serial port controller outputs an enabling signal to the one of the plurality of devices according to the communication information and the request. The method further comprises communicating with the serial port controller, the storage device, and the plurality of devices with a routing device, and allowing data to flow at least one of to and from the plurality of devices with the routing device.


A servo controller for a disk drive controller comprises storage means for storing communication information for a plurality of devices and serial port control means located on the servo controller for communicating with the storage means, for receiving a request to communicate with one of the plurality of devices, and for allowing communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol.


In other features of the invention, the storage means includes at least one register. The servo controller further comprises logic means for enabling the plurality of devices to receive at least one of a write request and a read request. The serial port controller arbitrates between a plurality of the requests to communicate. The serial port control means communicates with at least one client device and receives the plurality of the requests to communicate from the at least one client device. The communication information includes at least one of address information, write data information, and read data information. The serial port control means outputs an enabling signal to the one of the plurality of devices according to the communication information and the request. The servo controller further comprises routing means for communicating with the serial port control means, the storage means, and the plurality of devices and for allowing data to flow at least one of to and from the plurality of devices. At least one of the serial port control means and the storage means are located on one of an integrated circuit (IC) and a system on a chip (SOC) with the servo controller.


In still other features, the systems and methods described above are implemented by a computer program executed by one or more processors. The computer program can reside on a computer readable medium such as but not limited to memory, non-volatile data storage and/or other suitable tangible storage mediums.


Further areas of applicability of the present disclosure will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the disclosure, are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.





BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features and other features of the present invention will now be described. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures:



FIG. 1 shows a block diagram of a disk drive;



FIG. 2 is a block diagram of an embedded disk controller system, according to one aspect of the present invention;



FIG. 3 is a block diagram showing the various components of the FIG. 3 system and a two-platter, four-head disk drive, according to one aspect of the present invention;



FIG. 4 is a block diagram of a servo controller, according to one aspect of the present invention;



FIG. 5 is a schematic of a serial port controller, according to one aspect of the present invention;



FIGS. 6A and 6B provides examples of timing diagrams as used by the serial port controller of FIG. 5 during a write and read phase, respectively, according to one aspect of the present invention; and



FIG. 7 is a flow diagram of executable steps for a state machine used by the serial port controller, according to one aspect of the present invention.





DRAWINGS

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way.


DETAILED DESCRIPTION

The following description is merely exemplary in nature and is in no way intended to limit the disclosure, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module, circuit and/or device refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure.


To facilitate an understanding of the preferred embodiment, the general architecture and operation of an embedded disk controller will be described initially. The specific architecture and operation of the preferred embodiment will then be described.



FIG. 2 shows a block diagram of an embedded disk controller system 200 according to one aspect of the present invention. System 200 may be an application specific integrated circuit (“ASIC”).


System 200 includes a microprocessor (“MP) 201 that performs various functions described below. MP 201 may be a Pentium® Class processor designed and developed by Intel Corporation® or an ARM processor. MP 201 is operationally coupled to various system 200 components via buses 222 and 223. Bus 222 may be an Advance High performance (AHB) bus as specified by ARM Inc. Bus 223 may an Advance Peripheral Bus (“APB”) as specified by ARM Inc. The specifications for AHB and APB are incorporated herein by reference in their entirety.


System 200 is also provided with a random access memory (RAM) or static RAM (SRAM) 202 that stores programs and instructions, which allows MP 201 to execute computer instructions. MP 201 may execute code instructions (also referred to as “firmware”) out of RAM 202.


System 200 is also provided with read only memory (ROM) 203 that stores invariant instructions, including basic input/output instructions.


System 200 is also provided with a digital signal processor (“DSP”) 206 that controls and monitors various servo functions through DSP interface module (“DSPIM”) 208 and servo controller interface 210 operationally coupled to a servo controller (“SC”) 211.


DSPIM 208 interfaces DSP 206 with MP 201 and allows DSP 206 to update a tightly coupled memory module (TCM) 205 (also referred to as “memory module” 205) with servo related information. MP 201 can access TCM 205 via DSPIM 208.


Servo controller interface (“SCI”) 210 includes an APB interface 213 that allows SCI 210 to interface with APB bus 223 and allows SC 211 to interface with MP 201 and DSP 206.


SCI 210 also includes DSPAHB interface 214 that allows access to DSPAHB bus 209. SCI 210 is provided with a digital to analog and analog to digital converter 212 that converts data from analog to digital domain and vice-versa. Analog data 220 enters module 212 and leaves as analog data 220A to a servo device 221.


SC 211 has a read channel device (RDC) serial port 217, a motor control (“SVC”) serial port 218 for a “combo” motor controller device, a head integrated circuit (HDIC) serial port 219 and a servo data (“SVD”) interface 216 for communicating with various devices.



FIG. 3 shows a block diagram with disk 100 coupled to system 200, according to one aspect of the present invention. FIG. 3 shows a read channel device 303 that receives signals from a pre-amplifier 302 (also known as head integrated circuit (HDIC)) coupled to disk 100. One example of a read channel device 303 is manufactured by Marvell Semiconductor Inc.®, Part Number 88C7500, while pre-amplifier 302 may be a Texas instrument, Part Number SR1790. Pre-amplifier 302 is also operationally coupled to SC 211. Servo data (“SVD”) 305 is sent to SC 211.


A motor controller 307 (also referred to as device 307), (for example, a motor controller manufactured by Texas Instrument®, Part Number SH6764) sends control signals 308 to control actuator movement using motor 307A. It is noteworthy that spindle 101C is controlled by a spindle motor (not shown) for rotating platters 101A and 101B. SC 211 sends plural signals to motor controller 307 including clock, data and “enable” signals to motor controller 307 (for example, SV_SEN, SV_SCLK and SV_SDAT).


SC 211 is also operationally coupled to a piezo controller 509 that allows communication with a piezo device (not shown). One such piezo controller is sold by Rolm Electronics®, Part Number BD6801 FV. SC 211 sends clock, data and enable signals to controller 509 (for example, SV_SEN, SV_SCLK and SV_SDAT).



FIG. 4 shows a block diagram of SC 211, according to one aspect of the present invention.



FIG. 4 shows SC 211 with a serial port controller 404 for controlling various serial ports 405-407.


SC 211 also has a servo-timing controller (“STC”) 401 that automatically adjusts the time base when a head change occurs. Servo controller 211 includes an interrupt controller 411 that can generate an interrupt to DSP 206 and MP 201. Interrupts may be generated when a servo field is found (or not found) and for other reasons. SC 211 includes a servo monitoring port 412 that monitors various signals to SC 211.


SC 211 uses a pulse width modulation unit (“PWM”) 413 for supporting control of motor 307A PWM, and a spindle motor PWM 409 and a piezo PWM 408.


MP 201 and/or DSP 206 use read channel device 303 for transferring configuration data and operational commands through SC 211 (via read channel serial port interface 406).



FIG. 5 shows a block diagram of serial port controller 404, according to one aspect of the present invention. The example only shows how serial port controller 404 allows communication between system 200 and motor controller 307 and piezo controller 509. It is noteworthy that the invention is not limited to just these two or any particular number of devices.


Controller 404 includes a state machine 404A that has access to piezo controller 509 and device 307 information in registers 501 and 503 (that includes controller 509 and 307 protocol information), for MP 201 (referred to as Client 1 in FIG. 5 for illustration purposes only). State machine 404A can also access controller 509 and device 307 information in registers 502 and 504 for DSP 206 (referred to as Client 2 in FIG. 5 for illustration purposes only). Typically information in registers 501-504 includes address fields for each device (509 or 307 in this example), length of the data fields and timing control information (for example, if data from a certain device is captured on the rising or falling edge of a clock signal,) and setup and hold time data for the active edge of a clock signal.


Controller 404 also includes various registers, for example, registers 515-517 for storing address, write data and read data for controller requested by client 1, and registers 518-520 for storing address, write data and read data for a device requested by client 2. Information from register 515-520 is sent to a router 521 that allows MP 201 or DSP 206 to communicate with controller 509 or device 307.


Request to Write: The following example shows how MP 201 (or any other component) can write data to a device (in this example, controller 509 or device 307). MP 201 sends a request 506 that is received by state machine 404A. MP 201 then adds the address and data in register 515 and 516. Based on the information in registers 501-504, state machine 404A determines the identity of the device to which MP 201 wants to write. State machine 404A then sets up the device by generating signal 508 or 513 that enables controller 509 or device 307, respectively. Thereafter, data is written to controller 509 or device 307.



FIG. 6A provides a timing diagram showing the relationship between signals 513, 512 and 511 to write data to device 307. Signal 512 is a serial clock that is used for synchronizing data transfer between a client and the device.


Request to Read: The following example shows how DSP 206 (or any other component) can read data from a device (in this example, controller 509 or device 307). A request 507 is received by state machine 404A from DSP 201. DSP 201 also provides an address to register 518. Based on the information in registers 501 and 502, state machine 404A determines the identity of the device to read data. State machine 404A then sets up signal 508 or 513 to read data from controller 509 or device 307.



FIG. 6B provides a timing diagram showing the relationship between signals 508, 512 and 511 to read data from controller 509.



FIG. 7 is a flow diagram showing executable process steps used by state machine 404A, according to one aspect of the present invention.


In step S700, state machine 404A is in an idle state. When it receives requests from various clients (MP 201 and DSP 206), state machine 404A enters an arbitration mode in step S701. One of the clients wins arbitration and is then allowed to communicate to an external device, 509 or device 307.


In step S702, state machine 404A reads programmed information about a device (for example, controller 509 or device 307) from registers 501-504.


In step S703, state machine 404A transmits the appropriate device address to the client who won arbitration in step S701.


In step S704, state machine 404A, transmits data via router 521, to controller 509 or device 307, for a write mode. Thereafter, the process returns to step S700.


In step S705, state machine 404A, collects data via router 521, from controller 509 or device 307, for a read mode and the data is sent to register 520 for later recovery by the requesting client. Thereafter, the process returns to step S700.


In one aspect of the present invention, the servo controller with a single state machine can communicate with multiple serial port devices, and each device may have a different protocol.


Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.

Claims
  • 1. A servo controller for a disk drive controller, comprising: a storage device that stores communication information for a plurality of devices associated with servo control; anda serial port controller located on the servo controller that communicates with the storage device, that receives a request to communicate with one of the plurality of devices via a respective one of a plurality of serial ports, and that allows communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol.
  • 2. The servo controller of claim 1 wherein the storage device includes at least one register.
  • 3. The servo controller of claim 1 further comprising logic that enables the plurality of devices to receive at least one of a write request and a read request.
  • 4. The servo controller of claim 1 wherein the serial port controller arbitrates between a plurality of the requests to communicate.
  • 5. The servo controller of claim 4 wherein the serial port controller communicates with at least one client device and receives the plurality of the requests to communicate from the at least one client device.
  • 6. The servo controller of claim 1 wherein the communication information includes at least one of address information, write data information, and read data information.
  • 7. The servo controller of claim 1, wherein the serial port controller outputs an enabling signal to the one of the plurality of devices according to the communication information and the request.
  • 8. The servo controller of claim 1, further comprising: a routing device that communicates with the serial port controller, the storage device, and the plurality of devices and that allows data to flow at least one of to and from the plurality of devices.
  • 9. The servo controller of claim 1 wherein at least one of the serial port controller and the storage device are located on one of an integrated circuit (IC) and a system on a chip (SOC) with the servo controller.
  • 10. A method for communicating with serial port devices with a servo controller for a disk drive controller, comprising: storing communication information for a plurality of devices associated with servo control in a storage device;communicating with the storage device at a serial port controller located on the servo controller;receiving a request to communicate with one of the plurality of devices via a respective one of a plurality of serial ports at the serial port controller; andallowing communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol.
  • 11. The method of claim 10 wherein the storage device includes at least one register.
  • 12. The method of claim 10 further comprising enabling the plurality of devices to receive at least one of a write request and a read request.
  • 13. The method of claim 10 wherein the serial port controller arbitrates between a plurality of the requests to communicate.
  • 14. The method of claim 13 wherein the serial port controller communicates with at least one client device and receives the plurality of the requests to communicate from the at least one client device.
  • 15. The method of claim 10 wherein the communication information includes at least one of address information, write data information, and read data information.
  • 16. The method of claim 10 wherein the serial port controller outputs an enabling signal to the one of the plurality of devices according to the communication information and the request.
  • 17. The method of claim 10 further comprising: communicating with the serial port controller, the storage device, and the plurality of devices with a routing device; andallowing data to flow at least one of to and from the plurality of devices with the routing device.
  • 18. A servo controller for a disk drive controller, comprising: storage means for storing communication information for a plurality of devices associated with servo control; andserial port control means located on the servo controller for communicating with the storage means, for receiving a request to communicate with one of the plurality of devices via a respective one of a plurality of serial ports, and for allowing communication between at least one processor and the one of the plurality of devices according to the stored communication information and the request, wherein each of the plurality of devices uses a different protocol.
  • 19. The servo controller of claim 18 wherein the storage means includes at least one register.
  • 20. The servo controller of claim 18 further comprising logic means for enabling the plurality of devices to receive at least one of a write request and a read request.
  • 21. The servo controller of claim 18 wherein the serial port controller arbitrates between a plurality of the requests to communicate.
  • 22. The servo controller of claim 21 wherein the serial port control means communicates with at least one client device and receives the plurality of the requests to communicate from the at least one client device.
  • 23. The servo controller of claim 18 wherein the communication information includes at least one of address information, write data information, and read data information.
  • 24. The servo controller of claim 18, wherein the serial port control means outputs an enabling signal to the one of the plurality of devices according to the communication information and the request.
  • 25. The servo controller of claim 18, further comprising: routing means for communicating with the serial port control means, the storage means, and the plurality of devices and for allowing data to flow at least one of to and from the plurality of devices.
  • 26. The servo controller of claim 18 wherein at least one of the serial port control means and the storage means are located on one of an integrated circuit (IC) and a system on a chip (SOC) with the servo controller.
CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 10/385,039, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,039,771). This application also relates to the subject matter of U.S. patent application Ser. No. 10/384,992, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,492,545); U.S. patent application Ser. No. 10/385,022, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,080,188); U.S. patent application Ser. No. 10/384,991, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,457,903); U.S. patent application Ser. No. 10/385,042, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,099,963); U.S. patent application Ser. No. 10/385,405, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,064,915); and U.S. patent application Ser. No. 10/385,056, filed on Mar. 10, 2003 (now U.S. Pat. No. 7,219,182). The disclosures of the above applications are incorporated herein by reference.

US Referenced Citations (258)
Number Name Date Kind
3800281 Devore et al. Mar 1974 A
3988716 Fletcher et al. Oct 1976 A
4001883 Strout et al. Jan 1977 A
4016368 Apple, Jr. Apr 1977 A
4050097 Miu et al. Sep 1977 A
4080649 Calle et al. Mar 1978 A
4144583 Lawson et al. Mar 1979 A
4156867 Bench et al. May 1979 A
4225960 Masters Sep 1980 A
4275457 Leighou et al. Jun 1981 A
4390969 Hayes Jun 1983 A
4451898 Palermo et al. May 1984 A
4486750 Aoki Dec 1984 A
4486827 Shima et al. Dec 1984 A
4500926 Yoshimaru et al. Feb 1985 A
4587609 Boudreau et al. May 1986 A
4603382 Cole et al. Jul 1986 A
4625321 Pechar et al. Nov 1986 A
4667286 Young et al. May 1987 A
4777635 Glover Oct 1988 A
4805046 Kuroki et al. Feb 1989 A
4807116 Katzman et al. Feb 1989 A
4807253 Hagenauer et al. Feb 1989 A
4809091 Miyazawa et al. Feb 1989 A
4811282 Masina Mar 1989 A
4812769 Agoston Mar 1989 A
4860333 Bitzinger et al. Aug 1989 A
4866606 Kopetz Sep 1989 A
4881232 Sako et al. Nov 1989 A
4920535 Watanabe et al. Apr 1990 A
4949342 Shimbo et al. Aug 1990 A
4970418 Masterson Nov 1990 A
4972417 Sako et al. Nov 1990 A
4975915 Sako et al. Dec 1990 A
4989190 Kuroe et al. Jan 1991 A
5014186 Chisholm May 1991 A
5023612 Liu Jun 1991 A
5027357 Yu et al. Jun 1991 A
5050013 Holsinger Sep 1991 A
5051998 Murai et al. Sep 1991 A
5068755 Hamilton et al. Nov 1991 A
5068857 Yoshida Nov 1991 A
5072420 Conley et al. Dec 1991 A
5088093 Storch et al. Feb 1992 A
5109500 Iseki et al. Apr 1992 A
5117442 Hall May 1992 A
5127098 Rosenthal et al. Jun 1992 A
5133062 Joshi et al. Jul 1992 A
5136592 Weng Aug 1992 A
5146585 Smith, III Sep 1992 A
5157669 Yu et al. Oct 1992 A
5162954 Miller et al. Nov 1992 A
5179704 Jibbe et al. Jan 1993 A
5193197 Thacker Mar 1993 A
5204859 Paesler et al. Apr 1993 A
5218564 Haines et al. Jun 1993 A
5220569 Hartness Jun 1993 A
5237593 Fisher et al. Aug 1993 A
5243471 Shinn Sep 1993 A
5249271 Hopkinson et al. Sep 1993 A
5257143 Zangenehpour Oct 1993 A
5261081 White et al. Nov 1993 A
5271018 Chan Dec 1993 A
5274509 Buch Dec 1993 A
5276564 Hessing et al. Jan 1994 A
5276662 Shaver, Jr. et al. Jan 1994 A
5276807 Kodama et al. Jan 1994 A
5280488 Glover et al. Jan 1994 A
5285327 Hetzler Feb 1994 A
5285451 Henson et al. Feb 1994 A
5301333 Lee Apr 1994 A
5307216 Cook et al. Apr 1994 A
5315708 Eidler et al. May 1994 A
5317713 Glassburn May 1994 A
5329630 Baldwin Jul 1994 A
5339443 Lockwood Aug 1994 A
5349667 Kaneko Sep 1994 A
5361266 Kodama et al. Nov 1994 A
5361267 Godiwala et al. Nov 1994 A
5375248 Lemay et al. Dec 1994 A
5408644 Schneider et al. Apr 1995 A
5408673 Childers et al. Apr 1995 A
5420984 Good et al. May 1995 A
5428627 Gupta Jun 1995 A
5440751 Santeler et al. Aug 1995 A
5465343 Henson et al. Nov 1995 A
5487170 Bass et al. Jan 1996 A
5488688 Gonzales et al. Jan 1996 A
5491701 Zook Feb 1996 A
5500848 Best et al. Mar 1996 A
5506989 Boldt et al. Apr 1996 A
5507005 Kojima et al. Apr 1996 A
5519837 Tran May 1996 A
5523903 Hetzler et al. Jun 1996 A
5544180 Gupta Aug 1996 A
5544346 Amini Aug 1996 A
5546545 Rich Aug 1996 A
5546548 Chen et al. Aug 1996 A
5557764 Stewart et al. Sep 1996 A
5563896 Nakaguchi Oct 1996 A
5568606 Dobbek Oct 1996 A
5572148 Lytle et al. Nov 1996 A
5574867 Khaira Nov 1996 A
5581715 Verinsky et al. Dec 1996 A
5583999 Sato et al. Dec 1996 A
5590380 Yamada et al. Dec 1996 A
5592404 Zook Jan 1997 A
5600662 Zook Feb 1997 A
5602857 Zook et al. Feb 1997 A
5603035 Erramoun et al. Feb 1997 A
5615190 Best et al. Mar 1997 A
5623672 Popat Apr 1997 A
5626949 Blauer et al. May 1997 A
5627695 Prins et al. May 1997 A
5640602 Takase Jun 1997 A
5649230 Lentz Jul 1997 A
5659759 Yamada Aug 1997 A
5664121 Cerauskis Sep 1997 A
5689656 Baden et al. Nov 1997 A
5691994 Acosta et al. Nov 1997 A
5692135 Alvarez, II et al. Nov 1997 A
5692165 Jeddeloh et al. Nov 1997 A
5692516 Kaneko et al. Dec 1997 A
5719516 Sharpe-Geisler Feb 1998 A
5729511 Schell et al. Mar 1998 A
5729718 Au Mar 1998 A
5734848 Gates et al. Mar 1998 A
5740466 Geldman et al. Apr 1998 A
5745793 Atsatt et al. Apr 1998 A
5754759 Clarke et al. May 1998 A
5758188 Applebaum et al. May 1998 A
5768044 Hetzler et al. Jun 1998 A
5784569 Miller et al. Jul 1998 A
5787483 Jam et al. Jul 1998 A
5794073 Ramakrishnan et al. Aug 1998 A
5801998 Choi Sep 1998 A
5805370 Lee Sep 1998 A
5818886 Castle Oct 1998 A
5822142 Hicken Oct 1998 A
5826093 Assouad et al. Oct 1998 A
5831922 Choi Nov 1998 A
5835299 Lee et al. Nov 1998 A
5835930 Dobbek Nov 1998 A
5841722 Willenz Nov 1998 A
5844844 Bauer et al. Dec 1998 A
5850422 Chen Dec 1998 A
5854918 Baxter Dec 1998 A
5890207 Sne et al. Mar 1999 A
5890210 Ishii et al. Mar 1999 A
5907717 Ellis May 1999 A
5912906 Wu et al. Jun 1999 A
5925135 Trieu et al. Jul 1999 A
5928367 Nelson et al. Jul 1999 A
5937435 Dobbek et al. Aug 1999 A
5950223 Chiang et al. Sep 1999 A
5968180 Baco Oct 1999 A
5983293 Murakami Nov 1999 A
5991911 Zook Nov 1999 A
6021458 Jayakumar et al. Feb 2000 A
6029226 Ellis et al. Feb 2000 A
6029250 Keeth Feb 2000 A
6041417 Hammond et al. Mar 2000 A
6065053 Nouri et al. May 2000 A
6067206 Hull et al. May 2000 A
6070200 Gates et al. May 2000 A
6078447 Sim Jun 2000 A
6081397 Belser Jun 2000 A
6081849 Born et al. Jun 2000 A
6081867 Cox Jun 2000 A
6092231 Sze Jul 2000 A
6094320 Ahn Jul 2000 A
6105119 Kerr et al. Aug 2000 A
6108150 Lee Aug 2000 A
6115778 Miyake et al. Sep 2000 A
6124994 Malone, Sr. Sep 2000 A
6128153 Hasegawa et al. Oct 2000 A
6134063 Weston-Lewis et al. Oct 2000 A
6134676 VanHuben et al. Oct 2000 A
6157984 Fisher et al. Dec 2000 A
6178486 Gill et al. Jan 2001 B1
6192499 Yang Feb 2001 B1
6201655 Watanabe et al. Mar 2001 B1
6223303 Billings et al. Apr 2001 B1
6279089 Schibilla et al. Aug 2001 B1
6285632 Ueki Sep 2001 B1
6297926 Ahn Oct 2001 B1
6314480 Nemazie et al. Nov 2001 B1
6330626 Dennin et al. Dec 2001 B1
6381659 Proch et al. Apr 2002 B2
6401149 Dennin et al. Jun 2002 B1
6401154 Chiu et al. Jun 2002 B1
6421760 McDonald et al. Jul 2002 B1
6470461 Pinvidic et al. Oct 2002 B1
6487631 Dickinson et al. Nov 2002 B2
6490635 Holmes Dec 2002 B1
6493171 Enokida et al. Dec 2002 B2
6496517 Gehman et al. Dec 2002 B1
6515813 Kitazaki et al. Feb 2003 B2
6530000 Krantz et al. Mar 2003 B1
6574676 Megiddo Jun 2003 B1
6574699 Dobbek Jun 2003 B1
6583943 Malone Jun 2003 B2
6594721 Sakarda et al. Jul 2003 B1
6618780 Popat Sep 2003 B1
6629204 Tanaka et al. Sep 2003 B2
6651126 Cantrell et al. Nov 2003 B1
6662253 Gary et al. Dec 2003 B1
6662313 Swanson et al. Dec 2003 B1
6662334 Stenfort Dec 2003 B1
6693462 Wang et al. Feb 2004 B1
6694398 Zhao et al. Feb 2004 B1
6711643 Park et al. Mar 2004 B2
6714373 Sasaki Mar 2004 B1
6721828 Verinsky et al. Apr 2004 B2
6728054 Chng et al. Apr 2004 B2
6728814 Leinen Apr 2004 B2
6742060 Poisner et al. May 2004 B2
6742065 Suh May 2004 B1
6765736 Ko et al. Jul 2004 B2
6765744 Gomez et al. Jul 2004 B2
6772258 Poisner et al. Aug 2004 B2
6807595 Khan et al. Oct 2004 B2
6826650 Krantz et al. Nov 2004 B1
6842819 Smith et al. Jan 2005 B2
6880030 Brenner et al. Apr 2005 B2
6895500 Rothberg May 2005 B1
6917997 Bhagat Jul 2005 B2
6924953 Fish et al. Aug 2005 B2
6944703 Okaue et al. Sep 2005 B2
6947233 Toda Sep 2005 B2
6950258 Takaishi Sep 2005 B2
6952749 Kim Oct 2005 B2
6963462 Satoh Nov 2005 B2
7054236 Kawano May 2006 B2
7064915 Spaur et al. Jun 2006 B1
7080188 Byers et al. Jul 2006 B2
7099963 Byers et al. Aug 2006 B2
7174401 Stuber et al. Feb 2007 B2
7219182 Byers et al. May 2007 B2
20010043424 Nguyen Nov 2001 A1
20010044873 Wilson et al. Nov 2001 A1
20020080698 Turner et al. Jun 2002 A1
20020087773 Poisner et al. Jul 2002 A1
20020087931 Jaber Jul 2002 A1
20020120815 Zahavi et al. Aug 2002 A1
20020124132 Haines et al. Sep 2002 A1
20020199076 Fujii Dec 2002 A1
20030037225 Deng et al. Feb 2003 A1
20030070030 Smith et al. Apr 2003 A1
20030081479 Matsumoto et al. May 2003 A1
20030084269 Drysdale et al. May 2003 A1
20030117909 Kawano Jun 2003 A1
20030204655 Schmisseur et al. Oct 2003 A1
20040019831 Gergen et al. Jan 2004 A1
20040093538 Hester et al. May 2004 A1
20040199695 Purdham et al. Oct 2004 A1
20060129704 Byers et al. Jun 2006 A1
20070226392 Byers et al. Sep 2007 A1
Foreign Referenced Citations (8)
Number Date Country
0528273 Feb 1993 EP
0622726 Nov 1994 EP
0718827 Jun 1996 EP
2285166 Jun 1995 GB
63-292462 Nov 1988 JP
01-315071 Dec 1989 JP
03183067 Aug 1991 JP
9814861 Apr 1998 WO
Continuations (1)
Number Date Country
Parent 10385039 Mar 2003 US
Child 11384657 US