1. Field of Invention
The present invention relates to high-speed digital circuits, and more particularly, to high-speed time domain multiplexers with reduced inter-symbol interference.
2. Description of Related Art
High-speed multiplexers operating at several giga-bits-per-second (Gb/s) range are employed in order to exploit the high data transmission rate of today's communication systems.
System 100 comprises a first and a second bit stream denoted 1 and 3 respectively and a clock signal denoted 5. Circuit 100 further comprises a first and a second edge-triggered latch denoted 7A and 7D respectively, wherein both latches are clocked in phase when clock signal 5 transitions into a first polarity to simultaneously sample new input data from bit streams 1 and 3 respectively.
Moreover, two additional edge-triggered latches denoted 7B and 7E coupled to latches 7A and 7D respectively are clocked in phase when clock signal 5 then transitions into a second polarity opposite that of the first polarity to simultaneously sample output from latches 7A and 7D respectively. Subsequently, a fifth edge-triggered latch denoted 7C is clocked in phase when clock signal 5 once again transitions into the first polarity to sample the output of latch 7B.
Additionally,
In one instance of operation, select input signal 12 coupled to selector 9 provides a data selection (MUX) operation for selecting, respectively, input 8 when select input signal 12=1, and input 10 when select input signal 12=0.
Furthermore,
Conventional bit interleaving multiplexers such as illustrated in
Furthermore, the output voltage relies on the state of the present bits of the input bit streams, as well as on the state of previous bits. Therefore, the variability in voltage during the clock transition results in variation in the crossing points of the multiplexer output, and since the critical crossing points define the bit periods of the multiplexer output bit stream, such variability in voltage may cause the crossing points in the multiplexer output to move, which in turn creates timing jitter in the output bit stream of the multiplexer.
Accordingly, there is a need to design a high-speed time domain multiplexer with reduced inter-symbol interference.
The present invention provides a method and system for high-speed time domain multiplexers with reduced inter-symbol interference.
In one embodiment of the present invention, a first edge-triggered latch and a second edge-triggered latch each samples a first bit stream and a second bit stream respectively, wherein each latch samples its respective bit stream as the clock signal transitions into a first polarity.
Subsequently, a third edge-triggered latch and a fourth edge-triggered latch each samples the output of the first edge-triggered latch and the second edge-triggered latch respectively as the clock signal transitions into a second polarity opposite that of the first polarity. Additionally, a fifth edge-triggered latch samples the output of the third edge-triggered latch as the clock signal transitions back into the first polarity.
Moreover, output of the fourth and the fifth edge-triggered latches are coupled to two inputs of a selector, and the output of the selector is determined by a select input signal comprising the inverse value of the clock signal. The fourth and the fifth edge-triggered latches further comprise return-to-differential-zero latches designed to drive an input to a neutral state (a differential zero) in cases where its respective input bit stream is not chosen by the select input signal as the selector output.
In an alternate embodiment of the present invention, a first edge-triggered latch and a second edge-triggered latch each samples a first bit stream and a second bit stream respectively, wherein each latch samples its respective bit stream as the clock signal transitions into a first polarity.
Subsequently, a third edge-triggered latch samples the output of the first edge-triggered latch as the clock signal transitions into a second polarity opposite to the first polarity. Moreover, the output of the second edge-triggered latch and the output of the third edge-triggered latch are coupled to two inputs of a pre-selector, and the output of the pre-selector is selected by a first select input signal coupled to the clock signal.
Furthermore, the pre-selector drives one of the two outputs to a neutral state and passes one of the data input signals to the other output depending on the value of the select input signal. The two outputs of the pre-selector are coupled in turn to two inputs of a selector, the output of the selector is then determined by a second select input signal comprising a value inverse to that of the clock signal.
The accompanying drawings that are incorporated in and form a part of this specification illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention:
The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. In the following description, specific nomenclature is set forth to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the specific details may not be necessary to practice the present invention. Furthermore, various modifications to the embodiments will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features described herein.
Referring now to
System 300 further comprises a first and a second edge-triggered latch denoted 27A and 27D respectively, wherein both latches are clocked in phase when clock signal 25 transitions into a first polarity to simultaneously sample new input data from bit streams 21 and 23 respectively.
Moreover, two additional edge-triggered latches denoted 27B and 29B coupled to latches 27A and 27D respectively are clocked in phase when clock signal 25 transitions into a second polarity opposite to the first polarity to simultaneously sample outputs from latches 27A and 27D respectively. Subsequently, a fifth edge-triggered latch denoted 29A coupled to latch 27B is clocked in phase when clock signal 25 transitions back to the first polarity to sample the output of latch 27B.
Additionally,
In one instance of operation, select input signal 34 coupled to selector 31 provides a data selection (MUX) operation for selecting, respectively, input 30 when select input signal 34=1 and clock signal 25=0, and input 28 when select input signal 34=0 and clock signal 25=1.
Furthermore, edge-triggered latches 29A and 29B are return-to-differential-zero latches implemented with low loading capacitance circuits. In cases where the output of a return-to-differential-zero latch is not selected by selector 31 as output, the return-to-differential-zero latch operates to drive its input value to a neutral state before passing the neutralized value as its output. Conversely, in cases where the output of a return-to-differential-zero latch is to be selected by selector 31 as its output, the return-to-differential-zero latch passes its sampled input value unaltered to its output.
Element denoted 36 shown in
Although
Referring now to
The return-to-differential-zero latch shown in
Moreover, latch 400 comprises two selecting inputs denoted 37 and 39, wherein input 37 comprising a clock signal of the return-to-differential-zero latch such as signals 25 and 26 shown in
Furthermore, latch 400 operates in two modes: acquire and latch. Subsection 49 operates in the acquire mode, wherein the latch operates as a simple differential amplifier, transferring the data from the input signals 33 and 35 to the output signals denoted 45 and 47 respectively.
Conversely, subsection 51 operates in the latch mode, wherein the latch is internally disconnected from the input signals 33 and 35, and the output 45 and 47 are driven to a differential zero where the voltage level is midway between logic high and logic low levels.
Referencing now to
System 500 further comprises a first and a second edge-triggered latch denoted 59A and 59C respectively, wherein both latches are clocked in phase when clock signal 57 transitions into a first polarity to simultaneously sample new input data from bit streams 53 and 55 respectively.
Additionally, a third edge-triggered latch denoted 59B coupled to latch 59A is clocked in phase when clock signal 57 transitions into a second polarity opposite to the first polarity to sample the output of latch 59A.
Subsequently, a pre-selector denoted 61 acquires and samples input signals 52 and 54. Pre-selector 61 selects one of the two input signals as the output signal for a selector denoted 63 according to its select input signal 60 and passes the selected input signal unaltered while producing a differential zero in place of the unselected input signal.
Selector 63 then acquires and samples two output signals 56 and 58, and selects one signal from the two output signals according to a select input signal denoted 62 comprising a value inverse to that of clock signal 57. Selector 63 then produces an output bit stream denoted 65 that interleaves the bit streams 53 and 55.
In one instance of operation, select input signal 62 coupled to selector 63 provides a data selection (MUX) operation for selecting, respectively, input 58 when select input signal 62=1 and clock signal 57=0, and input 56 when select input signal 62=0 and clock signal 57=1.
Element denoted 64 shown in
Although
Referring now to
The pre-selector shown in
Pre-selector 600 further comprises two select input signals denoted 75 and 77, wherein signal 75 comprises the value of signal 60 shown in
In operation, when select signal 75 is high and signal 77 is low, pre-selector 600 passes input signals 67 and 69 to output signals 79 and 81 wherein output 79 comprising the value of output 56 sampled by selector 63 as shown in
Conversely, when select signal 75 is low and signal 77 is high, pre-selector 600 passes input signals 71 and 73 to output signals 83 and 85 wherein output 83 comprising the value of output 58 sampled by selector 63 as shown in
Referring now to
Moreover,
Referring now to
As shown in
Additionally, multiplexers such as shown in
Moreover,
In step 201, a first and a second latch driven by a common clock signal sample a first and a second bit stream respectively. Subsequently in step 203, the first and second bit streams are retimed and synchronized with the rising and falling edges of the clock signal respectively.
Step 205 determines the value of the clock, and if the clock signal is high, the first bit stream is propagated to an interleaved output bit stream in Step 207, while the second bit stream is neutralized to a differential zero state.
Conversely, if the clock is low, the second bit stream is propagated to an interleaved output bit stream in Step 207, while the first bit stream is neutralized to a differential zero state.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the arts to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.
For example, although only 2:1 multiplexers are illustrated, it is commonly understood by those skilled in the art that such multiplexers as described may be employed as building blocks to other multiplexers such as 4:1 multiplexers and 8:1 multiplexers.
Moreover, although
Additionally, numerical values 0 and 1 symbolize a logical low and a logical high respectively, and details such as delays lines 36 and 64 are implemented to suit parameters of a specific design and may be altered as desired for alternate designs.
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