Microelectromechanical systems (MEMS) include micro mechanical elements, actuators, and electronics. Micromechanical elements may be created using deposition, etching, and or other micromachining processes that etch away parts of substrates and/or deposited material layers or that add layers to form electrical and electromechanical devices. One type of MEMS device is called an interferometric modulator. An interferometric modulator may comprise a pair of conductive plates, one or both of which may be transparent and/or reflective in whole or part and capable of relative motion upon application of an appropriate electrical signal. One plate may comprise a stationary layer deposited on a substrate, the other plate may comprise a metallic membrane separated from the stationary layer by an air gap. Such devices have a wide range of applications, and it would be beneficial in the art to utilize and/or modify the characteristics of these types of devices so that their features can be exploited in improving existing products and creating new products that have not yet been developed.
The system, method, and devices of the invention each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this invention, its more prominent features will now be discussed briefly. After considering this discussion, and particularly after reading the section entitled “Detailed Description of Certain Embodiments” one will understand how the features of this invention provide advantages over other display devices.
In one embodiment, a method of actuating a MEMS display element is provided, wherein the MEMS display element comprises a portion of an array of MEMS display elements. The method includes writing display data to the MEMS display element with a potential difference of a first polarity during a first portion of a display write process, and re-writing the display data to the MEMS display element with a potential difference having a polarity opposite the first polarity during a second portion of the display write process. Subsequently, a first bias potential having the first polarity is applied to the MEMS display element during a third portion of the display write process and a second bias potential having the opposite polarity is applied to the MEMS display element during a fourth portion of the display write process.
In another embodiment, a method of maintaining a frame of display data on an array of MEMS display elements includes alternately applying approximately equal bias voltages of opposite polarities to the MEMS display elements for periods of time defined at least in part by the inverse of a rate at which frames of display data are received by a display system. Each period of time may be substantially equal to 1/(2f) or 1/(4f), wherein f is a defined frequency of frame refresh cycles.
In another embodiment, a method of writing frames of display data to an array of MEMS display elements at a rate of one frame per defined frame update period includes writing display data to the MEMS display elements, wherein the writing takes less than the frame update period and applying a series of bias potentials of alternating polarity to the MEMS display elements for the remainder of the frame update period.
Display devices are also provided. In one such embodiment, a MEMS display device is configured to display images at a frame update rate, the frame update rate defining a frame update period. The display device includes row and column driver circuitry configured to apply a polarity balanced sequence of bias voltages to substantially all columns of a MEMS display array for portions of at least one frame update period, wherein the portions are defined by a time remaining between completing a frame write process for a first frame, and beginning a frame write process for a next subsequent frame.
The following detailed description is directed to certain specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to the drawings wherein like parts are designated with like numerals throughout. As will be apparent from the following description, the invention may be implemented in any device that is configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or pictorial. More particularly, it is contemplated that the invention may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and/or displays, display of camera views (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry). MEMS devices of similar structure to those described herein can also be used in non-display applications such as in electronic switching devices.
One interferometric modulator display embodiment comprising an interferometric MEMS display element is illustrated in
The depicted portion of the pixel array in
The fixed layers 16a, 16b are electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more layers each of chromium and indium-tin-oxide onto a transparent substrate 20. The layers are patterned into parallel strips, and may form row electrodes in a display device as described further below. The movable layers 14a, 14b may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes 16a, 16b) deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. When the sacrificial material is etched away, the deformable metal layers are separated from the fixed metal layers by a defined air gap 19. A highly conductive and reflective material such as aluminum may be used for the deformable layers, and these strips may form column electrodes in a display device.
With no applied voltage, the cavity 19 remains between the layers 14a, 16a and the deformable layer is in a mechanically relaxed state as illustrated by the pixel 12a in
In one embodiment, the processor 21 is also configured to communicate with an array controller 22. In one embodiment, the array controller 22 includes a row driver circuit 24 and a column driver circuit 26 that provide signals to a pixel array 30. The cross section of the array illustrated in
In typical applications, a display frame may be created by asserting the set of column electrodes in accordance with the desired set of actuated pixels in the first row. A row pulse is then applied to the row 1 electrode, actuating the pixels corresponding to the asserted column lines. The asserted set of column electrodes is then changed to correspond to the desired set of actuated pixels in the second row. A pulse is then applied to the row 2 electrode, actuating the appropriate pixels in row 2 in accordance with the asserted column electrodes. The row 1 pixels are unaffected by the row 2 pulse, and remain in the state they were set to during the row 1 pulse. This may be repeated for the entire series of rows in a sequential fashion to produce the frame. Generally, the frames are refreshed and/or updated with new display data by continually repeating this process at some desired number of frames per second. A wide variety of protocols for driving row and column electrodes of pixel arrays to produce display frames are also well known and may be used in conjunction with the present invention.
In the
The details of the structure of interferometric modulators that operate in accordance with the principles set forth above may vary widely. For example,
It is one aspect of the above described devices that charge can build on the dielectric between the layers of the device, especially when the devices are actuated and held in the actuated state by an electric field that is always in the same direction. For example, if the moving layer is always at a higher potential relative to the fixed layer when the device is actuated by potentials having a magnitude larger than the outer threshold of stability, a slowly increasing charge buildup on the dielectric between the layers can begin to shift the hysteresis curve for the device. This is undesirable as it causes display performance to change over time, and in different ways for different pixels that are actuated in different ways over time. As can be seen in the example of
This problem can be reduced by actuating the MEMS display elements with a potential difference of a first polarity during a first portion of the display write process, and actuating the MEMS display elements with a potential difference having a polarity opposite the first polarity during a second portion of the display write process. This basic principle is illustrated in
In
Frame N+1 is written in accordance with the lowermost row of
A wide variety of modifications of this scheme can be implemented. For example, Frame N and Frame N+1 can comprise different display data. Alternatively, it can be the same display data written twice to the array with opposite polarities. One specific embodiment wherein the same data is written twice with opposite polarity signals is illustrated in additional detail in
In this Figure, Frame N and N+1 update periods are illustrated. These update periods are typically the inverse of a selected frame update rate that is defined by the rate at which new frames of display data are received by the display system. This rate may, for example, be 15 Hz, 30 Hz, or another frequency depending on the nature of the image data being displayed.
It is one feature of the display elements described herein that a frame of data can generally be written to the array of display elements in a time period shorter than the update period defined by the frame update rate. In the embodiment of
During the first portion 40 of a frame update period, the frame is written with potential differences across the modulator elements of a first polarity. For example, the voltages applied to the rows and columns may follow the polarity illustrated by the center row of
During a second portion 42 of the frame update period, the same data is written to the array with the opposite polarities applied to the display elements. During this period, the voltages present on the columns are the opposite of what they were during the first portion 40. If the voltage was, for example, +5 volts on a column during time period 50, it will be −5 volts during time period 60, and vice versa. The same is true for sequential applications of sets of display data to the columns, e.g., the potential during period 62 is opposite to that of 52, and the potential during period 64 is opposite to that applied during time period 54. Row strobes 61, 63, 65 of opposite polarity to those provided during the first portion 40 of the frame update period re-write the same data to the array during second portion 42 as was written during portion 40, but the polarity of the applied voltage across the display elements is reversed.
In the embodiment illustrated in
During the next frame update period for Frame N+1, the process may be repeated, as shown in
In some embodiments, several timing variables are independently programmable to ensure DC electric neutrality and consistent hysteresis windows. These timing settings include, but are not limited to, the write+ and write− cycle times, the positive hold and negative hold cycle times, and the row strobe time.
While the frame update cycles discussed herein have a set order of write+, write−, hold +, and hold −, this order can be changed. In other embodiments, the order of cycles can be any other permutation of the cycles. In still other embodiments, different cycles and different permutations of cycles can be used for different display update periods. For example, Frame N might include only a write+ cycle, hold+ cycle, and a hold− cycle, while subsequent Frame N+1 could include only a write−, hold+, and hold− cycle. Another embodiment could use write+, hold+, write−, hold− for one or a series of frames, and then use write−, hold−, write+, hold+ for the next subsequent one or series of frames. It will also be appreciated that the order of the positive and negative polarity hold cycles can be independently selected for each column. In this embodiment, some columns cycle through hold+ first, then hold−, while other columns go to hold− first and then to hold+. In one example, depending on the configuration of the column driver circuit, it may be more advantageous to set half the columns at −5 V and half at +5 V for the first hold cycle 44, and then switch all column polarities to set the first half to +5 V and the second half to −5 V for the second hold cycle 46.
It has also been found advantageous to periodically include a release cycle for the MEMS display elements. It is advantageous to perform this release cycle for one or more rows during some of the frame update cycles. This release cycle will typically be provided relatively infrequently, such as every 100,000 or 1,000,000 frame updates, or every hour or several hours of display operation. The purpose of this periodic releasing of all or substantially all pixels is to reduce the chance that a MEMS display element that is continually actuated for a long period due to the nature of the images being displayed will become stuck in an actuated state. In the embodiment of
In this example, Frame N+2 is unchanged from Frame N+1. No write cycles are then needed, and the update period for Frame N+2 is completely filled with hold cycles 44 and 46. As described above, more than two hold cycles, e.g. four cycles, eight cycles, etc. could be used.
During the first frame update 532, the column signal 524 is logically inverted from the data pattern of column 1 in the first array 520. The row signals 526, 528, and 530 will act as timing signals, wherein a pulse 533 indicates addressing of the row. In the first frame update 532, the row signals 526, 528, and 530 will pulse high. When the column signal 524 is low while a row signal is high, there will be a voltage difference across the electrodes of the particular interferometric modulator at the intersection of the column and row. When the first row signal 526 goes high, the column data signal 524 is low. The deformable layer 34, for example, will collapse if it was not already collapsed due to the differing voltage applied to the deformable layer 34 and the electrode 16, for example. If the cavity was already collapsed, nothing will happen. When the row 2 signal 528 goes high, the column data signal 524 is also high. In this case, the interferometric modulator addressed will be in the near position because the voltage difference between the deformable layer 34 and the electrode 16 will be low. When the third row signal 530 goes high, the column data signal 524 is low. Here, again, the deformable layer 34 at the particular row and column intersection will collapse if it was not already collapsed due to the differing voltage applied to the deformable layer 34 and the electrode 16.
When the row signals are not pulsing, they may be at a bias voltage. The difference between the bias voltage and the column signal is preferably within the hysteresis window, and thus the layers are maintained in their existing state. After the write cycle of the frame update, a hold cycle may occur. During the hold cycle the row signals 526, 528, and 530 will be at the bias voltage, and the column signal 524 is high. However, the column signal 524 could also be at different voltages, but this will not change the state of the interferometric modulators as long as the voltage differences are within the hysteresis window.
In the next frame update 534, the row signals 526, 528, and 530 sequentially go low to serve as timing pulses for addressing the row. The column signal 524 will be as seen in column 1 of the second array. However, the column data signal 524 will not be inverted from the status array 522 when the row signals go low as the timing pulse. When the row signal goes low, that row is addressed by the column signal 524. When the row signal is low and the column signal is low, there will be a very small voltage difference across the electrodes. For example, the column data signal 524 is high when the row voltage 526 is low, there will be a small voltage difference between the deformable layer 34 and the electrode 16. Thus, the deformable layer 34 will no longer be attracted to the electrode 16, and the deformable layer 34 will release, raising the reflective layer 14, for example, from an oxide layer formed on the electrode 16, for example. When the second row signal 528 goes low, the column data signal 524 is high. The deformable layer 34 will collapse if it was not already collapsed due to the differing voltage applied to the deformable layer 34 and the electrode 16. When the third row signal 530 goes low, the column data signal 524 is low. The deformable layer 34 will move away from the oxide layer if it was already collapsed due to the low voltage difference applied to the deformable layer 34 and the electrode 16. When the row signals are at the row bias voltage, the voltage difference is preferably within the hysteresis window and no change in state occurs. After the write cycle of the frame update, a hold cycle may occur. During the hold cycle the row signals 526, 528, and 530 will be at the bias voltage, and the column signal 524 is low. However, the column signal 524 could also be at different voltages, as long as the voltage difference is within the hysteresis window.
As mentioned above, the frame update cycles preferably also include a hold cycle. This will allow for time for new data to be sent to refresh the array. The hold cycle and the write cycles preferably alternate polarities so that a large charge does not build up on the electrodes. The row high voltage is preferably higher than the row bias voltage, which is higher than the row low voltage. In a preferred embodiment, all of these voltages applied on the column signal 524 and the row signals 526, 528, 530 are greater than or equal to a ground voltage. Preferably, the column hold voltages vary less than the column write voltages, so that the difference between the hold voltages and the row bias voltage will stay within the hysteresis window. In an exemplary embodiment, the column high and column low voltages vary by approximately 20 Volts, and the hold voltages vary 10 Volts. However, skilled practitioners will appreciate that the specific voltages used can be varied.
Note that the actuation or release of the upper membrane is not instantaneous. In order for the change in state to occur, the voltage must be outside the hysteresis window for a set length of time. This time period is defined by the following equation:
τChange Voltage>τiMoD+τRC
In other words, in order to change the state of the interferometric modulator, the time at the change voltage, i.e. a voltage either greater than the actuation threshold voltage or less than the release threshold voltage, should be greater than the sum of two time constants. The first time constant is a mechanical constant of the interferometric modulator, which is determined with reference to the thickness of the electrodes, the dielectric material, and the materials of the electrodes. Other factors that are relevant to the mechanical constant include the geometry of the deformable layer 34, the tensile stress of the deformable layer 34 material, and the ease with which air underneath the interferometric modulator reflective layer 14 can be moved out of the cavity. The ease of moving the air is affected by placement of damping holes in the reflective layer 14. The second time constant is the time constant of the resistance and capacitance in the circuit connecting the driving element and the interferometric modulator.
Referring to
In addition to the first condition or in the alternative, the second condition should be met to avoid accidental state changes. The second condition is that the RMS voltage across the two electrodes (column minus row) should be greater than the absolute value of the release voltage and less than the absolute value of the actuation voltage. When the voltage hops between the negative hysteresis window and the positive hysteresis window in
It will be understood by those of skill in the art that numerous and various modifications can be made without departing from the spirit of the present invention. Therefore, it should be clearly understood that the forms of the present invention are illustrative only and are not intended to limit the scope of the present invention.
This application is a continuation of U.S. application Ser. No. 13/672,558, entitled “Method and System for Writing Data to Mems Display Elements,” and filed on Nov. 8, 2012, which is a continuation of U.S. application Ser. No. 11/234,061, entitled “Method and System for Writing Data to Mems Display Elements,” and filed on Sep. 22, 2005, now issued as U.S. Pat. No. 8,310,441, which is a continuation-in-part of U.S. application Ser. No. 11/100,762, entitled “METHOD AND SYSTEM FOR WRITING DATA TO MEMS DISPLAY ELEMENTS,” and filed on Apr. 6, 2005, now U.S. Pat. No. 7,602,375, which claims priority under 35 U.S.C. Section 119(e) to U.S. Provisional Application 60/613,483, entitled “Method and Device for Driving Interferometric Modulators,” and filed on Sep. 27, 2004, and U.S. Provisional Application 60/613,419 entitled Method and Device for Driving Interferometric Modulators with Hysteresis and filed on Sep. 27, 2004, each of which are hereby expressly incorporated by reference in their entirety.
Number | Date | Country | |
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60613483 | Sep 2004 | US | |
60613419 | Sep 2004 | US |
Number | Date | Country | |
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Parent | 13672558 | Nov 2012 | US |
Child | 14307888 | US | |
Parent | 11234061 | Sep 2005 | US |
Child | 13672558 | US |
Number | Date | Country | |
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Parent | 11100762 | Apr 2005 | US |
Child | 11234061 | US |