Method and system to implement an improved floating point adder with integrated adding and rounding

TECHNICAL FIELD

The present invention relates to computing and floating point arithmetic, and, more particularly, to systems and methods to implement an improved floating point adder.

BACKGROUND

The Institute of Electrical and Electronics Engineers (IEEE) specifies a standard, IEEE Std 754, for representation and conversion of exponential or floating point numbers. For example, integer numbers can be converted to exponential numbers and binary numbers can be used to represent different parts of the exponential numbers. In particular, an exponential, or floating point, number includes a sign, a significand or mantissa, and an exponent. The precision of the floating point number indicates the number of bits available to represent the floating point number; that is, the higher the precision, the more bits available. A single precision floating point number is represented by 32 bits: one bit for the sign bit, eight bits for the exponent, and 23 bits for the mantissa. For norm numbers, a bit value of one is understood to precede the 23 bits of the mantissa, becoming in effect, an implicit one most significant bit.

Floating point arithmetic is used for high-powered computing operations that require millions or billions or more of floating point operations per second (FLOPS). Basic functional building blocks such as floating point adders, multipliers and dividers are used to perform the arithmetic operations on floating point numbers. Numerous methods and systems of implementing binary adders in compliance with the IEEE 754 standard are well known in the art. A common general technique for adding two floating point numbers includes aligning and then adding the mantissas of the floating point numbers to produce an arithmetic result for a mantissa. Arriving at the final result for the mantissa and for the calculation typically involves continued shifting and aligning, followed by a final rounding step, according to, for example, the round to nearest method of IEEE Std 754.

The design of floating point arithmetic functions to manage high amounts of data throughput at ever increasing speeds and in ever reducing chip area presents challenges for designers of circuit architecture to contend with. Implementations of floating point arithmetic functional blocks, such as binary floating point adder implementations, need to become faster, more efficient, and take up less space on-chip. Accordingly, it would be desirable to provide alternative implementations and schemes that do not suffer from the drawbacks and weaknesses of existing implementations but rather that are faster, more efficient, that consume incrementally less space on chip.

SUMMARY

The presently preferred embodiments described herein include systems and methods for implementing an improved floating point adder that integrates adding and rounding.

A method of adding a first floating point number to a second floating point number is provided according to one aspect of the invention. According to the method, a first mantissa, a second mantissa, and an input bit are added together to produce a third mantissa. The third mantissa is normalized to produce a final mantissa. The third mantissa and the final mantissa are correctly rounded as a result of the act of adding.

A method of adding a first floating point number to a second floating point number is provided according to a further aspect of the invention. According to the method, a first mantissa is added to a second mantissa. A fourth mantissa is added to an input bit to round the fourth mantissa. A third mantissa is normalized. The acts of adding are integrated together within a single adder to produce the third mantissa.

A method of adding a first floating point number to a second floating point number is provided according to another aspect of the invention. According to the method, a first mantissa, a second mantissa, and an input bit are added together to produce a third mantissa and an output bit. The third mantissa is rounded by updating the input bit based on the output bit to produce a fourth mantissa. The fourth mantissa is normalized. The acts of adding and rounding are integrated within a single adder so that a separate adder to produce a correctly rounded result is not needed and so that the acts of adding and rounding are performed prior to the act of normalizing.

A method of adding a first floating point number to a second floating point number is provided according to a further aspect of the invention. According to the method, a first floating point number having a first mantissa and a second floating point number having a second mantissa are received. The first floating point number, when added to the second floating point number, produces a third floating point number having a third mantissa. The first mantissa and the second mantissa are respectively left-shifted as appropriate to obtain a fourth mantissa and a fifth mantissa. A first carry bit is produced from a second carry bit and from round control variables derived from the first mantissa and the second mantissa. The fourth mantissa, the fifth mantissa and the first carry bit are added together to produce a sixth mantissa and the second carry bit. The sixth mantissa is correctly rounded. The sixth mantissa is right-shifted to produce the third mantissa.

A floating point adder system to add a first floating point number to a second floating point number is provided according to another aspect of the invention. The system includes an adder and a shifter coupled to the adder. The adder performs an add operation to add a first mantissa, a second mantissa, and an input bit together to produce a third mantissa. The shifter normalizes the third mantissa to produce a final mantissa, The third mantissa and the final mantissa are correctly rounded as a result of the add operation performed by the adder.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features, aspects, and advantages will become more apparent from the following detailed description when read in conjunction with the following drawings, wherein:

FIG. 1 is a diagram illustrating an exemplary floating point adder according to a first embodiment;

FIG. 2 is a diagram illustrating an exemplary floating point adder according to a second presently preferred embodiment;

FIGS. 3A and 3B are diagrams illustrating the unpack stages according to FIGS. 1 and 2; and

FIG. 4 is a diagram illustrating an exemplary floating point adder according to a third presently preferred embodiment.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

The present invention will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of preferred embodiments of the present invention.

The presently preferred embodiments described herein include systems and methods for implementing an improved floating point adder that integrates adding and rounding. Two mantissas are added together to produce a correctly rounded mantissa prior to normalization of the mantissa, making a follow on rounding stage unnecessary and conserving more space on chip. With feedback of a carry output of the adder, a less significant bit of the correctly rounded mantissa is a function of a more significant bit of the mantissa.

FIG. 1 is a diagram illustrating an exemplary floating point adder (FADD) 100 according to a first embodiment. The FADD 100 includes a swapper stage 102, a first unpack stage 104, a second unpack stage 106, a right shifter 108, a complement stage 112, an adder stage 114, a normalizer stage 116, a subtract stage 122, an increment adder stage 124, round control logic. 126, a rounding stage 128, adders 130, 132, and a left shifter 134. The normalizer stage 116 includes a count up to e₃leading zeros stage 120 and a left shifter 118.

FIG. 2 is a diagram illustrating an exemplary floating point adder (FADD) 100 according to a second presently preferred embodiment. The FADD 200 includes the swapper stage 102, the first unpack stage 104, the second unpack stage 106, a right shifter 208, a complement stage 212, an adder stage 214, a normalizer stage 216, a subtract stage 222, an increment adder stage 224, round control logic 226, and carry logic 228. The normalizer stage 216 includes a count up to e₃leading zeros stage 220 and a left shifter 218.

FIGS. 3A and 3B are diagrams illustrating the unpack stages 104, 106 according to FIGS. 1 and 2. The second unpack stage 106 of FIG. 3A unpacks a floating point number f₀into a sign bit s₀, a 23 bit mantissa m₀, and an 8 bit exponent field e₀. If e₀is equal to zero, the second unpack stage 106 supplements the mantissa m₀with “00” to form a 25 bit mantissa m₂and forms an 8 bit exponent field e₂that is equal to one. If, as is far more commonly the case, e₀is not equal to zero but is less than 255, the second unpack stage 106 supplements the mantissa m₀with “01” to form a 25 bit mantissa m₂and forms an 8 bit exponent field e₂that is equal to e₀.

Similarly, the first unpack stage 104 of FIG. 3B unpacks a floating point number f₁into a sign bit s₁, a 23 bit mantissa m₁, and an 8-exponent field e₁. If e₁is equal to zero, the first unpack stage 104 supplements the mantissa m₁with “00” to form a 25 bit mantissa m₃and forms an 8 bit exponent field e₃that is equal to one. If, as is far more commonly the case, e₁is not equal to zero but is less than 255, the second unpack stage 104 supplements the mantissa m₁with “01” to form a 25 bit mantissa m₃and forms an 8 bit exponent field e₃that is equal to e₁.

FIG. 4 is a diagram illustrating an exemplary floating point adder (FADD) 300 according to a third presently preferred embodiment. The FADD 300 includes the swapper stage 102, a first right shifter 308, a second right shifter 304, inverters 306, 310, 330, a complement stage 312, an adder stage 314, a normalizer stage 316, a subtract stage 322, an increment adder stage 324, round control logic 326, carry logic 328, and eight two input AND gates 332. The normalizer stage 316 includes a count up to e₁leading zeros stage 320 and a left shifter 318.

Operation of the First Embodiment

Processing of the exemplary FADD 100 shown in FIG. 1 according to the first embodiment is now described. The swapper stage 102 receives two floating point numbers, i₁and i₀, and compares theunsigned magnitudes of the numbers to determine their relative size. The number whose magnitude is less than or equal to theunsigned magnitude of the other number is designated f₀and is processed on the right-hand side of FIG. 1. The greater or equivalent other number is designated f₁and is processed on the left-hand side of FIG. 1. The floating point number f₀includes a sign bit s₀(bit 31 of 32), an eight bit exponent field e₀(bits 30-23 of 32), and a mantissa or significand field (bits 22-0 of 32). The floating point number f₁includes a sign bit s₁(bit 31 of 32), an eight bit exponent field e₁(bits 30-23 of 32), and a mantissa or significand field (bits 22-0 of 32).

The floating point numbers f₁and f₀are processed by the unpack stages 104, 106, respectively, as described above, so that on the left-hand side of FIG. 1, the sign bit s₁and the eight bit exponent field e₃are removed from f₁, leaving a 25 bit adjusted mantissa m₃, and on the right-hand side of FIG. 1, the sign bit s₀and the eight bit exponent field e₂are removed from f₀, leaving a 25 bit adjusted mantissa m₂.

Processing of the remaining mantissa m₃continues downward with the introduction of two control variables, K₃and L₃to the adder 130. L₃and K₃respectively represent the least significant bit m₃[0] and the second least significant bit m₃[1] of the mantissa m₃that serves an input to the adder stage 114.

A control variable for the FADD 100, ADD, is calculated by applying the Boolean equivalence function to the sign bits s₁and s₀, so that when s₁and s₀are both false or are both true, the floating point numbers f₀and f₁have the same sign, an addition operation is being performed, and ADD is true, that is, is equal to a logic one. Similarly, when s₁and s₀are different valued, a subtraction operation is being performed, and ADD is false, that is, is equal to a logic zero. The inverter 110 is provided to complement the ADD control variable to produce the SUB control variable which is input to the complement stage 112 and the adder 132.

Processing continues and the right shifter 108 receives and shifts the bits of the 25 bit mantissa m₂to the right according to the value of the following control variable, RSHIFT, where

RSHIFT=e₃−e₂.

Accordingly, if RSHIFT is equal to zero, the mantissa m₂is not shifted. The right shifter 108 produces a 25 bit mantissa m₄as well as a series of control variables K₄, L₄, G₄, R₄, and S₄. TABLE I is a truth table for generation of K₄, L₄, G₄, R₄, and S₄within the right shifter 108 given the value of the control variable RSHIFT. For example, if RSHIFT is equal to 23, then K₄is equal to the most significant bit m₂[24] of the mantissa m₂, that is, K₄is False. The control variables L₄and K₄respectively represent the least significant bit m₄[0] and the second least significant bit m₄[1] of the mantissa m₄.

TABLE I:-DTruth Table for Generation of J₄, K₄, L₄, G₄, R₄and S₄within Right Shifters 108, 208(FIGS. 1 and 2) where | = OR; and m₂[i] is the ith digit of m₂RSHIFTJ₄K₄L₄G₄R₄S₄0Falsem₂[1]m₂[0]FalseFalseFalse1Falsem₂[2]m₂[1]m₂[0]FalseFalse2Falsem₂[3]m₂[2]m₂[1]m₂[0]False3Falsem₂[4]m₂[3]m₂[2]m₂[1]m₂[0]4Falsem₂[5]m₂[4]m₂[3]m₂[2](m₂[1] | m₂[0])5Falsem₂[6]m₂[5]m₂[4]m₂[3](m₂[2] | m₂[1] | m₂[0])6Falsem₂[7]m₂[6]m₂[5]m₂[4](m₂[3] | . . . | m₂[0])7Falsem₂[8]m₂[7]m₂[6]m₂[5](m₂[4] | . . . | m₂[0])8Falsem₂[9]m₂[8]m₂[7]m₂[6](m₂[5] | . . . | m₂[0])9Falsem₂[10]m₂[9]m₂[8]m₂[7](m₂[6] | . . . | m₂[0])10Falsem₂[11]m₂[10]m₂[9]m₂[8](m₂[7] | . . . | m₂[0])11Falsem₂[12]m₂[11]m₂[10]m₂[9](m₂[8] | . . . | m₂[0])12Falsem₂[13]m₂[12]m₂[11]m₂[10](m₂[9] | . . . | m₂[0])13Falsem₂[14]m₂[13]m₂[12]m₂[11](m₂[10] | . . . | m₂[0])14Falsem₂[15]m₂[14]m₂[13]m₂[12](m₂[11] | . . . | m₂[0])15Falsem₂[16]m₂[15]m₂[14]m₂[13](m₂[12] | . . . | m₂[0])16Falsem₂[17]m₂[16]m₂[15]m₂[14](m₂[13] | . . . | m₂[0])17Falsem₂[18]m₂[17]m₂[16]m₂[15](m₂[14] | . . . | m₂[0])18Falsem₂[19]m₂[18]m₂[17]m₂[16](m₂[15] | . . . | m₂[0])19Falsem₂[20]m₂[19]m₂[18]m₂[17](m₂[16] | . . . | m₂[0])20Falsem₂[21]m₂[20]m₂[19]m₂[18](m₂[17] | . . . | m₂[0])21Falsem₂[22]m₂[21]m₂[20]m₂[19](m₂[18] | . . . | m₂[0])22Falsem₂[23]m₂[22]m₂[21]m₂[20](m₂[19] | . . . | m₂[0])23FalseFalsem₂[23]m₂[22]m₂[21](m₂[20] | . . . | m₂[0])24FalseFalseFalsem₂[23]m₂[22](m₂[21] | . . . | m₂[0])25FalseFalseFalseFalsem₂[23](m₂[22] | . . . | m₂[0])26FalseFalseFalseFalseFalse(m₂[23] | . . . | m₂[0])≦27FalseFalseFalseFalseFalse(m₂[23] | . . . | m₂[0])

At the complement stage 112, if SUB is False, then ADD is True and an addition is being preformed and none of the inputs to the complement stage 112 are complemented. If, however, SUB is True, each binary digit of the mantissa m₄as well as each of the control variables K₄, L₄, G₄, R₄, and S₄are complemented by the complement stage 112. The operation of the complement stage 112 is summarized as follows:

- m₆={m₆[24], m₆[23], . . . , m₆[1], m₆[0]}={m₄[24]{circumflex over ( )} SUB, m₄[23]{circumflex over ( )} SUB, . . . m₄[2]{circumflex over ( )} SUB},
- K₆=K₄{circumflex over ( )} SUB=m₄[1]{circumflex over ( )} SUB=m₆[1],
- L₆=L₄{circumflex over ( )} SUB=m₄[0]{circumflex over ( )} SUB=m₆[0],
- G₆=G₄{circumflex over ( )} SUB,
- R₆=R₄{circumflex over ( )} SUB, and
- S₆=S₄{circumflex over ( )} SUB where {circumflex over ( )} represents the Boolean exclusive-or operation. The 25 bit mantissa m₆produced by the complement stage 112 serves as another input to the adder stage 114. The control variables K₆and L₆are input to the adder 130 and the control variables G₆, R₆, and S₆are input the adder 132.

TABLE II is a truth table for generation of Cin, G₈, R₈, and S₈within the adder 132 given the values of the control variable SUB and the input control variables G₆, R₆, and S₆. For example, if SUB is True, and G₆, R₆, and S₆are all True, then G₈, R₈, and S₈are all False and the overflow bit Cin is True. The signal Cin serves as a carry input to the adder stage 114 as well as the adder 130.

TABLE II

Truth Table for Generation of Cin, G₈, R₈, and S₈

within Adder 132 (FIG. 1)

SUB = ˜ADD

Cin (Adder

(Adder 132
G₆R₆S₆
G₈R₈S₈
132 Carry

Carry In Bit)
(Adder 132 Input)
(Adder 132 Sum)
Out Bit)

False
True False True
True False True
False

False
True True False
True True False
False

False
True True True
True True True
False

True
False False False
False False True
False

True
False False True
False True False
False

True
False True False
False True True
False

True
False True True
True False False
False

True
True False False
True False True
False

True
True False True
True True False
False

True
True True False
True True True
False

True
True True True
False False False
True

Cin = SUB & G₆& R₆& S₆

where & = AND; and ˜ = NOT

TABLE III is a truth table for generation of K₈and L₈within the adder 130 given the values of Cin from the adder 132 and of the pairs of input control variables K₃, L₃and K₆, L₆. For example, if Cin is False, and K₃, L₃and K₆, L₆are all True, then K₈and L₈are True and False, respectively. The control variables K₈and L₈join with G₈, R₈, and S₈to form a 5 bit word that is input to the left shifter 134.

TABLE IIITruth Table for Generation of K₈and L₈withinAdder 130 (FIG. 1)CinK₃L₃K₆L₆K₈L₈(Adder 130(Adder 130 First(Adder 130 Second(Adder 130 SumCarry In Bit)Input)Input)Input)00 00 00 000 00 10 100 01 01 000 01 11 100 10 00 100 10 11 000 11 01 100 11 10 001 00 01 001 00 11 101 01 00 001 01 10 101 10 01 101 10 10 001 11 00 101 11 11 010 00 00 110 00 11 010 01 01 110 01 10 010 10 01 010 10 11 110 11 00 010 11 10 111 00 01 111 00 10 011 01 00 111 01 11 011 10 00 011 10 10 111 11 01 011 11 11 1

The adder stage 114 receives the 25 bit mantissa m₃, the 25 bit mantissa m₆, and the Cin bit signal and adds these together to produce a 25 bit mantissa m₇. The carry out bit of the adder stage 114 is discarded and is not used to obtain the final result of the FADD 100.

Processing continues to the normalizer stage 116, which receives the 25 bit mantissa m₇the control variable G₈from the adder 132. The count up to e₃leading zeros stage 120 examines each bit of the mantissa m₇beginning with the most significant bit m₇[24] and counts logic zeros until the stage 120 counts e₃logic zeros, until the stage 120 encounters a logic one, or until the 25 bits of the mantissa m₇are exhausted, whichever comes first. The stage 120 outputs a control variable LSHIFT that is equal to the number of counted leading logic zeros in the mantissa m₇. The left shifter 118 receives and shifts the bits of the 25 bit mantissa m₇to the left to produce a 25 bit mantissa m₁₁according to the value of the control variable, LSHIFT. Accordingly, if LSHIFT is equal to zero, the mantissa m₇is not shifted and the mantissa m₁₁equals the mantissa m₇. If LSHIFT is equal to one, then the control variable G₈is shifted in to become the least significant bit of the mantissa m₁₁. If LSHIFT is greater than one, the control variable G₈is shifted in, followed by LSHIFT-1 logic zeros, to form the latter part of the mantissa m₁₀.

Returning to the left shifter 134, the shifter 134 receives the 5 bit word consisting of the control variables K₈, L₈, G₈, R₈, and S₈and shifts the bits of the 5 bit word to the left to produce a 5 bit word that consists of the control variables K₁₀, L₁₀, G₁₀, R₁₀, and S₁₀, according to the value of the control variable, LSHIFT. TABLE IV is a truth table for generation of K₁₀, L₁₀, G₁₀, R₁₀, and S₁₀within the left shifter 134 given the values of the control variable LSHIFT and the input control variables K₈, L₈, G₈, R₈,and S₈. For example, if LSHIFT is equal to three, then K₁₀is equal to R₈, L₁₀is equal to S₈, and G₁₀, R₁₀, and S₁₀are all False. The 5 bit word of K₁₀L₁₀G₁₀R₁₀S₁₀serves as the input to the round control logic 126.

TABLE IVTruth Table for Generation of K₁₀, L₁₀, G₁₀, R₁₀and S₁₀withinLeft Shifter 134 (FIG. 1) where | = ORLEFT SHIFT(integer value of 8bit number)K₁₀L₁₀G₁₀R₁₀S₁₀0K₈L₈G₈R₈S₈1L₈G₈R₈S₈False2G₈R₈S₈FalseFalse3R₈S₈FalseFalseFalse4S₈FalseFalseFalseFalse5 to e₃FalseFalseFalseFalseFalse

Next, the round control logic 126 receives the control variables K₁₀, L₁₀, G₁₀, R₁₀, and S₁₀. TABLE V is a truth table for generation of the control signal increment (INC) within the round control logic 126 given the values of the input control variables K₁₀, L₁₀, G₁₀, R₁₀, and S₁₀. For example, if K₁₀and S₁₀are False and L₁₀, G₁₀, and R₁₀are True, then INC is True. The signal INC serves as a carry input to the rounding stage 128.

TABLE VTruth Table for Generation of INC withinRound Control Logic 126 (FIG. 1)K₁₀L₁₀G₁₀R₁₀S₁₀INCFalseFalseFalseFalseFalseFalseFalseFalseFalseFalseTrueFalseFalseFalseFalseTrueFalseFalseFalseFalseFalseTrueTrueFalseFalseFalseTrueFalseFalseFalseFalseFalseTrueFalseTrueFalseFalseFalseTrueTrueFalseFalseFalseFalseTrueTrueTrueFalseFalseTrueFalseFalseFalseTrueFalseTrueFalseFalseTrueTrueFalseTrueFalseTrueFalseTrueFalseTrueFalseTrueTrueTrueFalseTrueTrueFalseFalseTrueFalseTrueTrueFalseTrueTrueFalseTrueTrueTrueFalseTrueFalseTrueTrueTrueTrueTrueTrueFalseFalseFalseFalseFalseTrueFalseFalseFalseTrueFalseTrueFalseFalseTrueFalseFalseTrueFalseFalseTrueTrueFalseTrueFalseTrueFalseFalseFalseTrueFalseTrueFalseTrueFalseTrueFalseTrueTrueFalseFalseTrueFalseTrueTrueTrueTrueTrueTrueFalseFalseFalseTrueTrueTrueFalseFalseTrueTrueTrueTrueFalseTrueFalseTrueTrueTrueFalseTrueTrueTrueTrueTrueTrueFalseFalseTrueTrueTrueTrueFalseTrueTrueTrueTrueTrueTrueFalseTrueTrueTrueTrueTrueTrueTrue

Processing of the mantissa m₁₁continues downward with the removal of the least significant bit m₁₁[0] from the mantissa m₁₁to produce a 24 bit mantissa m₁₂. The rounding stage 128 adds the signal INC to the mantissa m₁₂to produce a 24 bit mantissa m₁₃. The rounding stage 128 is in effect an additional adder stage that follows the normalizer stage 116.

Next, the most significant bit of the 24 bit mantissa m₁₃is removed to produce the 23 bit mantissa m of the floating point number f_resultoutput of the FADD 100. The most significant bit serves as an input to the increment adder stage 124.

The subtract stage 122 subtracts the 8 bit control variable LSHIFT from the 8 bit exponent field value e₃from the unpack stage 104 and produces an 8 bit output that is in turn sent to the increment adder stage 124. The increment adder stage 124 adds the 8 bit output of the subtract stage 122 to the one bit most significant bit described above to produce the 8 bit exponent field e of the floating point number f_result. The sign bit s1 of the floating point number f₁becomes the sign bit s of the floating point number f_result. All parts s, e, and m of the floating point number f_resultare thus known and processing of the FADD 100 terminates.

Operation of the Second Embodiment

Processing of the exemplary FADD 200 shown in FIG. 2 according to the second embodiment is now described. The swapper stage 102 receives two floating point numbers, i₁and i₀, and compares theunsigned magnitude of the numbers to determine their relative size. The number whose magnitude is less than or equal to theunsigned magnitude of the other number is designated f₀and is processed on the right-hand side of FIG. 2. The greater or equivalent other number is designated f₁and is processed on the left-hand side of FIG. 2. The floating point number f₀includes a sign bit s₀(bit 31 of 32), an eight bit exponent field e₀(bits 30-23 of 32), and a mantissa or significand field (bits 22-0 of 32). The floating point number f₁includes a sign bit s₁(bit 31 of 32), an eight bit exponent field e₁(bits 30-23 of 32), and a mantissa or significand field (bits 22-0 of 32).

The floating point numbers f₁and f₀are processed by the unpack stages 104, 106, respectively, as described above, so that on the left-hand side of FIG. 2, the sign bit s₁and the eight bit exponent field e₃are removed from f₁, leaving a 25 bit adjusted mantissa m₃, and on the right-hand side of FIG. 2, the sign bit s₀and the eight bit exponent field e₂are removed from f₀, leaving a 25 bit adjusted mantissa m₂.

Processing of the remaining mantissa m₃continues downward with the introduction of three control variables, J₃, K₃, and L₃to the round control logic 226. J₃, L₃, and K₃respectively represent the most significant bit m₃[24], the least significant bit m₃[0], and the second least significant bit m₃[1] of the mantissa m₃that serves as an input to the adder stage 214.

A control variable for the FADD 200, ADD, is calculated by applying the Boolean equivalence function to the sign bits s₁and s₀, so that when s₁and s₀are both false or are both true, the floating point numbers f₀and f₁have the same sign, an addition operation is being performed, and ADD is true, that is, is equal to a logic one. Similarly, when s₁and s₀are different valued, a subtraction operation is being performed, and ADD is false, that is, is equal to a logic zero. The inverter 210 is provided to complement the ADD control variable to produce the SUB control variable which is input to the complement stage 212 and the round control logic 226.

Processing continues and the right shifter 208 receives and shifts the bits of the 25 bit mantissa m₂to the right according to the value of the following control variable, RSHIFT, where

RSHIFT=e₃−e₂.

Accordingly, if RSHIFT is equal to zero, the mantissa m₂is not shifted. The right shifter 208 produces a 25 bit mantissa m₄as well as a series of control variables J₄, K₄, L₄, G₄, R₄, and S₄. TABLE I is a truth table for generation of J₄, K₄, L₄, G₄, R₄, and S₄within the right shifter 208 given the value of the control variable RSHIFT. For example, if RSHIFT is equal to 23, then K₄is equal to the most significant bit m₂[24] of the mantissa m₂, that is, K₄is False. The control variables J₄, L₄, and K₄respectively represent the most significant bit m₄[24], the least significant bit m₄[0], and the second least significant bit m₄[1] of the mantissa m₄.

At the complement stage 212, if SUB is False, then ADD is True and an addition is being performed and none of the inputs to the complement stage 212 are complemented. If, however, SUB is True, each binary digit of the mantissa m₄as well as each of the control variables J₄, K₄, L₄, G₄, R₄, and S₄are complemented by the complement stage 212. The operation of the complement stage 212 is summarized as follows:

- m₆={m₆[24], m₆[23], . . . , m₆[1], m₆[0]}={m₄[24]{circumflex over ( )} SUB, m₄[23]{circumflex over ( )} SUB, . . . , m₄[2]{circumflex over ( )} SUB, m₄[1]{circumflex over ( )} SUB},
- J₆=J₄{circumflex over ( )} SUB=m₄[24]{circumflex over ( )} SUB=m₆[24],
- K₆=K₄{circumflex over ( )} SUB=m₄[1]{circumflex over ( )} SUB=m₆[1],
- L₆=L₄{circumflex over ( )} SUB=m₄[0]{circumflex over ( )} SUB=m₆[0],
- G₆=G₄{circumflex over ( )} SUB,
- R₆=R₄{circumflex over ( )} SUB, and
- S₆=S₄{circumflex over ( )} SUB where {circumflex over ( )} represents the Boolean exclusive-or operation. The 25 bit mantissa m₆produced by the complement stage 212 serves as another input to the adder stage 214. The control variable outputs J₆, K₆, L₆, G₆, R₆, and S₆of the complement stage 212 are input to the round control logic 226.

TABLE VI is a truth table for generation of internal control variables L and K within the round control logic 226 given the values of the input control variables K₃, K₆, L₃, and L₆. For example, if K₃, K₆, L₃, and L₆are all true, then L and K are False and True, respectively.

TABLE VITruth Table for Generation of L and K withinRound Control Logic 226 (FIG. 2);K = K₃{circumflex over ( )}K₆{circumflex over ( )}(L₃& L₆); L = L₃{circumflex over ( )}L₆where {circumflex over ( )}= EXCLUSIVE-OR; and & = ANDK₃K₆L₃L₆LKFalseFalseFalseFalseFalseFalseFalseFalseFalseTrueTrueFalseFalseFalseTrueFalseTrueFalseFalseFalseTrueTrueFalseTrueFalseTrueFalseFalseFalseTrueFalseTrueFalseTrueTrueTrueFalseTrueTrueFalseTrueTrueFalseTrueTrueTrueFalseFalseTrueFalseFalseFalseFalseTrueTrueFalseFalseTrueTrueTrueTrueFalseTrueFalseTrueTrueTrueFalseTrueTrueFalseFalseTrueTrueFalseFalseFalseFalseTrueTrueFalseTrueTrueFalseTrueTrueTrueFalseTrueFalseTrueTrueTrueTrueFalseTrue

TABLE VII is a truth table for generation of the control variables GEN, PROP and G₈within the round control logic 226 given the values of the internal control variables K and L shown in TABLE VI and of the input control variables SUB, J₃, J₆, G₆, R₆, and S₆. For example, if J₃, J₆, SUB, K, L, G₆, R₆, and S₆are all True, then GEN and PROP are both True and G₈is False. The control variables GEN and PROP are input to the carry logic 228. G₈serves as an input to the left shifter 218 of the normalizer stage 216. TABLE VII also explains the generation of the signal Cin within the carry logic 228 given the values of the control variables GEN and PROP from the round control logic 226. Similarly, TABLE VIII is a truth table for generation of the signal Cin within the carry logic 228 given the values of the control variables GEN and PROP and the signal C23 from the adder stage 214. C23 is the second most significant carry bit of the adder stage 214, with C24 or Cout representing the most significant carry bit of the adder stage 214. For example, if GEN is False and PROP is True, then Cin follows the value of C23. If GEN and PROP are both False, then Cin is False. Finally, if GEN is True, then Cin is True.

TABLE VIITruth Table for Generation of GEN, PROP, and G₈within Round Control Logic226 and Cin within Carry Logic 228 (FIG. 2); GEN = (˜SUB & ˜G₆&(L | ˜R₆| ˜S₆)) | (SUB & G₆& (R₆| S₆)) |(˜J₆& ˜SUB & K & L); PROP = (˜J₃& ˜SUB & L & (K |˜R₆|˜S₆)) | (L & ˜G₆& R₆& S₆) | (SUB & G₆);G₈= (˜G₆& R6) | (G₆& ˜R₆& ˜S₆) where & =AND; | = OR; and ˜ = NOT; DC = Don't CareJ₃J₆SUBKLG₆R₆S₆GENPROPG₈CinFalseFalseFalseFalseFalseFalseFalseFalseFalseFalseDCFalseFalseFalseFalseFalseFalseFalseFalseTrueFalseFalseDCFalseFalseFalseFalseFalseFalseFalseTrueFalseFalseFalseDCFalseFalseFalseFalseFalseFalseFalseTrueTrueFalseFalseDCFalseFalseFalseFalseFalseFalseTrueFalseFalseFalseFalseDCFalseFalseFalseFalseFalseFalseTrueFalseTrueTrueFalseDCTrueFalseFalseFalseFalseFalseTrueTrueFalseTrueFalseDCTrueFalseFalseFalseFalseFalseTrueTrueTrueTrueFalseDCTrueFalseFalseFalseFalseTrueFalseFalseFalseFalseFalseDCFalseFalseFalseFalseFalseTrueFalseFalseTrueFalseTrueDCC23FalseFalseFalseFalseTrueFalseTrueFalseFalseTrueDCC23FalseFalseFalseFalseTrueFalseTrueTrueFalseTrueDCC23FalseFalseFalseFalseTrueTrueFalseFalseTrueTrueDCTrueFalseFalseFalseFalseTrueTrueFalseTrueTrueTrueDCTrueFalseFalseFalseFalseTrueTrueTrueFalseTrueTrueDCTrueFalseFalseFalseFalseTrueTrueTrueTrueTrueTrueDCTrueFalseFalseFalseTrueFalseFalseFalseFalseFalseFalseDCFalseFalseFalseFalseTrueFalseFalseFalseTrueFalseFalseDCFalseFalseFalseFalseTrueFalseFalseTrueFalseFalseFalseDCFalseFalseFalseFalseTrueFalseFalseTrueTrueFalseFalseDCFalseFalseFalseFalseTrueFalseTrueFalseFalseFalseFalseDCFalseFalseFalseFalseTrueFalseTrueFalseTrueTrueFalseDCTrueFalseFalseFalseTrueFalseTrueTrueFalseTrueFalseDCTrueFalseFalseFalseTrueFalseTrueTrueTrueTrueFalseDCTrueFalseFalseFalseTrueTrueFalseFalseFalseTrueTrueDCTrueFalseFalseFalseTrueTrueFalseFalseTrueTrueTrueDCTrueFalseFalseFalseTrueTrueFalseTrueFalseTrueTrueDCTrueFalseFalseFalseTrueTrueFalseTrueTrueTrueTrueDCTrueFalseFalseFalseTrueTrueTrueFalseFalseTrueTrueDCTrueFalseFalseFalseTrueTrueTrueFalseTrueTrueTrueDCTrueFalseFalseFalseTrueTrueTrueTrueFalseTrueTrueDCTrueFalseFalseFalseTrueTrueTrueTrueTrueTrueTrueDCTrueFalseFalseTrueFalseFalseFalseFalseFalseFalseFalseFalseFalseFalseFalseTrueFalseFalseFalseFalseTrueFalseFalseFalseFalseFalseFalseTrueFalseFalseFalseTrueFalseFalseFalseTrueFalseFalseFalseTrueFalseFalseFalseTrueTrueFalseFalseTrueFalseFalseFalseTrueFalseFalseTrueFalseFalseFalseTrueTrueC23FalseFalseTrueFalseFalseTrueFalseTrueTrueTrueFalseTrueFalseFalseTrueFalseFalseTrueTrueFalseTrueTrueFalseTrueFalseFalseTrueFalseFalseTrueTrueTrueTrueTrueFalseTrueFalseFalseTrueFalseTrueFalseFalseFalseFalseFalseFalseFalseFalseFalseTrueFalseTrueFalseFalseTrueFalseFalseFalseFalseFalseFalseTrueFalseTrueFalseTrueFalseFalseFalseTrueFalseFalseFalseTrueFalseTrueFalseTrueTrueFalseTrueTrueC23FalseFalseTrueFalseTrueTrueFalseFalseFalseTrueTrueC23FalseFalseTrueFalseTrueTrueFalseTrueTrueTrueFalseTrueFalseFalseTrueFalseTrueTrueTrueFalseTrueTrueFalseTrueFalseFalseTrueFalseTrueTrueTrueTrueTrueTrueFalseTrueFalseFalseTrueTrueFalseFalseFalseFalseFalseFalseFalseFalseFalseFalseTrueTrueFalseFalseFalseTrueFalseFalseFalseFalseFalseFalseTrueTrueFalseFalseTrueFalseFalseFalseTrueFalseFalseFalseTrueTrueFalseFalseTrueTrueFalseFalseTrueFalseFalseFalseTrueTrueFalseTrueFalseFalseFalseTrueTrueC23FalseFalseTrueTrueFalseTrueFalseTrueTrueTrueFalseTrueFalseFalseTrueTrueFalseTrueTrueFalseTrueTrueFalseTrueFalseFalseTrueTrueFalseTrueTrueTrueTrueTrueFalseTrueFalseFalseTrueTrueTrueFalseFalseFalseFalseFalseFalseFalseFalseFalseTrueTrueTrueFalseFalseTrueFalseFalseFalseFalseFalseFalseTrueTrueTrueFalseTrueFalseFalseFalseTrueFalseFalseFalseTrueTrueTrueFalseTrueTrueFalseTrueTrueC23FalseFalseTrueTrueTrueTrueFalseFalseFalseTrueTrueC23FalseFalseTrueTrueTrueTrueFalseTrueTrueTrueFalseTrueFalseFalseTrueTrueTrueTrueTrueFalseTrueTrueFalseTrueFalseFalseTrueTrueTrueTrueTrueTrueTrueTrueFalseTrueFalseTrueFalseFalseFalseFalseFalseFalseFalseFalseDCFalseFalseTrueFalseFalseFalseFalseFalseTrueFalseFalseDCFalseFalseTrueFalseFalseFalseFalseTrueFalseFalseFalseDCFalseFalseTrueFalseFalseFalseFalseTrueTrueFalseFalseDCFalseFalseTrueFalseFalseFalseTrueFalseFalseFalseFalseDCFalseFalseTrueFalseFalseFalseTrueFalseTrueTrueFalseDCTrueFalseTrueFalseFalseFalseTrueTrueFalseTrueFalseDCTrueFalseTrueFalseFalseFalseTrueTrueTrueTrueFalseDCTrueFalseTrueFalseFalseTrueFalseFalseFalseFalseFalseDCFalseFalseTrueFalseFalseTrueFalseFalseTrueFalseTrueDCC23FalseTrueFalseFalseTrueFalseTrueFalseFalseTrueDCC23FalseTrueFalseFalseTrueFalseTrueTrueFalseTrueDCC23FalseTrueFalseFalseTrueTrueFalseFalseTrueTrueDCTrueFalseTrueFalseFalseTrueTrueFalseTrueTrueTrueDCTrueFalseTrueFalseFalseTrueTrueTrueFalseTrueTrueDCTrueFalseTrueFalseFalseTrueTrueTrueTrueTrueTrueDCTrueFalseTrueFalseTrueFalseFalseFalseFalseFalseFalseDCFalseFalseTrueFalseTrueFalseFalseFalseTrueFalseFalseDCFalseFalseTrueFalseTrueFalseFalseTrueFalseFalseFalseDCFalseFalseTrueFalseTrueFalseFalseTrueTrueFalseFalseDCFalseFalseTrueFalseTrueFalseTrueFalseFalseFalseFalseDCFalseFalseTrueFalseTrueFalseTrueFalseTrueTrueFalseDCTrueFalseTrueFalseTrueFalseTrueTrueFalseTrueFalseDCTrueFalseTrueFalseTrueFalseTrueTrueTrueTrueFalseDCTrueFalseTrueFalseTrueTrueFalseFalseFalseFalseTrueDCC23FalseTrueFalseTrueTrueFalseFalseTrueFalseTrueDCC23FalseTrueFalseTrueTrueFalseTrueFalseFalseTrueDCC23FalseTrueFalseTrueTrueFalseTrueTrueFalseTrueDCC23FalseTrueFalseTrueTrueTrueFalseFalseTrueTrueDCTrueFalseTrueFalseTrueTrueTrueFalse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TABLE VIII

Truth Table for Generation of Cin

within Carry Logic 228 (FIG. 2);

GEN
PROP
C23
Cin

False
False
False
False

False
False
True
False

False
True
False
False

False
True
True
True

True
False
False
True

True
False
True
True

True
True
False
True

True
True
True
True

Cin = GEN | (PROP & C23)

where & = AND; | = OR

Processing continues to the normalizer stage 216, which receives the 25 bit mantissa m₇and the control variable G₈from the round control logic 226. The count up to e₃leading zeros stage 220 examines each bit of the mantissa m₇beginning with the most significant bit m₇[24] and counts logic zeros until the stage 220 counts e₃logic zeros, until the stage 220 encounters a logic one, or until the 25 bits of.the mantissa m₇are exhausted, whichever comes first. The stage 220 outputs a control variable LSHIFT that is equal to the number of counted leading logic zeros in the mantissa m₇. The left shifter 218 receives and shifts the bits of the 25 bit mantissa m₇to the left to produce a 25 bit mantissa m₁₀according to the value of the control variable, LSHIFT. Accordingly, if LSHIFT is equal to zero, the mantissa m₇is not shifted and the mantissa m₁₀equals the mantissa m₇. If LSHIFT is equal to one, then the control variable G₈is shifted in to become the least significant bit of the mantissa m₁₀. If LSHIFT is greater than one, the control variable G₈is shifted in, followed by LSHIFT-1 logic zeros, to form the latter part of the mantissa m₁₀.

Processing of the mantissa m₁₀continues downward with the removal of the least significant bit m₁₀[0] from the mantissa m₁₀. Next, the most significant bit of the resulting 24 bit mantissa is removed to produce the 23 bit mantissa m of the floating point number f_resultoutput of the FADD 200. The most significant bit serves as an input to the increment adder stage 224.

The subtract stage 222 subtracts the 8 bit control variable LSHIFT from the 8 bit exponent field value e₃from the unpack stage 104 and produces an 8 bit output that is in turn sent to the increment adder stage 224. The increment adder stage 224 adds the 8 bit output of the subtract stage 222 to the one bit most significant bit described above to produce the 8 bit exponent field e of the floating point number f_result, The sign bit s1 of the floating point number f₁becomes the sign bit s of the floating point number f_result. All parts s, e, and m of the floating point number f_resultare thus known and processing of the FADD 200 terminates.

Operation of the Third Embodiment

Processing of the exemplary FADD 300 shown in FIG. 4 according to the third embodiment is now described. The swapper stage 102 receives two floating point numbers, i₁and i₀, and compares theunsigned magnitude of the numbers to determine their relative size. Theunsigned number that is less than or equal to the otherunsigned number is designated f₀and is processed on the right-hand side of FIG. 4. The greater or equivalent otherunsigned number is designated f₁and is processed on the left-hand side of FIG. 4. The floating point number f₀includes a sign bit s₀(bit 31 of 32), an eight bit exponent field e₀(bits 30-23 of 32), and a mantissa or significand field (bits 22-0 of 32). The floating point number f₁includes a sign bit s₁(bit 31 of 32), an eight bit exponent field e₁(bits 30-23 of 32), and a mantissa or significand field (bits 22-0 of 32).

On the left-hand side of FIG. 4, the sign bit s₁and the eight bit exponent field e₁are removed from f₁. Processing of the remaining mantissa continues downward with the introduction of a guard bit G₁having a value of logic zero and an implicit one bit, producing a 25 bit mantissa m₁.

On the right-hand side of FIG. 4, the sign bit s₀and the eight bit exponent field e₀are removed from f₀. Processing of the remaining mantissa continues downward with the introduction of an implicit one bit, producing a 24 bit mantissa m₀. The implicit one bit is the most significant bit m₀[23] of the mantissa m₀.

A control variable for the FADD 300, ADD, is calculated by applying the Boolean equivalence function to the sign bits s₁and s₀, so that when s₁and s₀are both false or are both true, the floating point numbers f₀and f₁have the same sign, an addition operation is being performed, and ADD is true, that is, is equal to a logic one. Similarly, when s₁and s₀are different valued, a subtraction operation is being performed, and ADD is false, that is, is equal to a logic zero. The inverter 310 is provided to complement the ADD control variable to produce the SUB control variable which is input to the complement stage 312 and the round control logic 326.

On the left-hand side of FIG. 4, processing continues at the second right shifter 304, which receives the control variable ADD. If ADD=True, then the second right shifter 304 shifts the mantissa m₁to the right by one to produce a mantissa m₃so that

m₃={m₃[24], m₃[23], . . . , m₃[1], m₃[0]}={0, m₁[24]=1, m₁[23], . . . , m₁[2], m₁[1]}.

If ADD=False, then m₁passes through the second right shifter 304 without any change so that m₃is equal to m₁.

Processing of the mantissa m₃continues downward with the introduction of two control variables, L₃and G₃to the round control logic 326. G₃and L₃respectively represent the least significant bit m₃[0], and the second least significant bit m₃[1] of the mantissa m₃. Next, the guard bit G₃of m₃, that is, m₃[0], is removed and a new guard bit G₅generated from the round control logic 326 is added as the new least significant bit to produce a mantissa m₅. The most significant bit of m₅, m₅[24], is complemented by the inverter 306 and returned as the new most significant bit to form a mantissa m₇that serves as an input to the adder stage 314.

Returning to the right-hand side of FIG. 4, the first right shifter 308 receives and shifts the bits of the 24 bit mantissa m₀to the right according to the value of the following control variable, RSHIFT, where

RSHIFT=e₁−e₀+ADD.

Accordingly, if RSHIFT is equal to zero mantissa m₀is not shifted. The first right shifter 308 produces a 25 bit mantissa m₂as well as a series of control variables L₂, G₂, R₂, and S₂. TABLE IX is a truth table for generation of L₂, G₂, R₂, and S₂within the first right shifter 308 given the value of the control variable RSHIFT. For example, if RSHIFT is equal to 23, then L₂is equal to the most significant bit m₀[23] of the mantissa m₀, that is, L₂is True. The control variables G₂and L₂respectively represent the least significant bit m₂[0], and the second least significant bit m₂[1] of the mantissa m₂.

TABLE IXTruth Table for Generation of L₂, G₂, R₂and S₂within Right Shifter 308 (FIG. 4)where | = OR; and m₀[i] is the ith digit of m₀RSHIFTL₂G₂R₂S₂0m₀[0]FalseFalseFalse1m₀[1]m₀[0]FalseFalse2m₀[2]m₀[1]m₀[0]False3m₀[3]m₀[2]m₀[1]m₀[0]4m₀[4]m₀[3]m₀[2](m₀[1] |m₀[0])5m₀[5]m₀[4]m₀[3](m₀[2] |m₀[1] | m₀[0])6m₀[6]m₀[5]m₀[4](m₀[3] | . . . | m₀[0])7m₀[7]m₀[6]m₀[5](m₀[4] | . . . | m₀[0])8m₀[8]m₀[7]m₀[6](m₀[5] | . . . | m₀[0])9m₀[9]m₀[8]m₀[7](m₀[6] | . . . | m₀[0])10m₀[10]m₀[9]m₀[8](m₀[7] | . . . | m₀[0])11m₀[11]m₀[10]m₀[9](m₀[8] | . . . | m₀[0])12m₀[12]m₀[11]m₀[10](m₀[9] | . . . | m₀[0])13m₀[13]m₀[12]m₀[11](m₀[10] | . . . | m₀[0])14m₀[14]m₀[13]m₀[12](m₀[11] | . . . | m₀[0])15m₀[15]m₀[14]m₀[13](m₀[12] | . . . | m₀[0])16m₀[16]m₀[15]m₀[14](m₀[13] | . . . | m₀[0])17m₀[17]m₀[16]m₀[15](m₀[14] | . . . | m₀[0])18m₀[18]m₀[17]m₀[16](m₀[15] | . . . | m₀[0])19m₀[19]m₀[18]m₀[17](m₀[16] | . . . | m₀[0])20m₀[20]m₀[19]m₀[18](m₀[17] | . . . | m₀[0])21m₀[21]m₀[20]m₀[19](m₀[18] | . . . | m₀[0])22m₀[22]m₀[21]m₀[20](m₀[19] | . . . | m₀[0])23Truem₀[22]m₀[21](m₀[20] | . . . | m₀[0])24FalseTruem₀[22](m₀[21] | . . . | m₀[0])25FalseFalseTrue(m₀[22] | . . . | m₀[0])≦26FalseFalseFalseTrue

At the complement stage 312, if SUB is False, then ADD is True and an addition is being performed and none of the inputs to the complement stage 312 are complemented. If, however, SUB is True, each binary digit of the mantissa m₂as well as each of the control variables L₂, G₂, R₂, and S₂are complemented by the complement stage 312. The operation of the complement stage 312 is summarized as follows:

- m₄={m₄[24], m₄[23], . . . , m₄[1], m₄[0]}={m₂[24]{circumflex over ( )} SUB, m₂[23]{circumflex over ( )} SUB, . . . , m₂[2]{circumflex over ( )} SUB, m₂[1]{circumflex over ( )} SUB},
- L₄=L₂{circumflex over ( )} SUB=m₂[1]{circumflex over ( )} SUB=m₄[1],
- G₄=G₂{circumflex over ( )} SUB=m₂[0]{circumflex over ( )} SUB=m₄[0],
- R₄=R₂{circumflex over ( )} SUB, and
- S₄=S₂{circumflex over ( )} SUB where {circumflex over ( )} represents the Boolean exclusive-or operation.
  
  The 25 bit mantissa m₄produced by the complement stage 312 serves as another input to the adder stage 314. The control variable outputs L₄, G₄, R₄, and S₄of the complement stage 312 are input to the round control logic 326.

TABLE X is a truth table for generation of internal control variables G, L, and G₅within the round control logic 326 given the values of the input control variables L₃, L₄, G₃, and G₄and the internal control variable X. For example, if L₃, L₄, G₃, and G₄are all true, then G and L are False and True. As another example, if G₃or X is True, then G₅is True; otherwise G₅is False. As described above, G₅becomes the least significant bit of the 25 bit mantissa m₅. The internal control variable X used to produce G₅is generated according to TABLE XI below.

TABLE XTruth Table for Generation of G, L and G₅within Round Control Logic 326 (FIG. 4);L = L₃{circumflex over ( )}L₄{circumflex over ( )}(G₃& G₄); G =G₃{circumflex over ( )}G₄; G₅= G₃| Xwhere {circumflex over ( )}= EXCLUSIVE-OR; & =AND; and | = ORL₃L₄G₃G₄GLXG₅FalseFalseFalseFalseFalseFalseFalseFalseFalseFalseFalseTrueTrueFalseFalseFalseFalseFalseTrueFalseTrueFalseFalseTrueFalseFalseTrueTrueFalseTrueFalseTrueFalseTrueFalseFalseFalseTrueFalseFalseFalseTrueFalseTrueTrueTrueFalseFalseFalseTrueTrueFalseTrueTrueFalseTrueFalseTrueTrueTrueFalseFalseFalseTrueTrueFalseFalseFalseFalseTrueFalseFalseTrueFalseFalseTrueTrueTrueFalseFalseTrueFalseTrueFalseTrueTrueFalseTrueTrueFalseTrueTrueFalseFalseFalseTrueTrueTrueFalseFalseFalseFalseFalseFalseTrueTrueFalseTrueTrueFalseFalseFalseTrueTrueTrueFalseTrueFalseFalseTrueTrueTrueTrueTrueFalseTrueFalseTrueFalseFalseFalseFalseFalseFalseTrueTrueFalseFalseFalseTrueTrueFalseTrueTrueFalseFalseTrueFalseTrueFalseTrueTrueFalseFalseTrueTrueFalseTrueTrueTrueFalseTrueFalseFalseFalseTrueTrueTrueFalseTrueFalseTrueTrueTrueTrueTrueFalseTrueTrueFalseTrueTrueTrueTrueFalseTrueTrueTrueFalseFalseTrueTrueTrueFalseFalseFalseFalseTrueTrueTrueTrueFalseFalseTrueTrueTrueTrueTrueTrueFalseTrueFalseTrueTrueTrueTrueTrueFalseTrueTrueFalseFalseTrueTrueTrueTrueFalseFalseFalseFalseTrueTrueTrueTrueFalseTrueTrueFalseTrueTrueTrueTrueTrueFalseTrueFalseTrueTrueTrueTrueTrueTrueFalseTrueTrueTrue

TABLE XI is a truth table for generation of the control variables GEN and PROP and the internal control variable X within the round control logic 326 given the values of the internal control variables L and G shown in TABLE X and of the input control variables SUB, R₄, and S₄. For example, if L, G, R₄, S₄, and SUB are all True, then GEN and PROP are both True and X is False. The control variables GEN and PROP are input to the carry logic 328. TABLE XI also explains the generation of the signal Cin within the carry logic 328 given the values of the control variables GEN and PROP from the round control logic 326. Similarly, TABLE XII is a truth table for generation of the signal Cin within the carry logic 328 given the values of the control variables GEN and PROP and the signal Cout from the adder stage 314. Cout is the most significant carry bit of the adder stage 214. For example, if GEN is False and PROP is True, then Cin follows the value of Cout. If GEN and PROP are both False, then Cin is False. Finally, if GEN is True, then Cin is True.

TABLE XITruth Table for Generation of X, GEN, PROPwithin Round Control Logic 326 and Cinwithin Carry Logic 328 (FIG. 4); X =L & ˜G & R₄& S₄& SUB; GEN =˜X & R₄& (G | S₄| SUB) |G & S₄& SUB; PROP = G & (L |S₄| SUB) | X where & =AND; | = OR; and ˜ = NOTLGR₄S₄SUBXGENPROPCinFalseFalseFalseFalseFalseFalseFalseFalseFalseFalseFalseFalseFalseTrueFalseFalseFalseFalseFalseFalseFalseTrueFalseFalseFalseFalseFalseFalseFalseFalseTrueTrueFalseFalseFalseFalseFalseFalseTrueFalseFalseFalseFalseFalseFalseFalseFalseTrueFalseTrueFalseTrueFalseTrueFalseFalseTrueTrueFalseFalseTrueFalseTrueFalseFalseTrueTrueTrueFalseTrueFalseTrueFalseTrueFalseFalseFalseFalseFalseFalseFalseFalseTrueFalseFalseTrueFalseFalseTrueCoutFalseTrueFalseTrueFalseFalseFalseTrueCoutFalseTrueFalseTrueTrueFalseTrueTrueTrueFalseTrueTrueFalseFalseFalseTrueFalseTrueFalseTrueTrueFalseTrueFalseTrueTrueTrueFalseTrueTrueTrueFalseFalseTrueTrueTrueFalseTrueTrueTrueTrueFalseTrueTrueTrueTrueFalseFalseFalseFalseFalseFalseFalseFalseTrueFalseFalseFalseTrueFalseFalseFalseFalseTrueFalseFalseTrueFalseFalseFalseFalseFalseTrueFalseFalseTrueTrueFalseFalseFalseFalseTrueFalseTrueFalseFalseFalseFalseFalseFalseTrueFalseTrueFalseTrueFalseTrueFalseTrueTrueFalseTrueTrueFalseFalseTrueFalseTrueTrueFalseTrueTrueTrueTrueFalseTrueCoutTrueTrueFalseFalseFalseFalseFalseTrueCoutTrueTrueFalseFalseTrueFalseFalseTrueCoutTrueTrueFalseTrueFalseFalseFalseTrueCoutTrueTrueFalseTrueTrueFalseTrueTrueTrueTrueTrueTrueFalseFalseFalseTrueTrueTrueTrueTrueTrueFalseTrueFalseTrueTrueTrueTrueTrueTrueTrueFalseFalseTrueTrueTrueTrueTrueTrueTrueTrueFalseTrueTrueTrue

TABLE XII

Truth Table for Generation of Cin

within Carry Logic 328 (FIG. 4);

GEN
PROP
Cout
Cin

False
False
False
False

False
False
True
False

False
True
False
False

False
True
True
True

True
False
False
True

True
False
True
True

True
True
False
True

True
True
True
True

Cin = GEN | (PROP & Cout)

where & = AND; | = OR

The adder stage 314 receives the 25 bit mantissa m₇, the 25 bit mantissa m₄, and the Cin bit signal and adds these together to produce a 25 bit mantissa m₈. The most significant carry bit Cout of the adder stage 314 is fed back to the carry logic 328 as described above. Thus, the input carry bit Cin to the adder stage 314 is a function of the carry bit Cout of the adder stage 314. Next, the most significant bit of m₈, m₈[24], is complemented by the inverter 330 and returned as the new most significant bit to form a mantissa m₉that serves as an input to the normalizer stage 316.

Processing continues to the normalizer stage 316, which receives the 25 bit mantissa m₉. The count up to e₁leading zeros stage 320 examines each bit of the mantissa m₉beginning with the most significant bit m₉[24] and counts logic zeros until the stage 320 counts e₁leading zeros, until the stage 320 encounters a logic one, or until the 25 bits of the mantissa m₉are exhausted, whichever comes first. The stage 320 outputs a control variable LSHIFT that is equal to the number of counted leading logic zeros in the mantissa m₉The left shifter 318 receives and shifts the bits of the 25 bit mantissa m₉to the left to produce a 25 bit mantissa m₁₀according to the value of the control variable, LSHIFT. Accordingly, if LSHIFT is equal to zero, the mantissa m₉is not shifted and the mantissa m₁₀equals the mantissa m₉. If LSHIFT is greater than zero, then LSHIFT logic zeros are shifted in to form the latter part of the mantissa m₁₀.

Processing of the mantissa m₁₀continues downward with the removal of G₁₀from the mantissa m₁₀. G₁₀represents the least significant bit m₁₀[0] of the mantissa m₁₀. Next, the most significant bit of the resulting 24 bit mantissa is removed to produce the 23 bit mantissa m of the floating point number f_resultoutput of the FADD 300.

The subtract stage 322 subtracts the 8 bit control variable LSHIFT from the 8 bit exponent field value e₁and produces an 8 bit output that is in turn sent to the increment adder stage 324. The increment adder stage 324 adds the 8 bit output of the subtract stage 322 to the one bit control variable ADD to yield an 8 bit output. The count up to e₁leading zeros stage 320 also outputs a control variable NOTZERO that is True if the mantissa m₉is not equal to zero and False if m₉is equal to zero. The eight AND gates 332 each receive a respective bit of the 8 bit output of the increment adder stage 324 along with the control variable NOTZERO. If the mantissa m₉is nonzero, then NOTZERO is True and the 8 bit output of the increment adder stage 324 is passed through the eight AND gates 332 to produce the 8 bit exponent field e of the floating point number f_result. If the mantissa m₉is zero, then NOTZERO is False, the outputs of the eight AND gates 332 are zero, and the 8 bit exponent field e is zero. The sign bit s₁of the floating point number f₁becomes the sign bit s of the floating point number f_result. All parts s, e, and m of the floating point number f_resultare thus known and processing of the FADD 300 terminates.

EXAMPLE A

An example that demonstrates the operation of the FADDs 100, 200, 300 according to the embodiments is now described. The swapper stage 102 receives two floating point numbers, i₁and i₀, and compares the numbers to determine their relative size. The number that is less than or equal to the other number is designated f₀. The floating point number f₀has the following values:

Decimal value: 8388609 = 2²³+ 1,s₀= 0,e₀= 1 0 0 1 0 1 1 0 = 150,andBit222120191817161514131211109 8 7 6 5 4 3 2 1 0m_f0=00000000000000 0 0 0 0 0 0 0 0 1.

The floating point number f₁has the following values:

Decimal value: 8388610 = 2²³+ 2,s₁= 0,e₁= 1 0 0 1 0 1 1 0 = 150,andBit222120191817161514131211109 8 7 6 5 4 3 2 1 0m_f1=00000000000000 0 0 0 0 0 0 0 1 0.

The ADD and SUB control variables are calculated:

- ADD=(s₀==s₁)=(0==0)=1, indicating an addition operation, and
- SUB=˜ADD=˜(1)=0.

EXAMPLE A
First Embodiment

The floating point numbers f₁and f₀, including m₁=m_f1and m₀=m_f0, are processed by the unpack stages 104, 106, respectively, so that on the left-hand side of FIG. 1, the sign bit s₁and the eight bit exponent field e₃=e₁are removed from f₁, leaving a 25 bit adjusted mantissa m₃,

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₃=0100000000000000 0 0 0 0 0 0 0 1 0

and on the right-hand side of FIG. 1, the sign bit s₀and the eight bit exponent field e₂=e₀are removed from f₀, leaving a 25 bit adjusted mantissa m₂:

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₂=0100000000000000 0 0 0 0 0 0 0 0 1.

Processing of the mantissa m₃continues downward with the introduction of two control variables, K₃=m₃[1]=1 and L₃=m₃[0]=0 to the adder 130.

Since RSHIFT is equal to zero, the mantissa m₂is not shifted. The right shifter 108 produces a 25 bit mantissa m₄

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₄=0100000000000000 0 0 0 0 0 0 0 0 1

as well as a series of control variables K₄, L₄, G₄, R₄, and S₄. By inspection of TABLE I,

K₄=m₂[1]=m₄[1]=0, L₄=m₂[0]=m₄[0]=1, G₄=R₄=S₄=0.

At the complement stage 112, SUB is False since ADD is True and an addition is being performed and none of the inputs to the complement stage 112 are complemented. The operation of the complement stage 112 is summarized as follows:

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₆=0100000000000000 0 0 0 0 0 0 0 0 1

The adder 132 receives the control variable SUB and the input control variables G₆, R₆, and S₆, and, according to TABLE II, generates:

G₈=R₈=S₈=0, and Cin=0.

The adder 130 receives the values of Cin from the adder 132 and of the pairs of input control variables K₃, L₃and K₆, L₆, and, according to TABLE III, generates:

K₈=L₈=1

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 10Carry1m₃=0100000000000000 0 0 0 0 0 0 0 10m₆=0100000000000000 0 0 0 0 0 0 0 01Cin0m₇=1000000000000000 0 0 0 0 0 0 0 11

Processing continues to the normalizer stage 116, which receives the 25 bit mantissa m₇and the control variable G₈from the adder 132. The control variable LSHIFT is equal to the number of counted leading logic zeros in the mantissa m₇and is therefore zero. Since LSHIFT is equal to zero, the mantissa m₇is not shifted and the mantissa m₁₁equals the mantissa m₇

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁₁=1000000000000000 0 0 0 0 0 0 0 1 1.

The control variables K₈and L₈join with G₈, R₈, and S₈to form a 5 bit word that is input to the left shifter 134:

K₈L₈G₈R₈S₈=1 1 0 0 0.

The shifter 134 receives the 5 bit word consisting of the control variables K₈, L₈, G₈, R₈, and S₈and shifts the bits of the 5 bit word to the left to produce a 5 bit word that consists of the control variables K₁₀, L₁₀, G₁₀, R₁₀, and S₁₀, according to the value of the control variable, LSHIFT. Since LSHIFT=0, there is no shift and, according to TABLE IV, the 5 bit word is equal to

K₁₀L₁₀G₁₀R₁₀S₁₀=K₈L₈G₈R₈S₈=1 1 0 0 0.

Next, the round control logic 126 receives the control variables K₁₀, L₁₀, G₁₀, R₁₀, and S₁₀, and, according to TABLE V, generates:

INC=1.

The signal INC serves as a carry input to the rounding stage 128.

Processing of the mantissa m₁₁continues downward with the removal of the least significant bit m₁₁[0] from the mantissa m₁₁to produce a 24 bit mantissa m₁₂

Bit23222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁₂=100000000000000 0 0 0 0 0 0 0 0 1.

The rounding stage 128 adds the signal INC to the mantissa m₁₂to produce a 24 bit mantissa m₁₃

Bit23222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁₃=100000000000000 0 0 0 0 0 0 0 1 0.

Next, the most significant bit of the 24 bit mantissa m₁₃is removed to produce the 23 bit mantissa m

Bit222120191817161514131211109 8 7 6 5 4 3 2 1 0m =00000000000000 0 0 0 0 0 0 0 1 0

of the floating point number f_resultoutput of the FADD 100. The most significant bit msb=1 serves as an input to the increment adder stage 124.

The subtract stage 122 subtracts the 8 bit control variable LSHIFT 00000000 from the 8 bit exponent field value e₃10010110 from the unpack stage 104 and produces an 8 bit output 10010110 that is in turn sent to the increment adder stage 124. The increment adder stage 124 adds the 8 bit output 10010110 of the subtract stage 122 to the one bit most significant bit msb=1 to produce the 8 bit exponent field e 10010111 of the floating point number f_result. The sign bit s₁=0 of the floating point number f₁becomes the sign bit s of the floating point number f_result. All parts s, e, and m of the floating point number f_result, are thus known and processing of the FADD 100 terminates.

EXAMPLE A
Second Embodiment

The floating point numbers f₁and f₀, including m₁=m₀and m₁=m_f0, are processed by the unpack stages 104, 106, respectively, so that on the left-hand side of FIG. 2, the sign bit s₁and the eight bit exponent field e₃=e₁are removed from f₁, leaving a 25 bit adjusted mantissa m₃,

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₃=0100000000000000 0 0 0 0 0 0 0 1 0

and on the right-hand side of FIG. 2, the sign bit s₀and the eight bit exponent field e₂=e₀are removed from f₀, leaving a 25 bit adjusted mantissa m₂:

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₂=0100000000000000 0 0 0 0 0 0 0 0 1.

Processing of the mantissa m₃continues downward with the introduction of two control variables, J₃=m₃[24]=0, K₃=m₃[1]=1, and L₃=m₃[0]=0 to the round control logic 226.

Since RSHIFT is equal to zero, the mantissa m₂is not shifted. The right shifter 208 produces a 25 bit mantissa m₄

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₄=0100000000000000 0 0 0 0 0 0 0 0 1

as well as a series of control variables J₄, K₄, L₄, G₄, R₄, and S₄. By inspection of TABLE I,

- J₄=m₂[24]=m₄[24]=0, K₄=m₂[1]=m₄[1]=0, L₄=m₂[0]=m₄[0]=1, and
- G₄=R₄=S₄=0.

At the complement stage 212, SUB is False since ADD is True and an addition is being performed and none of the inputs to the complement stage 212 are complemented. The operation of the complement stage 212 is summarized as follows:

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₆=0100000000000000 0 0 0 0 0 0 0 0 1

The round control logic 226 receives the control variable SUB and the input control variables J₃, K₃, L₃, J₆, K₆, L₆, G₆, R₆, and S₆, and, according to TABLES VI and VII, generates:

- G₈=Don't Care,
- GEN=True=1, and
- PROP=True=1.

The control variables GEN and PROP and the signal C23 from the adder stage 214 are input to the carry logic 228, which, according to TABLES VII and VIII, generates

Cin=True=1.

In this example, Cin does not depend on the value of C23 from the adder stage 214.

Bit2423222120191817161514131211109 8 7 6 5 4 32 10Carry101 1m₃=0100000000000000 0 0 0 0 0 00 10m₆=0100000000000000 0 0 0 0 0 00 01Cin1m₇=1000000000000000 0 0 0 0 0 01 00

Processing continues to the normalizer stage 216, which receives the 25 bit mantissa m₇and the control variable G₈from the round control logic 226. The control variable LSHIFT is equal to the number of counted leading logic zeros in the mantissa m₇and is therefore zero. Since LSHIFT is equal to zero, the mantissa m₇is not shifted and the mantissa m₁₀equals the mantissa m₇

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁₀=1000000000000000 0 0 0 0 0 0 1 0 0.

Bit222120191817161514131211109 8 7 6 5 4 3 2 1 0m =00000000000000 0 0 0 0 0 0 0 1 0

of the floating point number f_resultoutput of the FADD 200. The most significant bit msb=1 serves as an input to the increment adder stage 224.

The subtract stage 222 subtracts the 8 bit control variable LSHIFT 00000000 from the 8 bit exponent field value e₃106101010 from the unpack stage 104 and produces an 8 bit output 10010110 that is in turn sent to the increment adder stage 224. The increment adder stage 224 adds the 8 bit output 10010110 of the subtract stage 222 to the one bit most significant bit msb=1 to produce the 8 bit exponent field e 10010111 of the floating point number f_result. The sign bit s₁=0 of the floating point number f₁becomes the sign bit s of the floating point number f_result. All parts s, e, and m of the floating point number f_resultare thus known and processing of the FADD 200 terminates.

EXAMPLE A
Third Embodiment

On the left-hand side of FIG. 4, the sign bit Si and the eight bit exponent field e₁are removed from the floating point number f₁, leaving the 23 bit mantissa m_f1. Processing of the mantissa m_f1continues downward with the introduction of a guard bit G₁having a value of logic zero as the new least significant bit and an implicit one bit as the new most significant bit, producing a 25 bit mantissa m₁

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁=1000000000000000 0 0 0 0 0 0 1 0 0.

and on the right-hand side of FIG. 4, the sign bit s₀and the eight bit exponent field e₀are removed from the floating point number f₀, leaving the 23 bit mantissa m_f0. Processing of the mantissa m_f0continues downward with the introduction of an implicit one bit as the new most siginificant bit, producing a 24 bit mantissa m₀

Bit23222120191817161514131211109 8 7 6 5 4 3 2 1 0m₀=100000000000000 0 0 0 0 0 0 0 0 1.

On the left-hand side of FIG. 4, processing continues at the second right shifter 304, which receives the control variable ADD. ADD is True, so the second right shifter 304 shifts the mantissa m₁to the right by one to produce a mantissa m₃

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₃=0100000000000000 0 0 0 0 0 0 0 1 0.

Processing of the mantissa m₃continues downward with the introduction of two control variables, L₃=m₃[1]=1, and G₃=m₃[0]=0 to the round control logic 326.

Processing continues and the first right shifter 308 receives and shifts the bits of the 25 bit mantissa m₀to the right according to the value of the following control variable, RSHIFT

RSHIFT=e₃−e₂+ADD=(1 0 0 1 0 1 1 0)−(1 0 0 1 0 1 1 0)+(1)=0 0 0 0 0 0 0 1.

Since RSHIFT is equal to one, each bit of the mantissa m₀is shifted to the right by one. The first right shifter 308 produces a 25 bit mantissa m₂

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₂=0100000000000000 0 0 0 0 0 0 0 0 1

as well as a series of control variables L₂, G₂, R₂, and S₂. By inspection of TABLE IX,

L₂=m₀[0]=m₂[1]=0, G₂=m₀[0]=m₂[0]=1, R₂=S₂=0.

At the complement stage 312, SUB is False since ADD is True and an addition is being performed and none of the inputs to the complement stage 312 are complemented. The operation of the complement stage 312 is summarized as follows:

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₄=0100000000000000 0 0 0 0 0 0 0 0 1

The round control logic 326 receives the control variable SUB and the input control variables L₃, G₆, L₄, G₄, R₄, and S₄, and, according to TABLES X and XI, generates:

- G₅=False=0,
- GEN=False 0, and
- PROP=True 1.

The control variables GEN and PROP and the signal Cout from the adder stage 314 are input to the carry logic 328, which, according to TABLES XI and XII, generates

Cin=Cout.

In this example, Cin follows the value of Cout from the adder stage 314.

Next, the guard bit G₃of m₃, that is, m₃[0]=0, is removed and a new guard bit G₅=0 generated from the round control logic 326 is added as the new least significant bit to produce a mantissa m₅

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₅=0100000000000000 0 0 0 0 0 0 0 1 0.

The most significant bit of m₅, m₅[24], is complemented by the inverter 306 and returned. as the new most significant bit to form a mantissa m₇

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₇=1100000000000000 0 0 0 0 0 0 0 1 0.

that serves as an input to the adder stage 314.

The adder stage 314 receives the 25 bit mantissa m₇, the 25. bit mantissa m₄, and the Cin bit signal and adds these together to produce a 25 bit mantissa m₈. The most significant carry bit Cout of the adder stage 314 is fed back to the carry logic 328. In order to calculate Cout from the adder stage 314, since Cin follows the value of Cout, an initial value of logic zero is assumed for Cin. If Cout is found to be equal to a logic one when the sum is performed, then Cin is adjusted to a logic one and the sum is performed again. The following illustrates the final sum, once Cin is found to be a logic one.

Bit2423222120191817161514131211109 8 7 6 5 4 32 10Carry11 1m₇=1100000000000000 0 0 0 0 0 00 10m₄=0100000000000000 0 0 0 0 0 00 01Cin1m₈=0000000000000000 0 0 0 0 0 01 00

Next, the most significant bit of m₈, m₈[24], is complemented by the inverter 330 and returned as the new most significant bit to form a mantissa m₉that serves as an input to the normalizer stage 316

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₉=1000000000000000 0 0 0 0 0 0 1 0 0.

Processing continues to the normalizer stage 316, which receives the 25 bit mantissa m₉. The control variable. LSHIFT is equal to the number of counted leading logic zeros in the mantissa m₉and is therefore zero. Since LSHIFT is equal to zero, the mantissa m₉is not shifted and the mantissa m₁₀equals the mantissa m₉

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁₀=1000000000000000 0 0 0 0 0 0 1 0 0.

Processing of the mantissa m₁₀continues downward with the removal of the least significant bit G₁₀from the mantissa m₁₀. Next, the most significant bit of the resulting 24 bit mantissa is removed to produce the 23 bit mantissa m

Bit222120191817161514131211109 8 7 6 5 4 3 2 1 0m =00000000000000 0 0 0 0 0 0 0 1 0

of the floating point number f_resultoutput of the FADD 300.

The subtract stage 322 subtracts the 8 bit control variable LSHIFT 00000000 from the 8 bit exponent field value e₁10010110 and produces an 8 bit output 10010110 that is in turn sent to the increment adder stage 324. The increment adder stage 324 adds the 8 bit output 10010110 of the subtract stage 322 to the one bit control variable ADD=1 to produce the 8 bit exponent field e 10010111 of the floating point number f_result. The sign bit s₁=0 of the floating point number f₁becomes the sign bit s of the floating point number f_result. All parts s, e, and m of the floating point number f_resultare thus known and processing of the FADD 300 terminates.

EXAMPLE B

Another example that demonstrates the operation of the FADDs 100, 200, 300 according to the embodiments is now described. The swapper stage 102 receives two floating point numbers, i₁and i₀, and compares the numbers to determine their relative size. The number that is less than or equal to the other number is designated f₀. The floating point number f₀has the following values:

Decimal value: −8388605.5 = −(2²³) + 2.5,s₀= 1,e₀= 1 0 0 1 0 1 0 1 = 149,andBit222120191817161514131211109 8 7 6 5 4 3 2 1 0m_f0=11111111111111 1 1 1 1 1 1 0 1 1.

The floating point number f₁has the following values:

Decimal value: 16777215 = 2²⁴− 1,s₁= 0,e₁= 1 0 0 1 0 1 1 0 = 150,andBit222120191817161514131211109 8 7 6 5 4 3 2 1 0m_f1=11111111111111 1 1 1 1 1 1 1 1 1.

The ADD and SUB control variables are calculated:

- ADD=(s₀==s₁)=(1==0)=0, indicating a subtraction operation, and
- SUB=˜ADD=˜(0)=1.

EXAMPLE B
First Embodiment

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₃=0111111111111111 1 1 1 1 1 1 1 1 1

and on the right-hand side of FIG. 1, the sign bit s₀and the eight bit exponent field e₂=e₀are removed from f₀, leaving a 25 bit adjusted mantissa m₂:

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₂=0111111111111111 1 1 1 1 1 1 0 1 1.

Processing of the mantissa m₃continues downward with the introduction of two control variables, K₃=m₃[1]=1 and L₃=m₃[0]=1 to the adder 130.

Since RSHIFT is equal to one, the right shifter 108 shifts the bits of the mantissa m₂to the right by one, producing a 25 bit mantissa m₄

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₄=0011111111111111 1 1 1 1 1 1 1 0 1

as well as a series of control variables K₄, L₄, G₄, R₄, and S₄. By inspection of TABLE I, with RSHIFT equal to one,

K₄=m₂[2]=m₄[1]=0, L₄=m₂[1]=m₄[0]=1, G₄=m₂[0]=1, R₄=S₄=0.

At the complement stage 112, SUB is True since ADD is False and a subtraction is being performed and so the inputs to the complement stage 112 are complemented. The operation of the complement stage 112 is summarized as follows:

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₆=1100000000000000 0 0 0 0 0 0 0 1 0

The adder 132 receives the control variable SUB and the input control variables G₆, R₆, and S₆, and, according to TABLE II, generates:

G₈=1, R₈=S₈=0, and Cin=0.

The adder 130 receives the values of Cin from the adder 132 and of the pairs of input control variables K₃, L₃and K₆, L₆, and, according to TABLE III, generates:

K₈=0, L₈=1.

The adder stage 114 receives the 25 bit-mantissa m₃, the 25 bit mantissa m₆, and the Cin bit signal and adds these together to produce a 25 bit mantissa m₇. The carry out bit of the adder stage 114 is discarded and is not used to obtain the final result of the FADD 100.

Bit2423222120191817161514131211109 8 7 6 5 4 3 210Carry1111111111111111 1 1 1 1 1 1 1m₃=0111111111111111 1 1 1 1 1 1 111m₆=1100000000000000 0 0 0 0 0 0 010Cin0m₇=0100000000000000 0 0 0 0 0 0 001

Processing continues to the normalizer stage 116, which receives the 25 bit mantissa m₇and the control variable G₈from the adder 132. The control variable LSHIFT is equal to the number of counted leading logic zeros in the mantissa m₇and is therefore one. Since LSHIFT is equal to one, the left shifter 118 shifts the bits of the mantissa m₇to the left by one and brings in the control variable G₈=1, producing the mantissa m₁₁

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁₁=1000000000000000 0 0 0 0 0 0 0 1 1.

The control variables K₈and L₈join with G₈, R₈, and S₈to form a 5 bit word that is input to the left shifter 134:

K₈L₈G₈R₈S₈=0 1 1 0 0.

The shifter 134 receives the 5 bit word consisting of the control variables K₈, L₈, G₈, R₈, and S₈and shifts the bits of the 5 bit word to the left to produce a 5 bit word that consists of the control variables K₁₀, L₁₀, G₁₀, R₁₀, and S₁₀, according to the value of the control variable, LSHIFT, which in this case is equal to one. According to TABLE IV, the 5 bit word is equal to

K₁₀L₁₀G₁₀R₁₀S₁₀=L₈G₈R₈S₈False=1 1 0 0 0.

Processing of the mantissa m₁₁continues downward with the removal of the least significant bit m₁₁[0] from the mantissa m₁₁to produce a 24 bit mantissa m₁₂

Bit23222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁₂=100000000000000 0 0 0 0 0 0 0 0 1.

The rounding stage 128 adds the signal INC to the mantissa m₁₂to produce a 24 bit mantissa m₁₃

Bit23222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁₃=100000000000000 0 0 0 0 0 0 0 1 0.

Next, the most significant bit of the 24 bit mantissa m₁₃is removed to produce the 23 bit mantissa m

Bit222120191817161514131211109 8 7 6 5 4 3 2 1 0m =00000000000000 0 0 0 0 0 0 0 1 0

of the floating point number f_resultoutput of the FADD 100. The most significant bit msb=1 serves as an input to the increment adder stage 124.

The subtract stage 122 subtracts the 8 bit control variable LSHIFT 00000001 from the 8 bit exponent field value e₃10010110 from the unpack stage 104 and produces an 8 bit output 10010101 that is in turn sent to the increment adder stage 124. The increment adder stage 124 adds the 8 bit output 10010101 of the subtract stage 122 to the one bit most significant bit msb=1 to produce the 8 bit exponent field e 10010110 of the floating point number f_result. The sign bit s₁=0 of the floating point number f₁becomes the sign bit s of the floating point number f_result. All parts s, e, and m of the floating point number f_resultare thus known and processing of the FADD 100 terminates.

EXAMPLE B
Second Embodiment

The floating point numbers f₁and f₀, including m₁=m_f1and m₀=m_f0, are processed by the unpack stages 104, 106, respectively, so that on the left-hand side of FIG. 2, the sign bit s₁and the eight bit exponent field e₃=e₁are removed from f₁, leaving a 25 bit adjusted mantissa m₃,

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₃=0111111111111111 1 1 1 1 1 1 1 1 1

and on the right-hand side of FIG. 2, the sign bit s₀and the eight bit exponent field e₂=e₀are removed from f₀, leaving a 25 bit adjusted mantissa m₂:

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₂=0111111111111111 1 1 1 1 1 1 0 1 1.

Processing of the mantissa m₃continues downward with the introduction of two control variables, J₃=m₃[24]=0, K₃=m₃[1]=1, and L₃=m₃[0]=1 to the round control logic 226.

Since RSHIFT is equal to one, the right shifter 208 shifts the bits of the mantissa m₂to the right by one, producing a 25 bit mantissa m₄

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₄=0011111111111111 1 1 1 1 1 1 1 0 1

as well as a series of control variables J₄, K₄, L₄, G₄, R₄, and S₄. By inspection of TABLE I, with RSHIFT equal to one,

- J₄=m₄[24]=0, K₄=m₂[2]=m₄[1]=0, L₄=m₂[1]=m₄[0]=1, G₄=m₂[0]=1 and
- R₄=S₄=0.

At the complement stage 212, SUB is True since ADD is False and a subtraction is being performed and so the inputs to the complement stage 212 are complemented. The operation of the complement stage 212 is summarized as follows:

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₆=1100000000000000 0 0 0 0 0 0 0 1 0

- G₈=True,
- GEN=False=0, and
- PROP=True 1.

The control variables GEN and PROP and the signal C23 from the adder stage 214 are input to the carry logic 228, which, according to TABLES VII and VIII, generates

Cin=C23.

In this example, Cin follows the value of C23 from the adder stage 214.

The adder stage 214 receives the 25 bit mantissa m₃, the 25 bit mantissa m₆, and the Cin bit signal and adds these together to produce a 25 bit mantissa m₇. The second most significant carry bit C23 of the adder stage 214 is fed back to the carry logic 228. In order to calculate C23 from the adder stage 214, since Cin follows the value of C23, an initial value of logic zero is assumed for Cin. If C23 is found to be equal to a logic one when the sum is performed, then Cin is adjusted to a logic one and the sum is performed again. The following illustrates the final sum, once Cin is found to be a logic one.

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 10Carry1111111111111111 1 1 1 1 1 1 1 1m₃=0111111111111111 1 1 1 1 1 1 1 11m₆=1100000000000000 0 0 0 0 0 0 0 10Cin1m₇=0100000000000000 0 0 0 0 0 0 0 10

Processing continues to the normalizer stage 216, which receives the 25 bit mantissa m₇and the control variable G₈from the round control logic 226. The control variable LSHIFT is equal to the number of counted leading logic zeros in the mantissa m₇and is therefore one. Since LSHIFT is equal to one, the left shifter 218 shifts the bits of the mantissa m₇to the left by one and brings in the control variable G₈=1, producing the mantissa m₁₀

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m_{10 =}1000000000000000 0 0 0 0 0 0 1 0 1

Bit222120191817161514131211109 8 7 6 5 4 3 2 1 0m =00000000000000 0 0 0 0 0 0 0 1 0

of the floating point number f_resultoutput of the FADD 200. The most significant bit msb=1 serves as an input to the increment adder stage 224.

The subtract stage 222 subtracts the 8 bit control variable LSHIFT 00000001 from the 8 bit exponent field value e₃10010110 from the unpack stage 104 and produces an 8 bit output 10010101 that is in turn sent to the increment adder stage 224. The increment adder stage 224 adds the 8 bit output 10010101 of the subtract stage 222 to the one bit most significant bit msb=1 to produce the 8 bit exponent field e 10010110 of the floating point number f_result. The sign bit s₁=0 of the floating point number f₁becomes the sign bit s of the floating point number f_result. All parts s, e, and m of the floating point number f_resultare thus known and processing of the FADD 200 terminates.

EXAMPLE B
Third Embodiment

On the left-hand side of FIG. 4, the sign bit s₁and the eight bit exponent field e₁are removed from the floating point number f₁, leaving the 23 bit mantissa m_f1. Processing of the mantissa m_f1continues downward with the introduction of a guard bit G₁having a value of logic zero as the new least significant bit and an implicit one bit as the new most significant bit, producing a 25 bit mantissa m₁

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁=1111111111111111 1 1 1 1 1 1 1 1 0

Bit23222120191817161514131211109 8 7 6 5 4 3 2 1 0m₀=111111111111111 1 1 1 1 1 1 0 1 1

On the left-hand side of FIG. 4, processing continues at the second right shifter 304, which receives the control variable ADD. ADD is False, so the second right shifter 304 does not shift the mantissa m₁and produces a mantissa m₃

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₃=1111111111111111 1 1 1 1 1 1 1 1 0

that is equal to the mantissa m₁.

Processing of the mantissa m₃continues downward with the introduction of two control variables, L₃=m₃[1]=1, and G₃=m₃[0]=0 to the round control logic 326.

Since RSHIFT is equal to one, each bit of the mantissa m₀is shifted to the right by one. The first right shifter 308 produces a 25 bit mantissa m₂

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₂=0111111111111111 1 1 1 1 1 1 0 1 1

as well as a series of control variables L₂, G₂, R₂, and S₂. By inspection of TABLE IX,

L₂=m₀[1]=m₂[1]=1, G₂=m₀[0]=m₂[0]=1, R₂=S₂=0.

At the complement stage 312, SUB is True since ADD is False and a subtraction is being performed and so the inputs to the complement stage 312 are complemented. The operation of the complement stage 312 is summarized as follows:

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₄=1000000000000000 0 0 0 0 0 0 1 0 0

The round control logic 326 receives the control variable SUB and the input control variables L₃, G₃, L₄, G₄, P₄, and S₄, and, according to TABLES X and XI, generates:

- G₅=True=1,
- GEN=False=0, and
- PROP=True=1.

Next, the guard bit G₃of m₃, that is, m₃[0]=0, is removed and a new guard bit G₅=1 generated from the round control logic 326 is added as the new least significant bit to produce a mantissa m₅

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₅=1111111111111111 1 1 1 1 1 1 1 1 1

The most significant bit of m₅, m₅[24], is complemented by the inverter 306 and returned as the new most significant bit to form a mantissa m₇

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₇=0111111111111111 1 1 1 1 1 1 1 1 1

that serves as an input to the adder stage 314.

The adder stage 314 receives the 25 bit mantissa m₇, the 25 bit mantissa m₄, and the Cin bit signal and adds these together to produce a 25 bit mantissa m₈. The most significant carry bit Cout of the adder stage 314 is fed back to the carry logic 328. In order to calculate Cout from the adder stage 314, since Cin follows the value of Cout, an initial value of logic zero is assumed for Cin. If Cout is found to be equal to a logic one when the sum is performed, then Cin is adjusted to a logic one and the sum is performed again. The following illustrates the final sum, once Cin is found to be a logic one.

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 10Carry1111111111111111 1 1 1 1 1 1 1 1m₇=0111111111111111 1 1 1 1 1 1 1 11m₄=1000000000000000 0 0 0 0 0 0 1 00Cin1m₈=0000000000000000 0 0 0 0 0 0 1 00

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₉=1000000000000000 0 0 0 0 0 0 1 0 0

Processing continues to the normalizer stage 316, which receives the 25 bit mantissa m₉. The control variable LSHIFT is equal to the number of counted leading logic zeros in the mantissa m₉and is therefore zero. Since LSHIFT is equal to zero, the mantissa m₉is not shifted and the mantissa m₁₀equals the mantissa m₉

Bit2423222120191817161514131211109 8 7 6 5 4 3 2 1 0m₁₀=1000000000000000 0 0 0 0 0 0 1 0 0

Bit222120191817161514131211109 8 7 6 5 4 3 2 1 0m =00000000000000 0 0 0 0 0 0 0 1 0

of the floating point number f_resultoutput of the FADD 300.

The subtract stage 322 subtracts the 8 bit control variable LSHIFT 00000000 from the 8 bit exponent field value el 10010110 and produces an 8 bit output 10010110 that is in turn sent to the increment adder stage 324. The increment adder stage 324 adds the 8 bit output 10010110 of the subtract stage 322 to the one bit control variable ADD=0 to produce the 8 bit exponent field e 10010110 of the floating point number f_result. The sign bit s₁=0 of the floating point number f₁becomes the sign bit s of the floating point number f_result. All parts s, e, and m of the floating point number f_resultare thus known and processing of the FADD 300 terminates.

Of course, it should be understood that the floating point adder 100, 200, 300 system configurations, control logic implementations, and connections shown in FIG. 1-4 are merely intended to be exemplary, and that other configurations, implementations, and connections are possible and may be used as suitable. For example, although the FADDs 100, 200, 300 of FIGS. 1, 2 and 4 are designed for handling single precision (32-bit) floating point numbers in compliance with the IEEE Std 754 round to nearest methodology, the FADDs 100, 200, 300 may be extended to process any size of floating point numbers as suitable, including, for example, double precision (64-bit) floating point numbers.

The 32 bits of a single precision floating point number include one bit for a sign bit, eight bits for an exponent field, and 23 bits for the mantissa. For norm numbers, a bit value of one is understood to precede the 23 bits of the mantissa, becoming in effect, an implicit one most significant bit. A norm number has an exponent field that takes on a value between zero and 255. A denorm number, by contrast, has an implicit zero most significant bit of the mantissa, a mantissa that is not equal to zero, and an exponent field that is equivalent to zero.

One notable difference between the FADDs 100, 200, 300 is that the FADD 300 is not designed to handle denorm numbers, while the FADDs 100, 200 are equipped to handle denorm numbers. Of course, depending on the demands of a particular application, the capability of handling denorm numbers may or may not be necessary. It should be understood that, where necessary or as desired, all embodiments may be easily modified to handle denorm numbers as in FIGS. 1-3 or otherwise modified to handle only norm numbers as in FIG. 4.

Of course, it should be understood that although inverters and complement stages are illustrated at various points in the FADDs 100, 200, 300, a given signal value and the complement of the given signal value are available at all places as suitable, even though inverters and complement stages are illustrated for clarity. For example, the functions performed by the complement stage 312 of FIG. 4 and the inverter 310 could be incorporated into the round control logic 326. Similarly, although certain control variable values overlap with mantissa values, in some instances, such values are illustrated separately for clarity. For example, in FIG. 2, the control variable outputs J₄, K₄, and L₄of the right shifter 208 are actually equivalent by definition to values within the mantissa m₄also output by the right shifter 208, these are drawn separately for clarity.

The present invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Apparatus of the invention can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and method acts of the invention can be performed by a programmable processor executing a program of instructions to perform functions of the invention by operating on input data and generating output. The invention can be implemented advantageously in one or more computer programs that executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits).

Although the present invention has been particularly described with reference to the preferred embodiments, it should be readily apparent to those of ordinary skill in the art that changes and modifications in the form and details may be made without departing from the spirit and scope of the invention. It is intended that the appended claims include such changes and modifications.

	Number	Date	Country
Parent	09919713	Jul 2001	US
Child	11140410	May 2005	US

Method and system to implement an improved floating point adder with integrated adding and rounding

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