Patent Grant
7778149
The present invention generally relates to wireless communications and, in particular, to methods and systems that are capable of providing efficient channel access in wireless communications.
IEEE 802.16a is a wireless communications specification for metropolitan area networks (MANs). The 802.16a standard was developed for wireless MANs operating on licensed and unlicensed radio-frequency (RF) bands between 2 GHz and 11 GHz, at data speeds of up to 75 megabits per second (Mbps), with low latency and efficient use of spectrum space. Security is enhanced by encryption features. The contention symbols are based on OFDM (orthogonal frequency division multiplexing) symbols similar in construction to 802.16a (OFDM mode) or 802.11a symbols.
The 802.16a focused contention transmission includes two (2) consecutive contention symbols, each beginning with a cyclic prefix and containing two hundred (200) usable subcarriers. The subcarriers are divided into fifty (50) contention channels of four (4) subcarriers apiece. The lowest numbered contention channel uses subcarriers 0, 50, 100 and 150. The highest numbered contention channel uses subcarriers 49, 99, 149 and 199. The symbol timeline is shown in
Hence, it would be desirable to provide methods and systems that are capable of, amongst other things, providing channel access in an efficient manner and extending the maximum supported propagation delay.
In one embodiment, a system for providing a fast access channel is disclosed. The system includes a transmitter configured to transmit a first long contention symbol and a second long contention symbol. The first long contention symbol is followed by the second long contention symbol. The system further includes a receiver configured to receive the first and second long contention symbols and determine a contention code and a contention channel upon which that contention code was transmitted based on the first and second long contention symbols. Each of the first and second long contention symbols includes a long cyclic prefix and a number of identical contention symbols.
In another embodiment, a system for providing a fast access channel is disclosed. The system includes a transmitter configured to transmit a first long contention symbol and a second long contention symbol. The first long contention symbol is followed by the second long contention symbol. Each of the first and second long contention symbols includes a long cyclic prefix and a plurality of contention symbols. The system further includes a receiver configured to: receive the first and second long contention symbols, retrieve information relating to a selected contention channel from the first and second long contention symbols, remove phase ramp and phase offset information from the retrieved information to generate refined information relating to the selected contention channel, perform correlation coefficient computations between the refined information relating to the selected contention channel and a number of contention codes, and determine a contention code from the contention codes based on results of the correlation coefficient computations.
In some embodiments, the transmitter may be configured to send three (3), four (4) or more contiguous long contention symbols. Each such long contention symbol includes a long cyclic prefix and a plurality of contention symbols. The system further includes a receiver configured to: receive a plurality of long contention symbols, retrieve information relating to a selected contention channel from the plurality of long contention symbols, remove phase ramp and phase offset information from the retrieved information to generate refined information relating to the selected contention channel, perform correlation coefficient computations between the refined information relating to the selected contention channel and a number of contention codes, and determine a contention code from the contention codes based on results of the correlation coefficient computations.
Reference to the remaining portions of the specification, including the drawings and claims, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to accompanying drawings, like reference numbers indicate identical or functionally similar elements.
Aspects, advantages and novel features of the present invention will become apparent from the following description of the invention presented in conjunction with the accompanying drawings:
One or more embodiments of the present invention will now be described. The present invention extends the concept of 802.16a focused contention. In one embodiment, the present invention provides a fast access channel (FACH) which is a unidirectional (reverse) channel.
Each of the contention symbols 204 may be constructed in a similar fashion as an 802.16a contention symbol. The length of a contention symbol 204 may be the same as the usable part of a data symbol. Depending on the version of the physical layer that is used, the contention symbol 204 may be, for example, similar to an 802.11a symbol or an 802.16a symbol. However, those of ordinary skill in the art will readily appreciate and understand that similarity to 802.11a or 802.16a symbols is not necessary and other types of contention symbols may be used. Each data symbol is constructed by populating a subset Nfft of the subcarriers of an IFFT (Inverse Fast Fourier Transform) of length Nfft-TOTAL with modulated data. Only Nfft subcarriers carry usable data.
The long cyclic prefix 202 is multiple times the length of a normal data symbol cyclic prefix 206. In one embodiment, the extension factor matches the number of contention symbols 204 in the long contention symbol 200. This produces a long contention symbol 200 that is exactly multiple times the length of a normal data symbol.
Contention codes and constellation as used in connection with an embodiment of the present invention will now be described. Each contention code defines four (4) BPSK (binary phase shift keying) states, which map onto four (4) subcarriers collectively corresponding to a contention channel. Those of ordinary skill in the art will readily appreciate and understand that a different number of subcarriers and different modulation schemes may alternatively be used. The subcarriers used by each contention channel are spaced at (Nfft/4)-subcarrier intervals, where Nfft is the number of usable subcarriers in the orthogonal frequency division multiplexed (OFDM) symbol, and each subcarrier is transmitted using BPSK modulation. All transmitted contention channels in the first long contention symbol 200 are sent with a calibration contention code. The calibration contention code is used by a receiving station as a reference against which subsequent contention codes are evaluated. All transmitted contention channels in the second long contention symbol 208 are sent with the information-bearing contention code selected by a transmitting station. The receiving station measures the contention channel's phase difference per subcarrier from the first long contention symbol 200 to the second long contention symbol 208 and determines the information content (i.e., identifies which contention code was sent by the transmitting station). Details of the transmitting and receiving stations will be further described below.
In embodiments in which more than two (2) long contention symbols 200, 208 are transmitted, the transmitted contention channels in the third and any subsequent long contention symbols are sent with the information-bearing contention code(s) selected by a transmitting station. A receiving station measures the contention channel's phase difference per subcarrier from the first long contention symbol 200 to the third (or subsequent) long contention symbol(s) and determines the information content (i.e., identifies which contention code was sent by the transmitting station).
The transmitter 300 is used to provide symbol generation for use with the FACH. The transmitter 300 may be incorporated into a master station or a slave station. The master and slave stations can be any one of a base station, access point or subscriber terminal. In the case of a subscriber terminal, the subscriber terminal may comprise a mobile device such as, for example, a consumer product or a mobile phone or terminal. The transmitter 300 is configured to perform a number of functions. The transmitter 300 is able to generate an OFDM symbol including a calibration contention code on specifically programmed contention channels. The transmitter 300 is also able to generate an OFDM symbol including a programmable code transmitted on specifically programmed contention channels. The transmitter 300 employs a handshake mechanism for communication with a downstream IFFT processor and is further able to write symbols to IFFT input memories.
Once enabled, the transmitter 300 has exclusive control over the interface to the IFFT processor. This includes both the memory interface and handshaking mechanism. The transmitter 300 first generates an Nfft subcarrier symbol in the IFFT input memory. This symbol contains a calibration contention code on one (1), two (2) or three (3) specified contention channels, leaving all other contention channels unused. The number and positions of the contention channels are programmable.
Then, a similar symbol is generated in the IFFT input memory. This symbol uses the same contention channels. The value of the contention code placed on each contention channel is specified by an input value. Each symbol includes Nfft data subcarriers divided into Nfft/4 contention channels. Each contention channel has a set of four (4) subcarriers, with adjacent subcarriers in the same set spaced Nfft/4 subcarriers apart. For example, the first contention channel would have subcarrier channels 0, Nfft/4, 2*Nfft/4, 3*Nfft/4; the second contention channel would have subcarrier channels 1, Nfft/4+1, 2*Nfft/4+1, 3*Nfft/4+1, etc.
The purpose of having two (2) or more different symbols 204 is to allow measurement of phase difference between a known contention code on the first symbol 204 and an unknown contention code on a subsequent symbol 204 on corresponding subcarrier frequencies, thereby allowing a receiving station to remove phase noise from the second symbol 204 and obtain the correction contention information. Each transmitter 300 transmits on certain channel(s) so the phase relationship is only applicable to corresponding channels of each symbol.
Some of the functions described above are further illustrated with respect to the finite state machine 302 and the memory control 304. The finite state machine 302 is configured to control the overall operation of the transmitter 300. The finite state machine 302 will remain idle until it is set to an active state. The inputs “contention_code_0”, “contention_code_1”, “contention_code_2”, “nb_channel”, “channel_0”, “channel_1” and “channel_2” have valid values when the active state is initiated. The inputs “contention_code_1”, “contention_code_2”, “channel_1” and “channel_2” depend on the value of “nb_channel”. Once the active state is initiated, the finite state machine 302 loads two (2) contention symbols to the IFFT processor. Each contention symbol 204 includes Nfft subcarriers.
A symbol is constructed by assigning complex values to each of the Nfft usable data subcarriers. This is sub-divided into Nfft/4 contention channels. Each contention channel is made up of four (4) subcarriers separated by Nfft/4 frequency divisions (i.e., the lowest numbered contention channel uses subcarriers 0, Nfft/4, 2*Nfft/4, 3*Nfft/4).
The first contention symbol 204 is generated using a calibration contention code on the contention channels indicated by “channels_0:2”. The second contention symbol 204 is generated using the contention codes indicated by “contention_code_0:2” on the contention channels indicated by “channels_0:2”. All other channels are not populated. The number of channels transmitted is defined by “nb_channel”.
Once the first contention symbol 204 has been read from the “contention code_0:2” input, the FSM determines whether any subsequent contention symbols 204 must be generated. If present, subsequent contention symbols 204 are generated using the contention code indicated by “contention_code_0:2” and are transmitted on the same contention channels as described above.
Once the IFFT processor confirms that all symbols have been processed, the finite state machine 302 returns to the idle state.
The memory control 304 is configured to execute the interface protocol required to access external memory banks.
As noted above, the transmitter 300 may transmit simultaneously on one (1), two (2) or three (3) selected OFDM contention channels during each FACH interval. Multiple transmitters 30 may transmit simultaneously on different contention channels during the same FACH interval. In one embodiment, the contention channels are provided in
Each transmitter 300 may transmit more than one (1) contiguous contention symbols, each of which contains multiple channels. Each transmitter may transmit on channels which are elements of any one or more of the contiguous contention symbols.
The receiver 600 may be incorporated into a base station or terminal. The receiver 600 is configured to detect and decode all of the simultaneous transmissions from various transmitters 300.
As mentioned above, the FACH transmission may include two (2) or more consecutive long contention symbols 200, 208. Each long contention symbol 200, 208 begins with a long cyclic prefix 202 and includes Nfft usable subcarriers. The subcarriers are divided into Nfft/4 contention channels of four (4) subcarriers apiece, as shown in
Each long contention symbol 200, 208 includes a long cyclic prefix 202 followed by multiple copies of the same contention symbol 204, each of which may be constructed in a similar fashion as an 802.16a contention symbol. A contention symbol 204 may represent one of a number of contention codes as shown in
All transmitted contention channels in the first long contention symbol 200 are sent with a calibration contention code (which may correspond to the contention code “0” in
The FFT memory controller 602 reads two (2) complex numbers simultaneously from corresponding FFT memory banks. These complex numbers are scaled down to a predetermined number of bits, e.g., eight (8) bits. The FFT memory controller 602 then further reads the FFT memory banks for a contention channel in a predetermined number of clock cycles, e.g., eight (8) clock cycles. In each two-clock cycle, two subcarrier components are read simultaneously from the memory banks for the first and second long contention symbols 200, 208 respectively. The outputs from the FFT memory controller 602 are then forwarded to the removal module 604.
The removal module 604 is configured to remove the phase ramp and local oscillator (LO) phase offset from the input signals by multiplying the complex conjugate value of xn,k by xn+1,k and outputting the real part of the result, i.e.,
{tilde over (y)}n,k=Re{x*n,k*xn+1,k}
{tilde over (y)}n,k=Re{xn,k}Re{xn+1,k}+Im{xn,k}Im{xn+1,k}
For a contention channel, the removal module 604 processes its inputs on a predetermined number of clock cycles, e.g., eight (8) clock cycles. During the first two clocks, xn,0 and xn+1,0 are read from the inputs and yn,0 is computed and stored in an output buffer. For the subsequent clocks, the remaining three (3) subcarrier components (xn,k and xn+1,k) are processed in a similar manner.
Outputs from the removal module 604 are then forwarded to the FHT module 606. The FHT module 606 correlates the outputs {tilde over (y)}n,k received from the removal module 604 with the contention codes as shown in
[{tilde over (ρ)}0 {tilde over (ρ)}1 {tilde over (ρ)}2 {tilde over (ρ)}3 {tilde over (ρ)}4 {tilde over (ρ)}5 {tilde over (ρ)}6 {tilde over (ρ)}7]T=[{tilde over (ρ)}0 {tilde over (ρ)}1 {tilde over (ρ)}2 {tilde over (ρ)}3 −{tilde over (ρ)}0 −{tilde over (ρ)}1 −{tilde over (ρ)}2 −{tilde over (ρ)}3]T
The computed correlated coefficients {tilde over (ρ)}0, . . . , 7 are then transferred to the code detector 610.
In one implementation, the code detector 610 is configured to compare each correlation coefficient {tilde over (ρ)}0, . . . , 7 with a threshold coefficient {tilde over (ρ)}threshold. If the comparisons show that any correlation coefficient {tilde over (ρ)}k is above the threshold coefficient, then a valid contention code is detected. A detection indicator flag is set to “1” to indicate the presence of a valid contention code; otherwise, the detection indicator flag is set to “0”.
Outputs from the removal module 604 are also forwarded to the power calculator 608. The power calculator 608 is configured to compute the power of the signal in the contention channel as follows:
The computed power is compared to a threshold level. In one implementation, this threshold level is programmable. In another implementation as described below, the threshold level is adaptive. The power calculator 608 outputs the result of this comparison to the threshold calculator 612. The result is used to indicate whether the power level in the contention channel is suitable for code detection. If the result indicates that the power level in the contention channel is suitable for code detection, the threshold calculator 612 accordingly directs the code detector 610 to perform code detection as described above; otherwise, the threshold calculator 612 directs the code detector 610 to perform error handling processes.
In one implementation, the threshold calculator 612 is configured to update the estimate of the noise level that is used by the code detector 610 to perform code detection. Since code detection is based on the measured noise floor. The threshold calculator 612 maintains an estimate of the noise floor by exponentially averaging the received power in subcarriers that are inactive. The averaging formula is as follows:
σn2(k+1)=ασn2(k)+(1−α){circumflex over (σ)}n2(k)
σn2(k+1): next estimation
ασn2(k): current estimation
{circumflex over (σ)}n2(k): current instantaneous estimation
α<1: exponential weighting factor
The finite state machine 614 is configured to generate and control all the signals, such as, the reset, clock, timing and control signals, for the components as shown in
The receiver 600 generally processes the signals received from the transmitter 300 as follows. Information from the first and second long contention symbols 200, 208 is stored in the appropriate memory banks. A first contention channel is identified and selected. The selected contention channel's subcarrier components of the first and second long contention symbols 200, 208 are retrieved from the corresponding memory banks. The phase ramp and LO phase offset are then removed from the respective subcarrier components by the removal module 604. Outputs from the removal module 604 are then forwarded to the FHT module 606. The FHT module 606, in turn, correlates the outputs received from the removal module 604 with a number of contention codes, i.e., a number of correlation coefficients are computed. The computed correlation coefficients and outputs from the threshold calculator 612 are then used by the code detector 610 to identify the transmitted contention code. The foregoing process may then be repeated for other contention channels.
If more than one (1) information-bearing long contention symbols 208 are received, the process described above is repeated for each subsequent long contention symbol 208. Each subsequent long contention symbol 208 is likewise decoded by reference to the first (calibration) long contention symbol 200. This provides a mechanism by which the information content of the FACH process may be increased without incurring the overhead of a linear increase in the time taken to transmit multiple FACH events.
The methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executable by a processor, or in a combination of both, in the form of control logic, programming instructions, or other directions, and may be contained in a single device or distributed across multiple devices. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, DVD or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
The previous description of the disclosed embodiments is provided for purposes of illustration and description to enable any person skilled in the art to make or use the present invention. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the full scope consistent with the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more”. All structural and functional equivalents to the elements of the various embodiments described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. §112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for”.
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