The present invention generally concerns modeling of semiconductor circuits and more particularly concerns the automated translation of fabrication process parameters used to specify a semiconductor fabrication process into an electric circuit model of the semiconductor circuit created by the semiconductor fabrication process.
Semiconductor process engineers need to understand the impact of process tolerances on the electrical performance of semiconductor devices. The path from process data to electric data is very intricate and requires expert knowledge of circuit analysis. Since process engineers typically are concerned with developments in process technology, they often lack expert knowledge concerning circuit analysis. Furthermore, the semiconductor fabrication process itself is becoming very involved in advanced technologies, which further complicates the evaluation of electric parameters. The known solutions based on rules of thumb and analytical approximations are no longer accurate enough. Also, solutions based on geometric information rather than process information neglects the impact of correlations between geometric and process parameters.
Progress has been made in understanding the impact of interconnect structures on circuit performance. Such understanding is limited, though, because it deals only with geometric interconnect information and not with semiconductor process information. Furthermore, it is restricted to nominal geometric parameters and does not address the case when these parameters have statistical distributions as they do in practice. Progress has also been made in understanding the effect of the statistical distribution of geometric parameters on electric parameters, including their pairwise correlation, but such understanding still does not address the issue of the effect of semiconductor process parameters on electric circuit performance.
Those skilled in the art desire methods and apparatus that allow process engineers to develop an understanding of the effect of process parameters on electric circuit performance. Those skilled in the art particularly desire methods and apparatus that allow process engineers to develop an understanding of the expected statistical distribution of electric parameters resulting from a semiconductor fabrication process. This is particularly important because various applications for integrated circuits resulting from a semiconductor fabrication process may exhibit widely varying tolerances to electric parameters exhibited by the integrated circuits. For example, if an application for an integrated circuit requires that electric parameters exhibited by the integrated circuit fall within relatively narrow statistical distributions, a process engineer would like to know before expending time and expense in actually fabricating the integrated circuit whether a collection of process parameters specifying a process for making the integrated circuit will result in a suitable device. Likewise, if an application for an integrated circuit is relatively tolerant of electric parameter variation, a process engineer would like to understand how the relatively loose tolerances of the application can be translated into a process for making the integrated circuit that is not unduly precise given the application. Precision often translates into expense, and if precision is both expensive and unnecessary, then a process engineer would be interested in developing an understanding of how process parameters can be relaxed while still meeting the needs of the application.
The foregoing and other problems are overcome, and other advantages are realized, in accordance with the following embodiments of the invention.
A first embodiment of the invention is a method. In a step of the method, a computer interface is established. The computer interface is configured to accept process parameters for specifying at least one step in a semiconductor fabrication process. The computer interface permits a user to specify at least one of the process parameters as a statistical distribution. In another step of the method, the computer interface receives process parameters entered using the graphical user interface, wherein at least one of the process parameters is specified as a statistical distribution. In a further step of the method, digital processing apparatus converts the process parameters into an electric circuit model comprised of electric parameters, wherein at least one of the electric parameters is specified as a statistical distribution.
A second embodiment of the invention is a computer program product comprising a computer readable memory medium tangibly embodying a computer readable program. The computer readable program is configured to perform operations when executed by digital process apparatus. In a first operation, the computer program, when executed, causes a graphical user interface to be displayed on a display device of a computer. The interactive graphical user interface is configured to allow a user to specify process parameters concerning at least one step in a semiconductor fabrication process. The interactive graphical user interface is further configured to allow at least one of the process parameters to be specified as a statistical distribution. In another operation, the computer program, when executed, receives process parameters entered using the graphical user interface, wherein at least one of the process parameters is specified as a statistical distribution. In a further operation, the computer program, when executed, generates an electric circuit model comprised of electric parameters, wherein at least one of the electric parameters is specified as a statistical distribution.
A third embodiment of the invention is a system comprising: at least one computer memory; a computer program stored in the at least one computer memory, the computer program configured to perform semiconductor fabrication modeling operations when executed by digital processing apparatus; and digital processing apparatus coupled to the at least one memory. When the computer program is executed by the digital processing apparatus the system is configured to perform operations. In a first operation, the system displays on a display device a graphical user interface for specifying process parameters associated with at least one step in a semiconductor fabrication process. At least one of the process parameters is specified as a statistical distribution. In another operation, the system receives process parameters entered using the graphical user interface, wherein at least one of the process parameters is specified as a statistical distribution. In a further operation, the system generates an electric circuit model comprised of electric parameters, wherein at least one of the electric parameters is specified as a statistical distribution.
A fourth embodiment of the invention is a method. In a step of the method, process parameters are received. The process parameters specify a semiconductor fabrication process, and at least one of the process parameters is specified as a statistical distribution. In a further step of the method, the process parameters are converted into an electric circuit model comprised of electric parameters. At least one of the electric parameters is specified as a statistical distribution.
In conclusion, the foregoing summary of the various embodiments of the present invention is exemplary and non-limiting. For example, one or ordinary skill in the art will understand that one or more aspects or steps from one embodiment can be combined with one or more aspects or steps from another embodiment to create a new embodiment within the scope of the present invention.
The foregoing and other aspects of these teachings are made more evident in the following Detailed Description of the Invention, when read in conjunction with the attached Drawing Figures, wherein:
The invention teaches a method for evaluating the impact of semiconductor process parameters on the electric performance of semiconductor circuits such as, for example, circuit interconnects. In one embodiment, the invention directly links statistical distributions of the semiconductor process parameters of, for example, a multi-layered interconnect structure to statistical distributions of the electric parameters of the structure (e.g., capacitance and resistance). Process engineers who are not expert in the art of electrical analysis can readily use methods and apparatus of the invention to analyze the effect semiconductor process parameters have on electric parameters and to target the process parameters most responsible for loss of electrical performance in, for example, interconnect wiring structures. An embodiment of this invention has a graphical user interface adapted to the language used by semiconductor process engineers and a parallel processing feature that significantly speeds up the translation of the statistical distributions of process parameters into statistical distributions of electric parameters.
V=d
v
−e
v
Another relationship relates the metal height to the height of metal deposition, depth of metal polishing and height of the via below the metal layer in question:
H=d
m
−p
m−(dv−ev)
Similar relationships exist for composite geometric variables associated with the remaining layers. This invention uses the process parameters as primitive parameters.
In an embodiment of the invention, exemplary graphical user interfaces 210, 220 as depicted in
In an embodiment of the invention, the semiconductor process engineer can request an electric performance analysis from the computer program using another graphical user interface 300 as depicted in
The graphical user interface 300 also has a portion 330 for specifying views to assist in parameter selection. Process view is selected with radio button 332. In the process view, all parameters, both design and process parameters are shown. Geometric view is selected with radio button 334. In geometric views only geometric parameters are shown.
Once the user enters the parameters, the computer program maps the process parameters onto composite geometric parameters such as metal height and via height. Then it generates the geometric configurations from which electric parameters such as the resistance and capacitance of the metal structures are computed. Graphical user interfaces 410, 420 depicting a geometric configuration used for the calculation of capacitance are shown in
The result of all the capacitance calculations for all the samples is displayed in
A feature of this embodiment is parallel processing capability. Statistical sampling methods such as Monte Carlo techniques are computationally intensive and so require excessive execution time when run sequentially. It is an advantage of the present invention that Monte Carlo statistical analysis can be run in parallel on clusters of sequential computing machines.
Another advantage of this invention is a parallel processing feature that allows semiconductor engineers not skilled in the art of parallel computing to perform complex simulations.
The parallel processing feature enables another advantage of this invention, namely the advantage that the process engineer can evaluate the statistical impact of the variations of two or more process parameters on electric parameters. An important improvement of this invention with respect to the teachings of the prior art is that the primitive process parameters are uncorrelated and therefore correlation information of the type required by composite geometric parameters is not needed anymore.
Yet another advantage of the present invention is the visualization feature of the electric parameter as a function of the process parameters.
In various embodiments of the invention, the process parameters concern at least a deposition step; an etching step; or a polishing step.
The process parameters are used to create an electric circuit model in various ways. In one embodiment of the invention, the process parameters are used to derive composite geometric parameters. The composite geometric parameters are then used to generate a geometric model of the electric circuit. The geometric model of the electric circuit is then used to calculate the electric parameters. Field solvers can be used to calculate the electric parameters.
In a further embodiment of the method depicted in
When using a sampling procedure, in an embodiment of the invention the sampling procedure may be run in parallel on a cluster of sequential machines. In embodiments of the invention allowing the sampling procedure to be run in parallel on a cluster of sequential machines, a graphical user interface may be provided to control the sampling procedure. Although there are many possible implementations of a graphical user interface in accordance with this aspect of the invention, one exemplary embodiment of a graphical user interface comprises input fields for specifying: the number of sequential machines that will be used to perform the simulation; the number of simulations to be performed by each sequential machine; and the report interval for each sequential machine involved in the simulation.
In embodiments of the method depicted in
Embodiments of the method depicted in
In still further embodiments, converting the process parameters into an electric circuit model further comprises outputting the statistical distribution of the at least one electric parameter as a histogram or as a response surface.
One of ordinary skill in the art will understand that methods depicted and described herein can be embodied in a computer program storable in a tangible computer-readable memory medium or signal bearing medium. Instructions embodied in the tangible computer-readable memory or signal-bearing medium perform the steps of the methods when executed. Tangible computer-readable memory media include, but are not limited to, hard drives, CD- or DVD ROM, flash memory storage devices or in a RAM memory of a computer system.
In addition, apparatus can be configured to perform operations corresponding to those depicted and described with respect to
Thus it is seen that the foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the best apparatus and methods presently contemplated by the inventors for creating electric circuit models of semiconductor circuits from process parameters used to specify fabrication processes used to form the semiconductor circuits. One skilled in the art will appreciate that the various embodiments described herein can be practiced individually; in combination with one or more other embodiments described herein; or in combination with methods and apparatus differing from those described herein. Further, one skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments; that these described embodiments are presented for the purposes of illustration and not of limitation; and that the present invention is therefore limited only by the claims which follow.