Patent Application
20140173173
1. Field of the Invention
The present invention generally relates to a method, device, and system for timing control in memory devices. More particularly, a new command for a NAND flash memory permits different portions of the memory to have different bit-per-cell settings.
2. Description of the Related Art
Recent trend analysis show that NAND flash device pervasion within mass storage applications, such as USB (Universal Serial Bus) keys, memory cards, MP3 (MPEG-2 Audio Layer III) players, digital still cameras, mobile phones, solid-state drives, etc., is very large. These many different application scenarios imply several usage models of the device, needs for standardized buses, protocols, and command sets to easily connect this type of memory.
A standard which had been created during the last years and is diffusing more and more is the “eMMC” (embedded MultiMedia Card) standard. This eMMC specification is maintained by JEDEC (Joint Electron Devices Engineering Council), an organization that is a global leader in developing open standards for the microelectronics industry, and is designed to fit well with NAND flash memories within systems. This standard defines a device which incorporates both NAND Flashes and a controller. The protocol, the electrical layer and the package are also defined by the standards body.
Most of the systems currently using this device are aligned to the 4.3 specification of the standard published in November, 2007. Designers are now starting or proceeding to develop products compliant with the 4.4 version (March, 2009) and the 4.41 version (March, 2010). The protocol specification 4.3 (November, 2007) and, even more, the protocol specifications 4.4 (March, 2009), and 4.41 (March, 2010), introduced peculiar features and details for embedded use, making eMMC one of the most interesting memory solutions within mobile and digital consumer platforms.
According to a first exemplary embodiment, a method includes providing a partition command to a device that includes a memory array including a plurality of memory cells, partitioning, in response to the providing of the partition command, the memory cells of the memory array to select a portion of the memory array, and selecting, in response to the providing of the partition command, one of bit numbers that are to be stored in one memory cell, so that each of the memory cells included in the selected portion stores data with the selected one of the bit numbers.
According to a second exemplary embodiment, a device includes a first memory array including a plurality of memory cells, a second memory array storing a plurality of bit numbers each of which defines how many bit(s) is to be stored in one memory cell, a controller partitioning, in response to a partition command, the memory cells of the memory array to select a portion of the memory array, and the controller selecting, in response to the partition command, one of the bit numbers stored in the second memory, so that each of the memory cells included in the selected portion of the first memory stores data with the selected bit number.
According to still another exemplary embodiment, a system includes a memory storing data, a controller detecting a type of a storage application to which the memory and the controller are applied, the controller determining, in response to the detecting, a bit number to be stored in one memory cell and the controller further controlling the memory so that the memory stores data with the determined bit number.
One of the features of the aforementioned protocol specifications which have a major impact for a system is “Partition Management”, which enables the capability to split a device into several partitions, each supporting a specific usage model.
In order to address this feature, the present invention provides a solution implemented to support different bit-per-cell storing capability in different portions of a monolithic device.
Referring now to the drawings, and more particularly to
The memory device 100 includes a voltage down converter 101 which is connected to a power supply (VCC) input 102, and a power-on reset circuit 103. The device 100 also includes a command input circuit 104 which is coupled to synchronization pads for receiving a read enable signal (RE#), a write enable signal (WE#), and a chip enable signal (CE#), and is connected to control pads for receiving an address latch enable signal (ALE) and a command latch enable signal (CLE), and is connected to a pad for receiving a write protect signal (WP). The device also includes a command interface 105 which is connected to the command input circuit 104.
The command interface 105 and the power-on reset circuit 103 are connected to a microcontroller unit 106, and a microcontroller RAM 107 and ROM 108 are accessible by the microcontroller unit 106. The device 100 includes SRAM control logic 109 which receives an output of the command interface 105 and the microcontroller unit 106, and also includes read/write column control system 110 and read/write row control system 111 which receive an output of the microcontroller unit 106. The device 100 also includes row decoder 112, column decoder 113, and page buffers 114 which are connected to the matrix (e.g., memory array) 115. The memory array 115 includes redundancy/configuration 116 storing bits and a plurality of memory blocks (e.g., n-WL blocks) 117. The matrix 115 is also connected to block redundancy management 118 and column redundancy management 119.
The device 100 includes a read pipeline 120 which is connected to the column redundancy management 119 and the front end interface 121 of the SRAM 122, and receives an output of the SRAM control logic 109, and an output of the microcontroller unit 106. The device 100 also includes a write pipeline 123 which is connected to the front end interface 121 of the SRAM 122 and receives an output of the SRAM control logic 109 and an output of the microcontroller unit 106. The device 100 also includes data output buffers 124 which receive data which is output of the read pipeline 120 and data input buffers 125 which inputs data to the write pipeline 123. The device 100 also includes data strobe input buffers 126 which are connected to the data output buffers 124 and the data input buffers 125, and address input buffers 127 which input an address to the command interface 105 and the microcontroller SRAM 107. The data output buffers 124, data input buffers 125, data strobe input buffers 126, and address input buffers 127 are connected to data pads (DQ) for inputting data to the device and outputting data from the device.
The device also includes a reference voltage/current generator 128, and oscillators 129, charge pumps 130, and internal voltage regulators 131 which receive an output of the reference voltage/current generator 128.
Further, the various signals (e.g., VCC, RE#, WE#, CE#, ALE, CLE, WP and DQ) may be generated by a controller 601 in a system or a digital processing apparatus 600, for example, a memory card, cellular phone as indicated in
Each plane includes a page buffer 148 for its blocks 146. Each string 147 includes a number n of cells in series and two selectors SSG, SSD, one for source side and one for drain side. A multiplicity of strings are connected to the same bit line that is arranged on a first direction and the structure is then repeated on a second direction to reach the full page size, the first and second direction being perpendicular to each other.
A page is the portion of the array addressed at a time for reading and program operations and is structured by a plurality of cells which gates are coupled to one word line. As a result, each memory array is divided in a number N blocks each including at least one string for each bit line. In a few cases, even and odd bit lines can be addressed separately and belong to different pages, but a page is constituted of cells connected by the same word line. Blocks are addressed selectively and represent the minimum area of memory cells to be biased for each erase operation.
Next, the bit-per-cell management is explained. The present invention is based on a dedicated command which sets a NAND device in a defined bit-per-cell (b/c) configuration, freely chosen by the user: 1b/c, 2b/c, 3b/c, 4b/c, . . . , etc. This command relies on existing read/program/erase algorithms actually implemented in the device. Each bit-per-cell configuration has its own specification in terms of timing, cycling, retention, etc. The full NAND Flash array can be impacted by the change or a sub-portion of it, freely chosen by the user.
In one aspect of the present invention, the bit-per-cell configuration selected is applied for any of the following operations (including, but not limited to, Page Read, Page Program, Copyback Program, etc., and their Multi-plane versions). The bit-per-cell configuration that has been previously set is kept until a next coming erase operation is performed in response to issue of a next coming Erase command. It is not possible, for example, to read in a multi-bit-per-cell mode a block that has been previously set in a single-bit-per-cell mode, since the result would be unpredictable. As more specifically explained below, write and read operations are required to be performed the same bit-per-cell configuration as the b/c configuration that has been previously set, so that correct data can be written and then read.
In this view, the conventional NAND Flash has no record of such the bit-per-cell configuration of each block. In such conventional NAND, a bit-per-cell is set as a manufactured product of a NAND Flash device manufacturer. Therefore, a new setting of the bit-per-cell configuration cannot be obtained since the conventional NAND flash product is not configured to change the bit-per-cell configuration for that device.
In contrast to the conventional NAND Flash product, in the present invention, a setting of a bit-per-cell configuration, with its partitioning, is proposed. For example, after power-on, the bit-per-cell configuration is ready to be set and can be set. The bit-per-cell configuration that has been previously set may not be retained after power-off, but it is able to retain the bit-per-cell configuration by storing necessary data for this setting in a non-volatile manner. The bit-per-cell configuration that has been set can be reset in response to reset commands (i.e., Asynchronous Reset: FFh, Synchronous Reset: FCh, Reset LUN: FAh).
In NAND Flashes, there are two address types:
Furthermore, in the present invention, the same address information structure can be used to address a target logical unit, block, and page. For example, the target block to be accessed can be configured in different bit-per-cell settings. As explained above, the memory cells are composed in a page of a block (which is addressed by the lower part of the Row Address). The number of such memory cells of a page is determined according to type of memory device product.
In the present invention, the number of bits (i.e. bit-per-cell configuration) stored in one memory cell is chosen depending on the chosen bit-per-cell configuration, so that the total storage capability changes and is determined according to the chosen bit-per-cell configuration.
The NAND Flash host can issue the address with the correct number of bits to the NAND flash memory chip/device, taking into consideration the selected bit-per-cell configuration.
In the eMMC v4.41 protocol (JESD84-A441), a Multiple Partition Support is implemented. In Section 7.2 (Partition Management), the following statement is written:
In view of the above-recited passage from the eMMC protocol, an exemplary embodiment of the present invention can be summarized as follow:
Therefore, the partition management and the bit-per-cell management of the present invention can be compatible, implemented, and/or used so as to meet the requirements of the eMMC protocol and the ONFI specification.
Next, one exemplary implementation of the present invention is now described for the 32 Gb 32 nm MLC CT-NAND product.
The 32 Gb 32 nm MLC device has the following characteristics:
Next, the ONFI/JEDEC Set/Get Feature command is introduced, as follows. With these characteristics, the address definitions will be the following:
1. The Set Features function is a mechanism that the host uses to modify the settings for a particular feature. The bit-per-cell configuration change is performed with the Set Feature command.
2. The Get Features function is a mechanism that the host uses to determine the current settings for a particular feature. This function returns the current settings for the feature (including modifications that may have been previously made with the Set Features function).
In the above-mentioned
Next, the implementation of the present invention here is described:
P1: number of bit-per-cell (see Table 1);
P2: full device vs. portion of device (see Table 2);
P3: starting block address (see Table 3),
It is noted that in this exemplary implementation the “boundary” is expressed as a multiple of [Number_of_Blocks divided by 256 (decimal for FFh)];
P4: number of consecutive blocks (see Table 4),
In this exemplary implementation, blocks are always considered in pairs in order to facilitate Multi-Plane operations on the device.
It is noted that it should be clear that the various values in these tables permit a number of possibilities, such as exemplarily defined by various of the attached claims. Turning now to
Block 0 and Block 1 store data with one bit-per-cell, which means each of the memory cells in those blocks stores one bit information and has two threshold distributions such as “0” and “1” values. A write operation and a read operation on the Block 0 and Block 1 are performed with one bit-per-cell configuration. Other blocks 2 to 2047 are not used and not applicable (N/A) in this case.
Since 1 b/c has wider threshold voltage differences than 2b/c and 3b/c, and it has higher reliability than 2b/c and 3b/c, important information, boot information, control information, such information as used for operation another memory areas can be stored in such Block 0 and 1 with high reliability.
Blocks 16 to 2047 store data with two bits-per-cell, which means each of the memory cells in those blocks stores two-bit information and has four threshold distributions such as “00”, “01”, “10” and “11” values. Other Blocks 1 to 15 are not used and not applicable (N/A) in this case.
Blocks 16 and 17 store data with three bits-per-cell which means each of the memory cells in those blocks stores three bit information and has eight threshold distributions such as “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111” values. Blocks 0 to 15 and Blocks 18 to 2047 are not used and not applicable in this case.
In another aspect, it can be chosen as the combination of the above cases such that blocks 0 and 1 are with one bit-per-cell configuration, and blocks 16 and 17 are with three bits-per-cell.
In still another aspect, if the product has two planes sizes 4096 blocks, it can be chosen with wider blocks sizes than one plane 2048 blocks. For example, P3 is FFh (means 4080) and P4 is 02h (means 6 blocks). Also, P3 is 02h (means 32) and P4 is FFh (means 521 blocks).
In still another aspect, since the page access is applicable in a NAND flash memory, a boundary can be chosen as a page of the chosen block. In the example that one block has 256 pages, page 0 and page 1 of the block stores data respectively with two bits-per-cell. Other pages 2 to 255 of the block cannot be used, as N/A, and also, as a choice, pages 2 to 255 of the block can be used, for instance, with three bits-per-cell. In this way, several arrangements can be applicable in this invention.
ROM block 507, corresponding to ROM 7 in
The controller 506 performs the partition management and bit-per-cell management of the present invention. The partition management 508 manages what parts of the memory array are to be used. The part can be a block or a page. The bit-per-cell management 509 manages how many bit(s)-per-cell is to be stored in the selected parts of the memory array 501. The bit-per-cell is 1b/c, 2b/c, and 3b/c and so on.
In the write operation (in response to a write command), the controller 506 receives via DQ pins the address information as indicated by
In the read operation (in response to a read command), the controller 506 receives via DQ pins the address information such as indicated by
In order to implement operations in SLC (1b/c), MLC (2b/c), and TLC (3b/c) and so on, several writing pulses, write time period, step-up program pulses or the like can be chosen appropriately to perform a write operation, and several reference voltages can be chosen appropriately to perform a read operation.
For example, when the controller 601 detects the USB application 604, data to be written in the memory 603 or read from the memory 603 is performed with one bit-per-cell. Conversely, when the controller detects the memory card 605 application, data to be written in the memory 603 or read from the memory 603 may be two bits-per-cell. Identification of the storage application 602 may be implemented by grounding one or more control pins on a chip used to implement the system 600.
Also, in general, one bit-per-cell (SLC) may be more suitable to storing data that needs reliability rather than multiple bits-per-cell (MLC). That is, SLC may be robust due to the wider threshold windows of SLC than those of MLC. Thus, a bit number to be used for storing in the memory may be selected, based upon the desired reliability.
While the invention has been described in terms of an exemplary embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
Further, it is noted that, Applicants' intent is to encompass equivalents of all claim elements, even if amended later during prosecution.
