Patent Application
20090251213
The present invention relates, in general, to integrated circuits and, more particularly, to the threshold voltage of transistors in an integrated circuit.
Complementary Metal Oxide Semiconductor (CMOS) low voltage amplifiers are used in a variety of circuit applications including consumer electronics, telecommunications, automotive, aviation, etc. Typically these amplifiers are connected in a feedback configuration to linearly amplify a voltage difference that appears at their inputs. Like other integrated circuits, CMOS low voltage amplifiers are described in terms of various performance parameters, e.g., common mode input voltage, common mode rejection ratio, gain, slew rate, full-power bandwidth, input resistance, and output resistance, among others. Common mode input voltage range is an important performance parameter that indicates the range of input voltages over which a differential amplifier behaves in a linear fashion, i.e., the range of input voltages over which the amplifier can operate without any of the circuits of the individual gain stages within the amplifier entering a saturation operating mode. Common mode rejection ratio (CMRR) is a related performance parameter that is defined as the ratio of the open loop gain of the CMOS low voltage amplifier to its common mode gain. This performance parameter is a measure of the operational amplifier's ability to reject input signals that are common to both of the operational amplifier's differential inputs.
For CMOS low voltage operational amplifiers, it is desirable to maintain a high common mode rejection ratio over a wide range of common mode input voltages. This is a challenging goal because the processes for manufacturing CMOS low voltage amplifiers are typically suited for building field effect transistors having high threshold voltages.
Current source 16 comprises P-channel MOSFETS 30, 32, 34, and 36 coupled in a cascode configuration, wherein the drain of P-channel MOSFET 32 is coupled to source of operating potential VEE through a current setting resistor 38, and the drain of P-channel MOSFET 36 is connected to the sources of P-channel MOSFETS 20 and 22. The sources of P-channel MOSFETS 30 and 34 are commonly coupled for receiving a source of operating potential VCC. The gates of P-channel MOSFETS 30 and 34 are connected together and to the drain of P-channel MOSFET 32. The gates of P-channel MOSFETS 32 and 36 are connected together and for receiving a bias voltage VBIAS. In operation, the maximum common mode input voltage VCM,MAX that can be applied to differential pair 12 is given by equation 1 (EQT. 1):
V
CM,MAX
=V
CC−(|Vtho|+2*Vdsat) EQT. 1
For a 5 volt CMOS process in which the upper supply rail is 1.8 volts and the saturation voltage for the P-channel MOSFETS is about 100 millivolts, the maximum common mode input voltage, VCM,MAX, is about 0.8 volts.
The minimum common mode input voltage VCM,MIN that can be applied to differential pair 12 is given by equation 2 (EQT. 2):
V
CM,MIN
=V
EE
+V
DIFFLD
−|V
tho| EQT. 2
For the 5 volt CMOS process in which the lower supply rail is 0 volts and the voltage drop across differential pair load 14 is about 100 millivolts, the minimum common mode input voltage, VCM,MIN, is about −0.5 volts. Thus, the common mode input voltage range is about 1.3 volts.
A drawback with this circuit is that techniques for increasing the maximum common mode input voltage VCM,MAX have also increased the minimum common mode input voltage VCM,MIN. Because both the maximum and minimum common mode input voltages are increased, the common mode input voltage range is not increased.
Another parameter that limits the common mode range of a circuit such as, for example, an operational amplifier, is the threshold voltages of the transistors making up the circuit. When the threshold voltages of these circuits are large, parameters such as common mode range are degraded. This limitation also applies to other analog and digital circuits.
Accordingly, it would be advantageous to have a circuit and a method for increasing the common mode input voltage range. In addition, it would be advantageous for the circuit and method to adjust the threshold voltages of the transistors in the circuit. It would be of further advantage for the circuit and method to be time and cost efficient to implement.
The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which:
Generally, the present invention provides a method and a structure for adjusting the threshold voltages of transistors and increasing the common mode input voltage range of circuits such as, for example, operational amplifiers, comparators, microprocessors, controllers, sensors, drivers, or the like. It should be noted that the threshold voltages may be adjusted upward, i.e., increased, or downward, i.e., decreased. In accordance with an embodiment, the present invention comprises a method for changing a threshold voltage of a transistor by steering current through a resistance in response to an input signal, wherein the current varies a potential of a body region of a semiconductor material. It should be noted that the body region refers to the bulk of the semiconductor material in which a gate, source, and drain of a transistor are formed. For example, the body region of a P-channel device may be an N-well, i.e., a doped region of N-type conductivity in a semiconductor material, wherein the source and drains are formed in the N-well and the gate controls the formation of a channel between the source and drain regions that are formed in the N-well. The body region of an N-channel device may be a P-well, i.e., a doped region of P-type conductivity in a semiconductor material, wherein the source and drains are formed in the P-well and the gate controls the formation of a channel between the source and drain regions that are formed in the P-well. Alternatively, the body region may be a body of semiconductor material from which the source and drains of a transistor are formed wherein the gate controls the formation of a channel between the source and drain regions. The body of semiconductor material may be an epitaxial layer or a semiconductor substrate material.
In accordance with another embodiment of the present invention, a first current that flows along a first path in response to a common mode input voltage being greater than a reference signal is provided. The first current flows along a second path in response to the common mode input voltage range being less than the reference signal. When the first current flows along the second path, second and third currents are generated by taking the product of separate area multipliers and the first current. A fourth current is generated by amplifying or multiplying the second current with another area multiplier. A fifth current is provided that is used to make a first voltage greater than a voltage of a body or body region of a semiconductor material when the first current flows along the first path. The third, fourth, and fifth currents are used to make the first voltage less than the voltage of the body of the semiconductor material when the first current flows along the second path.
In accordance with another embodiment of the present invention, a circuit comprises a differential pair of transistors having commonly coupled sources. First and second current sources are coupled to first and second switches, respectively, through the commonly coupled sources, and third and fourth current sources are coupled to a bulk or body terminal of the operational amplifier through third and fourth switches, respectively. A common mode sense circuit is coupled to the commonly coupled sources and a bias resistor is coupled between the body terminal and the commonly coupled sources.
In accordance with another embodiment of the present invention, an operational amplifier comprises a differential pair of transistors having current carrying electrodes commonly connected together. A common mode sense circuit is connected to the commonly connected current carrying electrodes. A switching transistor is connected to the common mode sense circuit and the common mode sense circuit and the switching transistor are coupled to a current source. A bias resistor is coupled between the commonly connected current carrying electrodes and a body terminal.
It should be further noted that the gate of a transistor is also referred to as a gate electrode or a control electrode and the drain and source of a transistor are also referred to as the drain electrode and the source electrode or as current carrying electrodes.
As those skilled in the art are aware, in a standard CMOS process, each P-channel MOSFET has a gate, a source, a drain, and a bulk or body. A contact is made to the gate through a gate electrode or terminal, a contact is made to the source through a source electrode or terminal, a contact is made to the drain through a drain electrode or terminal, and a contact is made to the bulk or body through a body electrode or terminal. Typically, for every P-channel MOSFET that has a source, there will be a body connection.
A common mode sense circuit 128 is coupled to node 115. Common mode sense circuit 128 has a reference terminal coupled for receiving reference voltage VREF and a current sensing terminal connected to the sources of P-channel MOSFETS 104 and 106 and to one terminal of bias resistor 114 at node 115. In accordance with an embodiment of the present invention, common mode sense circuit 128 comprises a P-channel current sensing MOSFET 130 connected to a switch control circuit 131. P-channel sensing MOSFET 130 has a gate that serves as the reference terminal of common mode sense circuit 128, a drain that is coupled to a current sensing input of switch control circuit 131, and a source that is coupled to the sources of P-channel MOSFETS 104 and 106, and to one terminal of bias resistor 114 at node 115. Switch control circuit 131 has an output 133 coupled to switches 132 and 118 and an output 135 coupled to switches 136 and 122.
The source of P-channel MOSFET 130 is also coupled to one terminal of a current source 134 through a switch 132. The other terminal of current source 134 is coupled for receiving a source of operating potential VCC. Thus, the sources of P-channel MOSFETS 104 and 106 and one terminal of bias resistor 114 are coupled to current source 134 through switch 132. The sources of P-channel transistors 104, 106, and 130 and one terminal of bias resistor 114 are also connected to a terminal of a current source 138 through a switch 136 and the other terminal of current source 138 is coupled for receiving source of operating potential VCC. In addition, the sources of P-channel transistors 104, 106, and 130 and one terminal of bias resistor 114 are coupled for receiving source of operating potential VCC through a current source 140.
It should be noted that
Referring again to
Referring now to
Although CMOS low voltage operational amplifier 100 has been described using P-channel MOSFETS, this is not a limitation of the present invention.
Current multiplier circuit 208 comprises P-channel MOSFETS 210, 212, and 214 having gates that are commonly connected together and to the drains of P-channel MOSFETS 206 and 210 and sources coupled for receiving source of operating potential VCC. P-channel MOSFETS 210, 212, and 214 are sized to have source area multipliers D, B, and A, respectively. Preferably, the source areas of P-channel MOSFETS 212 and 214 are sized relative to the source area of P-channel MOSFET 210. Thus, the source area of P-channel MOSFET 210 is one or unity. The drain of P-channel MOSFET 214 is connected to body terminal 116. The drain of P-channel MOSFET 212 is coupled to a current multiplier circuit 218, which comprises N-channel MOSFETS 220 and 222. The source area of N-channel MOSFET 222 is sized to have an area multiplier equal to C, relative to the source area of P-channel MOSFET 210. The gates of N-channel MOSFETS 220 and 222 are commonly connected together and to the drain of N-channel MOSFET 220, which drain is connected to the drain of P-channel MOSFET 212. The drain of N-channel MOSFET 222 is connected to the sources of P-channel transistors 104, 106, and 130 and to one terminal of bias resistor 114. The sources of MOSFETS 220 and 222 are coupled for receiving source of operating potential VEE. The gates of P-channel MOSFETS 210, 212, and 214 are coupled for receiving source of operating potential VCC through a pull-up current source 224 and the gates of N-channel MOSFETS 220 and 222 are coupled for receiving source of operating potential VEE through a pull-down current source 226. Body terminal 116 is coupled for receiving source of operating potential VEE through a current source 228. Body terminal 116 is also connected to the body or body regions of P-channel MOSFETS 104 and 106.
In operation, common mode sense circuit 128 senses common mode input voltage VCM and compares it to a known reference voltage VREF. By way of example, voltage VREF is equal to a ground potential. In response to the common mode input voltage VCM being greater than voltage VREF, the voltages at the sources of P-channel MOSFETS 104 and 106 are greater than the body voltage (VBODY) of the semiconductor material from which CMOS low voltage operational amplifier 200 is fabricated. Under this condition P-channel MOSFET 130 is on and conducting current and N-channel MOSFET 206 is off and not conducting current. A current substantially equal to (I1−I2) flows towards node 230 to vary the potential of the body or body region of the semiconductor material or substrate from which the CMOS low voltage operational amplifier is manufactured. Preferably, current I1 is set to be greater than current I2. A bias current IT flows from current source 140 towards node 230 which is divided between P-channel MOSFETS 104 and 106 so that a current IT/2 flows from the sources to the drains of each P-channel MOSFET 104 and 106. Current (I1−I2) flows from node 230 through bias resistor 114, body contact 116, and current source 228 to source of operating potential VEE. The current generated by current source 228 is labeled current I3. Therefore current I3 is equal to current (I1−I2). The potential developed across bias resistor 114 by current I3 generates an input pair body-to-source potential (VBS) that is less than zero, i.e., the body-to-source potential, VBS, for transistors 104 and 106 is less than zero. Thus, steering current (I1−I2) through bias resistor 114 increases the body potential to be greater than the potential at the sources of transistors 104 and 106. This causes the effective threshold voltage (Vth) of input transistors 104 and 106 to be lower than their nominal value of Vtho, which increases the maximum common mode input voltage that can be achieved by CMOS low voltage operational amplifier 200.
It should be further noted that current sources 224 and 226 are included so that the gates of P-channel MOSFETS 210, 212, and 214 and the gates of N-channel MOSFETS 220 and 222 are not left floating when P-channel MOSFET 130 is on and conducting current and N-channel MOSFET 206 is off and not conducting current. More particularly, when P-channel MOSFET 130 is on and conducting current and N-channel MOSFET 206 is off and not conducting current, current source 224 provides a pull-up path to source of operating potential VCC and current source 226 provides a pull-down path to source of operating potential VEE so that the gates of P-channel MOSFETS 210, 212, and 214 are at potential VCC and the gates of N-channel MOSFETS 220 and 222 are at potential VEE. It should be noted that current sources 224 and 226 are optional components that may or may not be included with CMOS low voltage operational amplifier 200.
In response to common mode sense circuit 128 sensing the common mode input voltage VCM being less than voltage VREF, common mode sense circuit 128 in cooperation with current multiplier circuits 208 and 218, bias resistor 114, and current sources 202, 204, 224, 226, and 228, CMOS low voltage operational amplifier 200 changes the body voltage or potential (VBODY) of the semiconductor material from which CMOS low voltage operational amplifier 200 is fabricated to be higher than the voltage or potential at the sources of P-channel MOSFETS 104 and 106. Under this condition, P-channel MOSFET 130 is off and therefore not conducting a substantial current. N-channel MOSFET 206 is on and conducting current I2. Because N-channel MOSFET 206 is on and conducting current, it conducts substantially all of the current from current source 204. Current I2 flowing through N-channel MOSFET 206 is mirrored to P-channel MOSFET 212 and multiplied by area multiplier B. Thus, the current flowing from the drain of P-channel MOSFET 212 is B*I2. Here, current I2 is amplified by source area multiplier B. Similarly, current I2 flowing through N-channel MOSFET 206 is mirrored to P-channel MOSFET 214 and multiplied by area multiplier A. Thus a current equal to A*I2 flows from the drain of P-channel MOSFET 214 and is steered or directed to body terminal 116. Here, current I2 is amplified by source area multiplier A. The current flowing from the drain of P-channel MOSFET 212 is mirrored to N-channel MOSFET 222 and is multiplied by area multiplier C. Thus, a current equal to B*C*I2 flows through N-channel MOSFET 222. Here, current I2 is amplified by source area multipliers B and C. It should be noted that bias current IT flows from current source 224 and is divided between P-channel MOSFETS 104 and 106 do that a current IT/2 flows from the sources to the drains of each P-channel MOSFET 104 and 106. Using Kirchhoff's Current Law (KCL) at node 230 produces:
I
1
+A*I
2
−I
3
+I
T
−I
T/2−IT/2−B*C*I2=0 EQT. 3
I
1
+A*I
2
—I
3
−B*C*I
2=0 EQT. 4
I
1
+A*I
2
=B*C*I
2
+I
3 EQT. 5
Substituting EQT. 6 into EQT. 5 yields EQTS. 7-10:
I
3
=I
1
−I
2 EQT. 6
I
1
+A*I
2
=B*C*I
2
+I
1
−I
2 EQT. 7
A*I
2
=B*C*I
2
−I
2 EQT. 8
A*I
2
+I
2
=B*C*I
2 EQT. 9
B*C=A+1 EQT. 10
where:
I1 is the current flowing from current source 202;
I2 is the current flowing from current source 204;
I3 is the current flowing from current source 228;
A is the source area multiplier for P-channel MOSFET 214;
B is the source area multiplier for P-channel MOSFET 212; and
C is the source area multiplier for N-channel MOSFET 222.
Thus, CMOS low voltage operational amplifier 200 is designed such that current I3 equals the difference between currents I1 and I2 (i.e., I3=I1−I2) and the product of source area multipliers B and C equals the sum of one plus source area multiplier A (i.e., B*C=A+1). Operating under these conditions, a current equal to (A*I2−I3) flows from body contact 116 through bias resistor 114 to node 230. Here, source area multiplier amplifies current I2 by source area multiplier A. The potential developed across bias resistor 114 by current (A*I2−I3) generates an input pair body-to-source potential (VBS) that is greater than zero, i.e., the body-to-source potential, VBS, for transistors 104 and 106 is greater than zero. Thus, steering current (A*I2−I3) through bias resistor 114 decreases the body potential to be less than the potential at the sources of transistors 104 and 106. This causes the effective threshold voltage (Vth) of the input transistors 104 and 106 to be greater than their nominal value of Vtho, which decreases the minimum common mode input voltage that can be achieved by CMOS low voltage operational amplifier 200. Accordingly, CMOS low voltage operational amplifier 200 in accordance with embodiments of the present invention has a controlled bi-directional body biasing that causes the effective threshold voltage of P-channel MOSFET transistors 104 and 106 to change in such a manner to give amplifier 200 the widest common mode input voltage range while maintaining a good common mode rejection ratio.
Similar to CMOS low voltage operational amplifier 100, CMOS low voltage operational amplifier 200 may be modified such that P-channel MOSFETS 104, 106, 130, 210, 212, and 214 are replaced by N-channel MOSFETS and N-channel MOSFETS 206, 220, and 222 are replaced by P-channel MOSFETS, the polarities of the current sources, and the configurations of the switches to form a CMOS low voltage operational amplifier in accordance with another embodiment of the present invention.
By now it should be appreciated that a circuit and a method for changing the threshold voltages of the circuit's transistors have been provided. In accordance with embodiments of the present invention, an operational amplifier and a method for increasing the input common mode voltage range of the operational amplifier have been provided. In accordance with other embodiments of the present invention, current is steered or directed to controllably and bi-directionally change the body potential of the semiconductor material or substrate from which the operational amplifier is fabricated. The common mode input voltage range is widened or increased by decreasing the effective threshold voltages of the input transistors of the operational amplifier when the common mode input voltage is greater than a reference voltage and increasing the effective threshold voltages of the input transistors of the operational amplifier when the common mode input voltage is less than the reference voltage. A current is steered or directed in one direction through a resistor when the common mode input voltage is greater than the reference voltage and another current is steered or directed in an opposite direction through the resistor when the common mode input voltage is less than the reference voltage. Steering the current through the resistor changes the potential of the body or body region of the semiconductor material or substrate from which the operational amplifier is manufactured, which changes the effective threshold voltages of the input transistors of the operational amplifier.
Although certain preferred embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.
