Claims
- 1. A method of sequentially testing a plurality of functional blocks having data ports within an integrated circuit having external circuit connectors using isolation circuits that are substantially transparent during normal operation of the integrated circuit, comprising the steps of:
- a) assigning designations to the functional blocks to be tested;
- b) selecting the external circuit connectors of the integrated circuit to which respective ports of each of the functional blocks to be tested are to be connected for testing;
- c) for each selected external connector, embedding a first multiplexer in the integrated circuit for multiplexing system signals in the integrated circuit with test signals associated with testing the functional blocks, said first multiplexer having a select port;
- d) controlling the select port of the first multiplexer with a signal which identifies whether or not the integrated circuit is in a test mode;
- e) for each selected pad and each set of two or more functional blocks that are to be connected to the pad for testing, embedding in the integrated circuit a second multiplexer circuit having a select port and an output port, with the output of the second multiplexer circuit connected to the first multiplexer; and
- f) simultaneous with step d), controlling the select port of the second multiplexer circuit with a signal which uniquely identifies the functional block to be tested;
- whereby each functional block, when identified as the functional block to be tested, is connected through said first and second multiplexers directly to a selected external circuit connector.
RELATED APPLICATION
The present application is a of co-pending application Ser. No. 07/824,892, filed in the United States Patent and Trademark Office on Jan. 22, 1992, now abandoned, which is a continuation of application Ser. No. 07/658,415, filed in the United States Patent and Trademark Office on Feb. 15, 1991, now abandoned, which is a continuation of application Ser. No. 07/340,325, filed in the United States Patent and Trademark Office on Apr. 18, 1989, now abandoned, all of which are commonly assigned herewith, and the disclosures of which are incorporated herein in their entirety.
US Referenced Citations (10)
Non-Patent Literature Citations (1)
Entry |
Samad et al., "A Methodology for the Test of Embedded Compiled Cells", IEEE Custom IC Conference, May 1988, pp. 16.7.1-16.7.3. |
Continuations (2)
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Number |
Date |
Country |
Parent |
658415 |
Feb 1991 |
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Parent |
340325 |
Apr 1989 |
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Continuation in Parts (1)
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Number |
Date |
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Parent |
824892 |
Jan 1992 |
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