Method for changing electrically programmable read-only memory devices

Abstract

A process for introducing negative charge onto the floating gate of an EPROM or EEPROM device is disclosed. The process uses CHISEL conditions to introduce charge onto the floating gate. The threshold voltage of the device is controlled by selecting a control gate voltage during programming that is less than 10 volts and that will provide a device with the desired threshold voltage. The device is then programmed using the selected control gate voltage and a negative substrate bias.

Description

TECHNICAL FIELD

The invention is directed to a method for charging electrically programmable read-only memory (EPROMs and EEPROMs) devices to a desired logic state.

BACKGROUND OF THE INVENTION

A nonvolatile memory is a type of memory that retains stored data when power is removed. There are various types of nonvolatile memories, including read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). An EPROM is erased using ultraviolet light and an EEPROM is erased using an electrical signal. An electrical signal is used to write EPROMS and EEPROMS. In a conventional flash EEPROM ("flash" indicating all memory cells or sectors of cells can be erased at once), memory cells are simultaneously erased to a low threshold voltage and then programmed, either individually or in small groups, to a high threshold voltage. EPROMs and EEPROMs are commonly used in data processing systems that require a nonvolatile memory that is reprogrammable. For convenience, EEPROMs and EPROMs are referred to collectively herein as EPROMS.

A typical device structure for EPROMS is the floating-gate polysilicon transistor. A typical floating gate structure is illustrated in FIG. 1. As depicted in FIG. 1, a floating gate 10, sandwiched between two insulator layers 20 and 60, is between the substrate 30 and the ordinary select-gate electrode 40. The structure depicted in FIG. 1 is a stacked gate memory cell, the word stacked indicating that the floating gate 10 is stacked over the source 50 and drain 70 portions of the substrate. Another EPROM structure is a split gate structure wherein the portion of the floating gate only overlies the drain and no portion of the floating gate overlies the source. Split gate EPROM device structures are described in U.S. Pat. No. 5,349,220, to Hong which is hereby incorporated by reference. As a result, in EPROMS, the select-gate voltage must be capacitively coupled in series with the floating gate rather than directly to the underlying channel.

There are n-channel and p-channel devices with the above structures. In the n-channel devices, the source and drain are doped with an n-type dopant and the substrate is doped with a p-type dopant. In p-channel devices, the source and drain contain p-type dopant and the substrate contains n-type dopant. In silicon based substrates, such as silicon or silicon germanium (SiGe) alloys, an example of a p-type dopant is boron and examples of suitable n-type dopants are arsenic and phosphorous.

EPROMS are programmed by applying a set of bias voltages to the device dLepicted in FIG. 1. The voltage applied to the select-gate (hereinafter referred to as a control gate) is V.sub.C, the voltage applied to the drain is V.sub.D, and the voltage applied to the source is V.sub.S. Voltage differences, typically referred to as biases, between these various terminals are designated in the following manner: e.g., V.sub.CS =V.sub.C -V.sub.S etc. In n-channel devices writing biases are used to introduce additional negative charge onto the floating gate, thereby writing the cell. However, if the charged state is chosen as the "unwritten" state, introducing additional negative charge onto the floating gate will erase the cell. Bias conditions that are used to introduce a more negatively charged state are different from bias conditions that are used to read the charged state or to create a more positively charged state.

These write biases are typically a high control gate-to-source voltage (V.sub.CS) and/or a high drain-to-source voltage V.sub.DS. These programming voltages are sufficient to cause a transfer of electrons from the bulk of the device (channel 80 and/or source 50 and/or drain 70) region to the floating gate 10 where they are trapped, thereby charging the floating gate more negatively. Charge is trapped in the floating gate 10 because the floating gate is isolated from the select-gate 40 by an insulating oxide layer 60 and from the drain-source-substrate region by another thin oxide insulating layer 20. The effect of trapping electrons on the floating gate is to raise the threshold voltage (V.sub.TH) to some predetermined level. Furthermore, these programming voltages are outside of the range of normal reading bias conditions so that an inadvertent write does not occur during reading.

EPROMS typically include an array of floating-gate transistors. The V.sub.TH of a given cell can be determined by a sense amplifier when read and decoded into its logic value. For example, in a conventional two-state memory, a high V.sub.TH which has been achieved by writing as described above is decoded as a logic one, and the intrinsic V.sub.TH (the V.sub.TH of a device which has not been written by adding negative charge to the floating gate 10) is decoded as a logic zero. Because the floating gate is isolated, the cell can remain programmed or erased for periods of up to 10 years and even longer.

However, certain problems are encountered when erasing and writing memory cells in arrays of memory devices configured in a common architecture known as a NOR array. A NOR architecture consists of a plurality of EPROM devices. In a NOR architecture, at least four devices are arranged such that there is a sequence of devices in two directions. The sequence of devices in the first direction are referred to as rows of devices and the sequence of devices in the second direction are referred to as columns of devices. A NOR array requires that there be at least two rows of devices and at least two columns of devices. Furthermore, in a NOR array, each column of devices has its own dedicated bit line and the drains of the devices in a given column are connected to the same bit line. Still further each row of devices has its own word line, and the gates of the devices in a given row are all connected to the same word line. The sources are connected to a source voltage (V.sub.S) supply.

Prior to the introduction of charge onto the floating gates of the cells in a NOR sub-array of memory cells, all of cells in the sub-array are erased. When a NOR array of memory cells is erased, the V.sub.TH distribution in the memory will be about 2 volts wide. This requires the erase to be carefully controlled to avoid "over-erasing" cells. A cell is over-erased when its V.sub.TH is less than zero. A cell with a V.sub.TH that is less than zero cannot be unselected during read. Such a cell cannot be left in this state because it adversely affects the operation of the array. All cells in the array must have a V.sub.TH that is sufficiently greater than zero to be unselected by application of a V.sub.CS equal to zero. Therefore, to the extent that cells are over-erased in a NOR array, those cells must be reprogrammed to a V.sub.TH greater than zero by a convergence technique. These over-erased cells cannot be written controllably using conventional channel hot electron injection techniques for introducing charge onto the floating gate because cells with a V.sub.TH less than zero contribute large bit-line leakage, which makes it difficult to supply the V.sub.DS required to write the cells. Furthermore, even if one or more of these over-erased cells are written, it is possible that unselected cells will be written in the process.

One method that is employed to introduce negative charge into the floating gate is channel hot electron injection (CHEI). The objective of CHEI is to heat electrons in the channel to high enough energies so that they enter the conduction band of the oxide layer 20, pass through it, and enter the floating gate 10. In CHEI the electron current which charges the floating gate (I.sub.F) is initiated by the electron current flowing from the source to the drain (I.sub.DS)--If I.sub.DS goes to zero, then IF goes to zero and, as a result, more negative charge is not introduced into the floating gate.

However, in order to introduce a charge onto the floating gate of a EPROM device by CHEI, a V.sub.CS typically greater than about 10 volts is required. Such a high V.sub.CS provides a correspondingly high V.sub.TH. The only way to write a device to a V.sub.TH that is less than the value that corresponds to a high V.sub.CS is to monitor the charge on the floating gate during programming and cease programming when the desired V.sub.TH is reached. Because such monitoring is cumbersome and time-consuming, a more efficient method for programming EPROM devices to a desired V.sub.TH is desired.

SUMMARY OF THE INVENTION

The present invention is directed to electrically programmable memory devices such as EPROMs and EEPROMs (referred to collectively as EPROMs) herein, and a method for introducing negative charge on the floating gate using channel initiated secondary electron injection (CHISEL). The present invention is also directed to a method for programming an array of memory devices using CHISEL.

A CHISEL device is a semiconductor n-channel device formed on a substrate having a source region and a drain region therein. A first layer of dielectric material is formed on the substrate and a floating gate electrode is formed on the first layer of dielectric material. At least a portion of the floating gate electrode overlies the drain region in the substrate. A second layer of dielectric material is formed on the surface of the floating gate electrode. A control gate electrode is formed on the on the first layer of dielectric material, lying above the entire channel length from the source to the drain.

Negative charge is introduced onto the floating gate using CHISEL by applying a negative substrate-source bias voltage (V.sub.BS) of about -0.5 volts or more negative, a control gate-source bias (V.sub.CS) of about 10 volts or less, and a drain-source bias voltage (V.sub.DS) of less than about 5 volts to the device. By way of definition, the voltage applied to the substrate is V.sub.B. The current that charges the floating gate is initiated by the electron current from the source to the drain. In embodiments of the present invention where programming times of about 1 to about 100 .mu.sec (1.times.10.sup.-6 seconds) are desired, VDS is about 4.5 volts or less and V.sub.BS is about -0.5 volts to about -4 volts.

Since the larger the V.sub.DS, the larger the substrate leakage current, it is advantageous to use a V.sub.DS of less than about 3.5 volts if programming times of 10 .mu.sec to about 100 .mu.sec are satisfactory. Also, in order to reduce the chance that a cell in the array will be erroneously programmed when writing other cells on the same bit line, it is advantageous if V.sub.BS is about -0.5 volts to about -3 volts.

In the method of the present invention, because CHISEL programming is self limiting to a low V.sub.TH using a low V.sub.CS, programming is accomplished by selecting a V.sub.CS that corresponds to a desired V.sub.TH and applying that V.sub.CS for a period of time sufficient to program the device to the desired V.sub.TH. Thus, in the method of the present invention, a V.sub.CS of less than 10 volts that is associated with a desired V.sub.TH is selected and applied to the device during programming for a time sufficient to introduce negative charge onto the floating to provide the device with the desired V.sub.TH. Consequently, the method of the present invention permits a device to be programmed by selecting a V.sub.CS that corresponds to a desired V.sub.TH. It is contemplated that it will not be necessary to monitor V.sub.TH during programming because, under the selected programming conditions, the actual V.sub.TH does not increase significantly over the desired V.sub.TH over time. In effect, the device quits programming (i.e. the negative charge on the floating gate does not increase significantly over time) once the desired V.sub.TH is reached. It is advantageous to use the CHISEL programming method of the present invention to program flash EPROM devices in a NOR architecture. However, statistical variations between devices dictates that a set of devices programmed with V.sub.CS will have a spread of V.sub.TH around the desired value. In certain embodiments, the devices are monitored in order to achieve the desired accuracy for V.sub.TH in all devices. In the context of the present invention, V.sub.CS is selected either by applying a predetermined V.sub.CS or by measuring V.sub.TH during programming and selecting a V.sub.CS in response to that measurement.

The V.sub.TH of a device is the voltage that must be applied in order for drain current (I.sub.D) to flow from the device. In the operation of memory devices, when a detectable I.sub.D flows from the device, the device reads as on. Consequently, when I.sub.D is not detectable, the device reads as off. One skilled in the art will appreciate that the amount of drain current needed for the device to register as on will depend upon the sensitivity of the sense amplifier being used to detect I.sub.D.

In an array of devices with multi-logic states, as the name implies, there are more than two logic levels. Each level is associated with a particular threshold read voltage (V.sub.TH-RD-0, V.sub.TH-RD-1, V.sub.TH-RD-2, . . . V.sub.TH-RD-n) where V.sub.TH-RD-n is less than V.sub.TH-RD-0, V.sub.TH-RD-n+1 where n is a non-negative integer. The notation V.sub.TH-RD is used to define a threshold which depends on the current level required by the sense-amplifier being used. It is related to, but different from the standard device V.sub.TH. For example, devices programmed to have a threshold voltage V.sub.TH-RD-0 read as "on" when a control gate voltage at or above V.sub.TH-RD-0 is applied to the device. Devices programmed to have a threshold voltage at V.sub.TH-RD-n read as "on" when a control gate voltage at or above V.sub.TH-RD-n is applied to the device but read as "off" when a V.sub.CS below V.sub.TH-RD-n is applied to the device, etc. According to the method of the present invention, it is possible to select a V.sub.CS of less than about 5 volts to program to both V.sub.TH-RD-0 or V.sub.TH-RD-1 provided that V.sub.TH-RD-1 is suffciently greater than V.sub.TH-RD-0).

In a binary device, i.e. a device with two logic states, the on state is a first logic state (e.g. logic zero) and the off state is a second logic state (e.g., logic one). Devices programmed to have a zero-state V.sub.TH-RD below the read voltage, V.sub.RD, read as on when a control gate voltage, V.sub.CS, at or above the V.sub.RD is applied to the device. Devices programmed to have a first order V.sub.TH-RD above the read voltage, V.sub.RD, read as off when the V.sub.RD is applied to the device.

In the method of the present invention, the devices (or a collection of devices in a sub-array desired to be subsequently written) are erased by applying a fixed erase pulse in which either V.sub.CS, V.sub.CD, or V.sub.CB are sufficiently negative to cause tunnel erasure of the floating gate until the threshold voltage of all of the devices in the array are less than the zero order threshold voltage of the device (V.sub.TH-RD-0). The memory cells are then programmed using the following conditions: a negative substrate-source bias voltage (V.sub.BS ) of about -0.5 volts to about -4 volts, a control gate-source bias (V.sub.CS) of about 10 volts or less that is selected to provide the device with a desired threshold voltage, V.sub.TH-RD-n, and a drain-source bias voltage (V.sub.DS) of less than about 4.5 volts. Typically, at least one of the cells in the array will be programmed to a logic state higher than V.sub.TH-RD-0. The V.sub.CS selected to program selected cells to a higher order (n) logic state is, at a minimum, at least 0.1 volt higher than the V.sub.CS used to program to the next lower logic level V.sub.TH-RD-(n-1). It is advantageous if the V.sub.CS that provides V.sub.TH-RD-n is at least 0.25 volts higher than the V.sub.CS that provides V.sub.TH-RD-(n-1). Since the present invention contemplates both positive and negative voltages, higher (lower) means either more (less) positive or more (less) negative. In certain embodiments it will be advantageous if the V.sub.CS that provides V.sub.TH-RD-n is at least 1 volt greater than the V.sub.CS that provides V.sub.TH-RD-(n-1).

Such variety and flexibility in selecting V.sub.TH-RD is not afforded by prior art methods for programming EPROM devices. For example, in CHEI, V.sub.CS must be high (e.g. 10 volts) to program the device. Because V.sub.CS is required to be so high, V.sub.TH-RD increases rapidly as a function of time through a wide range of lower V.sub.TH (e.g., voltages in the 1 to 5 volt range) before beginning to level off. Thus, the only way to program an EPROM device to a low V.sub.TH-RD (e.g. threshold voltages in the range of about 1 volt to about 5 volts) is to monitor the V.sub.TH of the device during programming and to interrupt programming when the desired V.sub.TH-RD is reached. Because V.sub.TH is increasing rapidly as a function of time, it is difficult to program an EPROM device to a low V.sub.TH-RD using CHEI. Also, the natural over-erase protection afforded through CHISEL to write the zero-state permits programming a lower zero-state V.sub.TH-RD than in CHEI. In CHISEL devices, V.sub.TH-RD-0 is as low as 0.4 volts and V.sub.CS is as low as 1.5 volts. In CHEI, the zero order V.sub.TH-RD state is typically higher than the highest V.sub.TH-RD of the devices in the array after erasure. The higher zero-order V.sub.TH-RD is required for CHEI devices in order to avoid over-erasure, which requires that the lowest erased V.sub.TH-RD be greater than zero. Since the distribution of erased V.sub.TH 'S in an array of CHEI devices is about 2 volts wide, the V.sub.TH-RD-0 is about 2 volts and, typically, CHEI devices have a V.sub.TH-RD-0 that is greater than 2 volts.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a floating gate memory device.

FIG. 2 is a graph of the change in threshold voltage as a function of time for CHISEL devices at various V.sub.CS.

FIG. 3 illustrates threshold voltage of a device programmed using CHEI as a function of time compared to CHISEL.

FIG. 4 illustrates the relationship between V.sub.DS and programming time in the process of the present invention.

DETAILED DESCRIPTION

The present invention is directed to a process for programming floating gate memory devices, specifically EPROM devices. The devices are programmed using CHISEL. The method of the present invention utilizes the self-limiting aspect of CHISEL to introduce charge onto the floating gate in a more efficient manner than in prior art methods for introducing charge onto the floating gate.

As previously noted, certain conditions are required to introduce negative charge onto a floating gate (introduction of a negative charge onto a floating gate is referred to as writing the floating gate or programming the floating gate herein) of an EPROM device using CHISEL. In the method of the present invention, a V.sub.CS in the range of about 1.5 volts to less than about 10 volts that corresponds to the desired threshold voltage of the device is selected to program the device. As previously noted, in an array of devices, typically some of the devices are programmed to correspond to a first logic level and some of the devices are going to be programmed to at least a second logic level. One skilled in the art will appreciate that the number of logic levels can exceed two.

Programming cells in a NOR array requires raising the voltage of a selected word-line to the desired V.sub.CS and applying a V.sub.DS (1.1 volts<V.sub.DS <5 volts) to the bit lines of the cells being programmed. The word lines of unselected cells and unselected bits have V.sub.CS =0 and V.sub.DS =0, respectively. Typically, one word line in an array is selected at a time during programming (i.e. when data is being written). However, in some embodiments when the zero state V.sub.TH-RD is being programmed, several, but less than all, word lines in the array (typically less than 10) are selected simultaneously during programming. The number of selected word lines is kept low in order to keep the programming current through a given bit line low.

In the method of the present invention, the devices in an array are erased prior to programming using the following conditions: either V.sub.CS, V.sub.CD, or V.sub.CB is less than zero (e.g., V.sub.CB is approximately equal to -17 volts to erase the devices in less than one second). Then, in the embodiment of the invention wherein the EPROM devices are stacked gate devices, all of the devices in the array are programmed to a desired logic level by introducing sufficient negative charge onto the floating gate that corresponds to the zero order threshold voltage. In the embodiment of the present invention wherein the EPROM devices are not stacked gate devices, the devices are erased to V.sub.TH-RD-0. Only those non-stacked gate devices that are desired to be programmed to a logic state higher than V.sub.TH-RD-0 are subsequently written.

The zero order threshold voltage is at least about 0.4 volts but is less than the first order threshold voltage (and higher order threshold voltages, if any). All threshold voltages are less than 10 volts. An nth order threshold voltage is less than an n+1 threshold voltage.

The device or devices are programmed by applying a V.sub.CS to the device that is less than 10 volts but greater than zero volts. The V.sub.BS is about -0.5 volts or more negative. The V.sub.DS is less than about 5 volts. V.sub.CS is selected to provide the devices with a desired threshold voltage V.sub.TH-RD-n, wherein n is zero or a positive integer.

In the context of programming by CHISEL, a V.sub.CS that will program a device to a desired V.sub.TH-RD-n is readily determined because there is a linear relationship between the required V.sub.CS and the combined value of V.sub.TH-RD-n and a constant related to the body effect shift due to the negative V.sub.BS used to write the device. One skilled in the art will appreciate that the body effect is the relationship between the substrate bias and the threshold voltage of the device. In most cases, the body effect of the device requires that V.sub.CS be higher than V.sub.TH-RD-n. How much higher will depend upon the body effect for a particular device, the V.sub.BS applied to the device during programming, and the I.sub.DS required to read a cell as on which is readily determined by one skilled in the art. For the devices and programming conditions of the present invention, a body effect of about 1 volt to about 2 volts is expected. The body effect is advantageous because it effectively precludes the possibility that stacked-gate devices in a NOR array will be over-erased. This is because the threshold voltage of the device is shifted upward by the value of the body effect. Thus, the problems associated with over-erasure of devices programmed by CHEI are not present in devices programmed by CHISEL. This allows V.sub.TH-RD-0 to be set lower than in prior art stacked gate devices in a NOR array as noted previously.

Once a V.sub.CS is selected for a desired V.sub.TH-RD-n, the device is programmed by the application of that V.sub.CS to the device. Programming is a dynamic process, i.e., over time, the threshold voltage of the device during programming (V.sub.TH-PROG) increases until the desired threshold voltage V.sub.TH-RD-n is reached. In order to continue to introduce charge onto the floating gate, V.sub.CS at any given time (t) must be greater than V.sub.TH-PROG (t). Following from the prescribed relationship between V.sub.CS and V.sub.TH-PROG (t) is the ability to change the V.sub.CS during programming. This is advantageous because it provides the ability to reduce the drain current, I.sub.D, during programming.

Specifically, I.sub.D is proportional to the square of the difference between V.sub.CS and V.sub.PROG (t) and a constant related to the body coefficient. Therefore, if the difference between V.sub.CS and V.sub.PROG (t) is controlled during programming by beginning with a V.sub.CS less than that desired, and increasing it to the desired value during programming instead of using one value for V.sub.CS during the programming cycle, I.sub.D is reduced during the programming cycle. Because CHISEL is more efficient when V.sub.CS -V.sub.TH-PROG is small, I.sub.D can be decreased in this manner without much effect on programming time. Efficient programming in this manner can be achieved in less than 10 .mu.sec using V.sub.DS =3.5 volts, V.sub.BS =-3 volts and with an I.sub.D of less than 20 .mu.A. Programming in this manner requires that V.sub.CS (t) be maintained larger than V.sub.PROG (t) in order to introduce charge onto the floating gate. However, V.sub.CS (t) must also be less than or equal to the V.sub.CS associated with the desired logic level, V.sub.TH-RD-n, being written in order to avoid programming a device to a different threshold voltage (e.g. V.sub.TH-RD-(n+1)) that is different than the desired V.sub.TH-RD-n. In one embodiment of the present invention, V.sub.CS (t) is a stepped function in which V.sub.CS is incremented through discrete levels.

There are numerous advantages to controlling I.sub.D during programming. Specifically, if I.sub.D is smaller during programming, it is easier to charge-pump the drain voltage from a lower power supply voltage and get the desired V.sub.DS. Furthermore, since programming power is proportional to I.sub.D, programming power is reduced by reducing I.sub.D. Also, series resistance loss from contact and bit lines is reduced by reducing I.sub.D for the devices during programming. However, this constraint does not mandate that V.sub.CS be varied throughout the programming cycle.

As previously noted, programming the floating gate using the CHISEL mechanism is self-limiting during programming with a V.sub.CS of less than about 10 volts. In the context of the present invention, self-limiting means that, after a certain time at a certain V.sub.CS, the threshold voltage of a device does not increase significantly. For example, when V.sub.CS-0 is applied to the device, once the V.sub.TH of the device reaches V.sub.TH-0, the threshold voltage of the device does not continue to increase significantly. FIG. 2 is a graph of the change in threshold voltage as a function of time for CHISEL devices at V.sub.CS of 2.25 volts, 3.75 volts, and zero volts. FIG. 2 illustrates that devices program to a particular threshold voltage for a given V.sub.CS, and, once that threshold voltage is reached, the threshold voltage does not increase significantly even if programming continues. The increase of V.sub.TH-RD as a function of time was measured for an EPROM device with a channel length of 0.25 .mu.m, a V.sub.DS of 3.3 volts and a V.sub.BS of -3 volts.

The dashed line in FIG. 2 illustrates the observed increase in V.sub.TH-RD as a function of time. The V.sub.TH-RD increased from -0.1 to about 1.1 V at time T (2.times.10.sup.-5 sec) when a V.sub.CS of 2.25 volts was applied to the device. The self-limiting aspect of the method of the present invention is illustrated by the fact that, after time T, V.sub.TH-RD no longer increases significantly. The programming current of the devices programmed under the conditions described in FIG. 2 had a measured maximum of 100 .mu.A/.mu.m and an average of about 60 .mu.A/.mu.m. When programming devices using CHEI, a programming current of about 1 mA/.mu.m is typically required. The body-effect aspect of CHISEL programming is illustrated by the fact that the cell does not program when V.sub.CS is zero, even though V.sub.TH was less than zero. Also essentially no cell current (i.e. current less than about 100 pA/.mu.m) is generated when V.sub.CS is less than zero. This is because the actual V.sub.TH-RD of the device at time zero was -0.1 volts plus the body effect, which, for the device described in FIG. 2, was about 1 volt. Furthermore, the V.sub.TH-RD-0 of the CHISEL device was 1.1 volt, yet the cell was not overerased

The fact that a particular V.sub.CS provides the device with a particular V.sub.TH-RD is also demonstrated by FIG. 2. Both lines with circles illustrate the V.sub.TH-RD of devices that were programmed at a V.sub.CS of 3.75 volts. One device had a V.sub.TH-RD of -0.1 volts at time to and one device had a V.sub.TH-RD of 1.8 volts at time t.sub.0. FIG. 2 demonstrates that both devices programmed to the same V.sub.TH-RD at time T. This indicates that V.sub.TH-RD is a function of the V.sub.CS applied to the device during programming independently of the initial state before programming.

In conventional methods for introducing a charge onto the floating gate, the programming cycle must be monitored to determine when sufficient negative charge has been introduced onto the floating gate to provide the device with the desired V.sub.TH. Monitoring is required because the negative charge introduced onto the floating gate is a function of time and the threshold voltage to which the device has been erased. One skilled in the art is aware that a block of FLASH memory devices are erased before the devices are programmed to their desired logic states and that there is some variation in the threshold voltage of the erased devices. Furthermore, in prior art methods for programming a memory device (i.e. CHEI as previously described), a V.sub.CS of at least 10 volts is required to introduce negative charge onto the floating gate. Under such conditions, the only way to control the V.sub.TH of a particular device is to monitor the device periodically during programming to determine its V.sub.TH. When the measured V.sub.TH is equal to the desired V.sub.TH, programming is complete.

FIG. 3 illustrates threshold voltages of devices programmed using CHEI as a function of time. V.sub.CS is 10 volts for the CHEI programming cycles illustrated in FIG. 3. These programming cycles were measured by programming devices using a V.sub.BS of 0 volts. The channel length of all the devices described in FIG. 3 was 0.25 .mu.m. As illustrated by the dashed lines in FIG. 3, for V.sub.DS of 4 volts, 4.5 volts, and 5 volts, the V.sub.TH-RD of the CHEI devices continued to significantly increase above 2.5 volts. In order to program using CHEI, a large V.sub.CS (e.g. 10 volts) is required. FIG. 3 illustrates that the threshold voltages of the devices programmed by CHEI continue to increase as a function of time. The solid line in FIG. 3 illustrates the threshold voltage as a function of time of a device being programmed by CHISEL. The device was programmed by applying a V.sub.CS of 2.5 volts and a V.sub.BS of -3 volts to the device. The solid line demonstrates that the threshold voltage of a device programmed by CHISEL did not increase significantly above 2.5 volts. Furthermore, the CHISEL-programmed device reached this threshold voltage in about 4.times.10.sup.-6 seconds when a V.sub.DS of 3.75 volts was applied to the device. A V.sub.DS of 5 volts and a V.sub.CS of 10 volts was required to program the device to 2 volts in a comparable time using CHEI.

The present invention is also directed to a method for programming flash EPROM devices in times less than 100 .mu.sec. Programming times of less than 100 .mu.sec, even as low as 10 .mu.sec, are required to write large memories (1 Mbit or larger) in a reasonable amount of time. FIG. 4 illustrates the relationship between V.sub.DS and programming time in the method of the present invention. FIG. 4 also illustrates that, in order to obtain programming time of less than 10 .mu.sec with a V.sub.BS of -3 volts, a V.sub.DS of at least about 3.75 volts is required. Programming with the CHISEL process of the present invention at V.sub.DS of 3.75 volts and a VBs of -3 volts is more than one-hundred times faster than programming with a non-CHISEL process (V.sub.BS =0 volts) at V.sub.DS of 3.75 volts.

Although faster programming times are achieved with higher V.sub.DS, V.sub.DS is limited by the fact that substrate leakage increases with increasing V.sub.DS. Band to band tunneling leakage currents from the drain-substrate junction increase exponentially with V.sub.DS. These leakage currents become difficult to support in large memory arrays. For example, in order to achieve the negative V.sub.BS required for CHISEL programming the substrate is charge-pumped. Charge-pumping the substrate is made more difficult with increased substrate leakage current. Furthermore, since increased drain-tub leakage currents also increase the bit-line series resistance drop, the larger the leakage current is, the larger the required bit-line voltage will have to be to achieve the desired V.sub.DS. Also, an increase in V.sub.DS also increases the substrate leakage current from impact ionizing channel electrons. As the channel-initiated current increases, so does the oxide damage from hot electrons and hot holes. This substrate leakage current is large enough when programming with CHEI to damage the oxide. In CHISEL, a V.sub.DS of less than about 4 volts provides sufficiently low drain-substrate leakage (<about 10 nA/cell) to avoid the problems described above.

In CHISEL, V.sub.DS is limited to less than 5 volts because of disturbs. A disturb is the erroneous programming of a partially selected cell (high bit-line drain voltage by low word line gate voltage) in a memory array. With increasing VDS, the drain-substrate leakage current that injects holes in the substrate, thereby generating secondary electrons, also increases. When V.sub.BS is less than zero as in CHISEL programming, a leakage-initiated parasitic ionization feedback results that has the potential to program the partially selected cell. The larger the V.sub.DS is, the larger the disturb effect is. Therefore, the larger the V.sub.DS is, the smaller the difference is between the time it takes a fully selected cell to program and the time it takes a partially selected cell to program. The desired difference (the time it takes a partially selected cell to program is advantageously on the order of 1.times.10.sup.5 larger than the time it takes to program a fully selected cell) is obtained when V.sub.BS is less negative than about -4 volts and V.sub.DS is less than about 5 volts.

In order for a cell to be effectively programmed by CHISEL it is advantageous if V.sub.BS is in the range of about -5 volts to about -4 volts. In order to provide an advantageous margin between the programming time and the disturb time, it is advantageous if V.sub.BS is about -0.5 volts to about -3 volts.

After the devices have been programmed to the desired logic state, the information stored in the memory can be accessed by addressing one or more devices. A device is addressed by applying certain reading biases. In a binary array the device reads as "on" if the threshold voltage of the device is below the read V.sub.CS and "off" if its threshold voltage is above the read V.sub.CS. In a binary array, an on device is a logic zero and an off device is a logic one. In a multi-state memory, the state is read by comparing read I.sub.DS at different levels of V.sub.CS.

CHISEL devices are programmed or written under certain prescribed conditions which require a negative substrate bias. However, when these devices are read, it is advantageous if the substrate bias applied to the devices is zero. When the substrate bias is zero during read, a "read disturb" is less likely. A read disturb is a condition whereby the charge on the floating gate of a device in the array is changed when that device or another device in the array is read. It is advantageous if the device is read under the following conditions: 0<V.sub.CS <5 V; V.sub.BS =0 V; and V.sub.DS <1.2 V.

One advantage of the present invention is that V.sub.CS is selected to provide a desired threshold voltage. In the embodiment of the present invention wherein the cell is a stacked gate cell in a NOR array, one example of a desired V.sub.TH-RD-0 is about 3 volts. In this embodiment, the device programmed to a V.sub.TH-RD-0 of about 3 volts is read using a V.sub.CS of about 3 volts (and the other read conditions prescribed above). Another example of a desired V.sub.TH-RD-0 for such stacked gate cells is about 1.8 volts. In this embodiment, the device programmed to a V.sub.TH-RD-0 of about 1.8 volts is read using a V.sub.CS of about 1.8 volts (and the other read conditions prescribed above). The examples used to illustrate the invention are not intended by way of limitation, except within the spirit and scope of the appended claims.

Claims

1. A method for charging a floating gate of an n-channel memory cell having a source, drain, control gate, floating gate, and a substrate comprising:

applying a voltage to the drain terminal of the cell to affect a positive bias of less than about 4.5 volts between the drain and the source (V.sub.DS);

applying a voltage to the control gate terminal of the cell to affect a positive bias of about 10 volts or less between the control gate and the source (V.sub.CS) wherein the control gate voltage is selected to provide the device with a desired threshold voltage and;

applying a negative voltage to the substrate to effect a negative bias of about -0.5 volts to about -4 volts between the substrate and the source (V.sub.BS) wherein the current that charges the floating gate is initiated by the electron current from the source to the drain.

2. The method of claim 1 wherein V.sub.DS is selected to program the device in about 100 .mu.sec or less.

3. The method of claim 1 wherein V.sub.DS is less than about 4 volts and is selected to program the device in about 10 .mu.sec or less.

4. The method of claim 1 wherein V.sub.DS is selected to program the device in about 1 .mu.second.

5. The method of claim 2 wherein V.sub.DS is less than about 3.5 volts.

6. The method of claim 5 wherein the V.sub.BS is about -0.5 volts to about -3 volts.

7. The method of claim 1 wherein the charged cell is read by:

applying a voltage to the control gate terminal of the cell to effect a positive bias of greater than about zero volts but less than about 5 volts;

applying a voltage to the drain terminal of the cell to affect a positive bias of less than about 1.2 volts between the drain and the source; and

maintaining about a zero voltage bias between the substrate and the source.

8. The method of claim 1 wherein V.sub.CS is increased when charging the floating gate and wherein at all times (t) during charging V.sub.CS (t) is greater than V.sub.TH (t).

9. The method of claim 1 wherein a plurality of cells in an array of cells are programmed to a first logic state, V.sub.TH-RD-0 and a second logic state, V.sub.TH-RD-1, and wherein the V.sub.CS used to program the cells to V.sub.TH-RD-0 is less than about 5 volts and the V.sub.CS used to program the cells to V.sub.TH-RD-1 is less than about 5 volts.

10. The method of claim 9 wherein the n-channel memory cell is a stacked-gate memory cell in a NOR array and wherein the V.sub.CS used to program the cells to V.sub.TH-RD-0 is selected to provide a V.sub.TH-RD-0 that is less than or equal to about 3 volts.

11. The method of claim 10 wherein the V.sub.CS used to program the cells to V.sub.TH-RD-0 is selected to provide a V.sub.TH-RD-0 that is less than or equal to about 1.8 volts.

12. The method of claim 10 wherein the charged cell is read by:

applying a voltage to the control gate terminal of the cell to affect a positive bias of about 3 volts;

applying a voltage to the drain terminal of the cell to effect a positive bias of less than about 1.2 volts between the drain and the source; and

maintaining about a zero voltage bias between the substrate and the source.

13. The method of claim 11 wherein the charged cell is read by:

applying a voltage to the control gate terminal of the cell to effect a positive bias of about 1.8 volts;

applying a voltage to the drain terminal of the cell to effect a positive bias of less than about 1.2 volts between the drain and the source; and

maintaining about a zero voltage bias between the substrate and the source.

14. The method of claim 1 wherein the selected V.sub.CS is predetermined.

15. The method of claim 1 wherein V.sub.CS is selected by reading the cell and selecting a V.sub.CS that will provide the desired threshold voltage.

16. A method for charging a floating gate of an n-channel memory cell having a source, drain, control gate, floating gate, and a substrate comprising:

applying a voltage to the drain terminal of the cell to effect a positive bias of less than about 4.5 volts between the drain and the source (V.sub.DS);

applying a voltage to the control gate terminal of the cell to effect a positive bias of about 10 volts or less between the control gate and the source (V.sub.CS) and;

applying a negative voltage to the substrate to effect a negative bias of about -0.5 volts to about -4 volts between the substrate and the source (V.sub.BS) wherein the current that charges the floating gate is initiated by the electron current from the source to the drain.

17. The method of claim 16 wherein V.sub.DS is selected to program the device in about 100 .mu.sec or less.

18. The method of claim 16 wherein V.sub.DS is less than about 4 volts and is selected to program the device in about 10 .mu.sec or less.

19. The method of claim 16 wherein V.sub.DS is selected to program the device in about 1 .mu.second.

20. The method of claim 17 wherein V.sub.DS is less than about 3.5 volts.

21. The method of claim 20 wherein the V.sub.BS is about -0.5 volts to about -3 volts.

22. The method of claim 16 wherein the control gate voltage is selected to provide the device with a desired threshold voltage.

23. The method of claim 22 wherein V.sub.CS is increased when charging the floating gate and wherein at all times (t) during programming V.sub.CS(t) is greater than V.sub.TH(t).

24. The method of claim 23 wherein a plurality of cells in an array of cells are programmed to a first logic state, V.sub.TH-RD-0 and a second logic state, V.sub.TH-RD-1, and wherein the V.sub.CS used to program the cells to V.sub.TH-RD-0 is less than about 5 volts and the V.sub.CS used to program the cells to V.sub.TH-RD-1 is less than about 5 volts.

25. The method of claim 1 wherein the n-channel memory cell is a stacked gate memory cell.

26. The method of claim 25 wherein the stacked gate memory cell is in a NOR array.